OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [sw/] [gcc-zippatch.patch] - Diff between revs 200 and 202

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Rev 200 Rev 202
Line 1... Line 1...
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/config.sub gcc-5.3.0-zip/config.sub
diff -Naur '--exclude=*.swp' gcc-6.2.0/config.sub gcc-6.2.0-zip/config.sub
--- gcc-5.3.0-original/config.sub       2015-01-02 04:30:21.000000000 -0500
--- gcc-6.2.0/config.sub        2015-12-31 16:13:28.000000000 -0500
+++ gcc-5.3.0-zip/config.sub    2016-01-30 12:27:56.023073747 -0500
+++ gcc-6.2.0-zip/config.sub    2017-01-11 11:07:21.116065311 -0500
@@ -316,7 +316,7 @@
@@ -355,6 +355,14 @@
        | visium \
        xscaleel)
        | we32k \
                basic_machine=armel-unknown
        | x86 | xc16x | xstormy16 | xtensa \
 
-       | z8k | z80)
 
+       | z8k | z80 | zip)
 
                basic_machine=$basic_machine-unknown
 
                ;;
                ;;
        c54x)
+       zip-*-linux*)
@@ -1547,6 +1547,9 @@
+               basic_machine=zip
 # system, and we'll never get to this point.
+               os=-linux
 
 
 case $basic_machine in
 
+       zip-*)
 
+               os=-elf
 
+               ;;
+               ;;
        score-*)
+       zip*)
                os=-elf
+               basic_machine=zip-unknown
 
+               os=-none
 
+               ;;
 
 
 
        # We use `pc' rather than `unknown'
 
        # because (1) that's what they normally are, and
 
diff -Naur '--exclude=*.swp' gcc-6.2.0/configure gcc-6.2.0-zip/configure
 
--- gcc-6.2.0/configure 2016-03-17 18:54:19.000000000 -0400
 
+++ gcc-6.2.0-zip/configure     2017-02-06 21:54:22.244807700 -0500
 
@@ -3548,6 +3548,44 @@
 
   ft32-*-*)
 
     noconfigdirs="$noconfigdirs ${libgcj}"
 
     ;;
 
+  zip*)
 
+    noconfigdirs="$noconfigdirs ${libgcj}"
 
+    noconfigdirs="$noconfigdirs target-boehm-gc"
 
+    noconfigdirs="$noconfigdirs target-libgfortran"
 
+    # noconfigdirs="$noconfigdirs target-libsanitizer"
 
+    # noconfigdirs="$noconfigdirs target-libada"
 
+    # noconfigdirs="$noconfigdirs target-libatomic"
 
+    # noconfigdirs="$noconfigdirs target-libcilkrts"
 
+    # noconfigdirs="$noconfigdirs target-libitm"
 
+    # noconfigdirs="$noconfigdirs target-libquadmath"
 
+    # noconfigdirs="$noconfigdirs target-libstdc++-v3"
 
+    # noconfigdirs="$noconfigdirs target-libssp"
 
+    # noconfigdirs="$noconfigdirs target-libgo"
 
+    # noconfigdirs="$noconfigdirs target-libgomp"
 
+    # noconfigdirs="$noconfigdirs target-libvtv"
 
+    # noconfigdirs="$noconfigdirs target-libobjc"
 
+       # target-libgcc
 
+       #       target-liboffloadmic
 
+       #       target-libmpx   # Only gets enabled by request
 
+       #       target-libbacktrace
 
+       #       ${libgcj}
 
+       #       target-boehm-gc
 
+       #       target-libada
 
+       #       target-libatomic
 
+       #       target-libcilkrts
 
+       #       target-libgfortran
 
+       #       target-libgo
 
+       #       target-libgomp
 
+       #       target-libitm
 
+       #       target-libobjc
 
+       #       target-libquadmath
 
+       #       target-libsanitizer
 
+       #       target-libstdc++-v3
 
+       #       target-libssp
 
+       #       target-libvtv
 
+       # target-libgloss
 
+       # target-newlib
 
+    ;;
 
   *-*-lynxos*)
 
     noconfigdirs="$noconfigdirs ${libgcj}"
                ;;
                ;;
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/configure gcc-5.3.0-zip/configure
@@ -3575,6 +3613,9 @@
--- gcc-5.3.0-original/configure        2015-05-03 13:29:57.000000000 -0400
     *-*-aix*)
+++ gcc-5.3.0-zip/configure     2016-01-30 16:19:48.264867231 -0500
        noconfigdirs="$noconfigdirs target-libgo"
@@ -3927,6 +3927,8 @@
        ;;
 
+    zip*)
 
+       noconfigdirs="$noconfigdirs target-libgo"
 
+       ;;
 
     esac
 
 fi
 
 
 
@@ -3971,6 +4012,9 @@
   vax-*-*)
   vax-*-*)
     noconfigdirs="$noconfigdirs target-newlib target-libgloss"
     noconfigdirs="$noconfigdirs target-newlib target-libgloss"
     ;;
     ;;
+  zip*)
+  zip*)
+    noconfigdirs="$noconfigdirs target-libffi target-boehm-gc gdb gprof"
+    noconfigdirs="$noconfigdirs target-libffi target-boehm-gc gdb gprof"
 
+    ;;
 esac
 esac
 
 
 # If we aren't building newlib, then don't build libgloss, since libgloss
 # If we aren't building newlib, then don't build libgloss, since libgloss
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/configure.ac gcc-5.3.0-zip/configure.ac
@@ -6785,16 +6829,16 @@
--- gcc-5.3.0-original/configure.ac     2015-05-03 13:29:57.000000000 -0400
 # CFLAGS_FOR_TARGET and CXXFLAGS_FOR_TARGET.
+++ gcc-5.3.0-zip/configure.ac  2016-02-12 10:47:23.847194843 -0500
 if test "x$CFLAGS_FOR_TARGET" = x; then
@@ -1274,6 +1274,10 @@
   if test "x${is_cross_compiler}" = xyes; then
 
-    CFLAGS_FOR_TARGET="-g -O2"
 
+    CFLAGS_FOR_TARGET="-O3"
 
   else
 
     CFLAGS_FOR_TARGET=$CFLAGS
 
     case " $CFLAGS " in
 
-      *" -O2 "*) ;;
 
-      *) CFLAGS_FOR_TARGET="-O2 $CFLAGS_FOR_TARGET" ;;
 
+      *" -O3 "*) ;;
 
+      *) CFLAGS_FOR_TARGET="-O3 $CFLAGS_FOR_TARGET" ;;
 
     esac
 
     case " $CFLAGS " in
 
       *" -g "* | *" -g3 "*) ;;
 
-      *) CFLAGS_FOR_TARGET="-g $CFLAGS_FOR_TARGET" ;;
 
+      *) CFLAGS_FOR_TARGET="$CFLAGS_FOR_TARGET" ;;
 
     esac
 
   fi
 
 fi
 
@@ -6802,16 +6846,16 @@
 
 
 
 if test "x$CXXFLAGS_FOR_TARGET" = x; then
 
   if test "x${is_cross_compiler}" = xyes; then
 
-    CXXFLAGS_FOR_TARGET="-g -O2"
 
+    CXXFLAGS_FOR_TARGET="-O3"
 
   else
 
     CXXFLAGS_FOR_TARGET=$CXXFLAGS
 
     case " $CXXFLAGS " in
 
-      *" -O2 "*) ;;
 
-      *) CXXFLAGS_FOR_TARGET="-O2 $CXXFLAGS_FOR_TARGET" ;;
 
+      *" -O3 "*) ;;
 
+      *) CXXFLAGS_FOR_TARGET="-O3 $CXXFLAGS_FOR_TARGET" ;;
 
     esac
 
     case " $CXXFLAGS " in
 
       *" -g "* | *" -g3 "*) ;;
 
-      *) CXXFLAGS_FOR_TARGET="-g $CXXFLAGS_FOR_TARGET" ;;
 
+      *) CXXFLAGS_FOR_TARGET="$CXXFLAGS_FOR_TARGET" ;;
 
     esac
 
   fi
 
 fi
 
diff -Naur '--exclude=*.swp' gcc-6.2.0/configure.ac gcc-6.2.0-zip/configure.ac
 
--- gcc-6.2.0/configure.ac      2016-03-17 18:54:19.000000000 -0400
 
+++ gcc-6.2.0-zip/configure.ac  2017-01-10 12:43:23.819301273 -0500
 
@@ -884,6 +884,9 @@
 
   ft32-*-*)
 
     noconfigdirs="$noconfigdirs ${libgcj}"
 
     ;;
 
+  zip*)
 
+    noconfigdirs="$noconfigdirs ${libgcj}"
 
+    ;;
 
   *-*-lynxos*)
 
     noconfigdirs="$noconfigdirs ${libgcj}"
 
     ;;
 
@@ -911,6 +914,9 @@
 
     *-*-aix*)
 
        noconfigdirs="$noconfigdirs target-libgo"
 
        ;;
 
+    zip*)
 
+       noconfigdirs="$noconfigdirs target-libgo"
 
+       ;;
 
     esac
 
 fi
 
 
 
@@ -1307,6 +1313,10 @@
   vax-*-*)
   vax-*-*)
     noconfigdirs="$noconfigdirs target-newlib target-libgloss"
     noconfigdirs="$noconfigdirs target-newlib target-libgloss"
     ;;
     ;;
+  zip*)
+  zip*)
+    noconfigdirs="$noconfigdirs target-libffi target-boehm-gc gdb gprof"
+    noconfigdirs="$noconfigdirs target-libffi target-boehm-gc gdb gprof ${libgcj}"
+    unsupported_languages="$unsupported_languages fortran java"
+    unsupported_languages="$unsupported_languages fortran"
+    ;;
+    ;;
 esac
 esac
 
 
 # If we aren't building newlib, then don't build libgloss, since libgloss
 # If we aren't building newlib, then don't build libgloss, since libgloss
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/cfgexpand.c gcc-5.3.0-zip/gcc/cfgexpand.c
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/cfgexpand.c gcc-6.2.0-zip/gcc/cfgexpand.c
--- gcc-5.3.0-original/gcc/cfgexpand.c  2015-07-23 06:39:26.000000000 -0400
--- gcc-6.2.0/gcc/cfgexpand.c   2016-04-27 08:23:50.000000000 -0400
+++ gcc-5.3.0-zip/gcc/cfgexpand.c       2016-04-01 06:40:17.288326711 -0400
+++ gcc-6.2.0-zip/gcc/cfgexpand.c       2016-12-31 16:38:36.195534819 -0500
@@ -108,6 +108,14 @@
@@ -74,6 +74,15 @@
 #include "tree-chkp.h"
 #include "tree-chkp.h"
 #include "rtl-chkp.h"
 #include "rtl-chkp.h"
 
 
 
+
+#ifdef DO_ZIP_DEBUGS
+#ifdef DO_ZIP_DEBUGS
+#include <stdio.h>
+#include <stdio.h>
+#define ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
+#define        ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s;%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
+extern void    zip_debug_rtx(const_rtx);
+extern void    zip_debug_rtx(const_rtx);
+#else
+#else
+#define        ZIP_DEBUG_LINE(STR,RTX)
+#define        ZIP_DEBUG_LINE(STR,RTX)
+#endif
+#endif
+
+
 /* Some systems use __main in a way incompatible with its use in gcc, in these
 /* Some systems use __main in a way incompatible with its use in gcc, in these
    cases use the macros NAME__MAIN to give a quoted symbol and SYMBOL__MAIN to
    cases use the macros NAME__MAIN to give a quoted symbol and SYMBOL__MAIN to
    give the same symbol without quotes for an alternative entry point.  You
    give the same symbol without quotes for an alternative entry point.  You
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/cgraphbuild.c gcc-5.3.0-zip/gcc/cgraphbuild.c
@@ -1172,7 +1181,7 @@
--- gcc-5.3.0-original/gcc/cgraphbuild.c        2015-01-09 15:18:42.000000000 -0500
                base_align = crtl->max_used_stack_slot_alignment;
+++ gcc-5.3.0-zip/gcc/cgraphbuild.c     2016-03-24 22:13:24.815287808 -0400
              else
@@ -62,6 +62,13 @@
                base_align = MAX (crtl->max_used_stack_slot_alignment,
 #include "ipa-prop.h"
-                                 GET_MODE_ALIGNMENT (SImode)
 #include "ipa-inline.h"
+                                 GET_MODE_ALIGNMENT (word_mode)
 
                                  << ASAN_SHADOW_SHIFT);
 
            }
 
          else
 
@@ -2225,7 +2234,7 @@
 
          data.asan_vec.safe_push (offset);
 
          /* Leave space for alignment if STRICT_ALIGNMENT.  */
 
          if (STRICT_ALIGNMENT)
 
-           alloc_stack_frame_space ((GET_MODE_ALIGNMENT (SImode)
 
+           alloc_stack_frame_space ((GET_MODE_ALIGNMENT (word_mode)
 
                                      << ASAN_SHADOW_SHIFT)
 
                                     / BITS_PER_UNIT, 1);
 
 
 
@@ -5745,7 +5754,7 @@
 
       && (last = get_last_insn ())
 
       && JUMP_P (last))
 
     {
 
-      rtx dummy = gen_reg_rtx (SImode);
 
+      rtx dummy = gen_reg_rtx (word_mode);
 
       emit_insn_after_noloc (gen_move_insn (dummy, dummy), last, NULL);
 
     }
 
 
 
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/cgraphbuild.c gcc-6.2.0-zip/gcc/cgraphbuild.c
 
--- gcc-6.2.0/gcc/cgraphbuild.c 2016-01-04 09:30:50.000000000 -0500
 
+++ gcc-6.2.0-zip/gcc/cgraphbuild.c     2016-12-31 16:39:44.963107994 -0500
 
@@ -32,6 +32,15 @@
 
 #include "ipa-utils.h"
 
 #include "except.h"
 
 
 
+
+#ifdef DO_ZIP_DEBUGS
+#ifdef DO_ZIP_DEBUGS
 
+#include <stdio.h>
 
+#define        ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s;%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
+extern void zip_debug_rtx(const_rtx);
+extern void zip_debug_rtx(const_rtx);
+#define        ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
 
+#else
+#else
+#define        ZIP_DEBUG_LINE(STR,RTX)
+#define        ZIP_DEBUG_LINE(STR,RTX)
+#endif
+#endif
+
+
 /* Context of record_reference.  */
 /* Context of record_reference.  */
 struct record_reference_ctx
 struct record_reference_ctx
 {
 {
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/common/config/zip/zip-common.c gcc-5.3.0-zip/gcc/common/config/zip/zip-common.c
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/combine.c gcc-6.2.0-zip/gcc/combine.c
--- gcc-5.3.0-original/gcc/common/config/zip/zip-common.c       1969-12-31 19:00:00.000000000 -0500
--- gcc-6.2.0/gcc/combine.c     2016-08-08 06:06:15.000000000 -0400
+++ gcc-5.3.0-zip/gcc/common/config/zip/zip-common.c    2016-02-14 00:54:31.821055716 -0500
+++ gcc-6.2.0-zip/gcc/combine.c 2017-02-03 09:25:19.676720321 -0500
 
@@ -103,6 +103,15 @@
 
 #include "rtl-iter.h"
 
 #include "print-rtl.h"
 
 
 
+#define        DO_ZIP_DEBUGS
 
+#ifdef DO_ZIP_DEBUGS
 
+#include <stdio.h>
 
+#define        ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
 
+extern void    zip_debug_rtx(const_rtx);
 
+#else
 
+#define        ZIP_DEBUG_LINE(STR,RTX)
 
+#endif
 
+
 
 #ifndef LOAD_EXTEND_OP
 
 #define LOAD_EXTEND_OP(M) UNKNOWN
 
 #endif
 
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/common/config/zip/zip-common.c gcc-6.2.0-zip/gcc/common/config/zip/zip-common.c
 
--- gcc-6.2.0/gcc/common/config/zip/zip-common.c        1969-12-31 19:00:00.000000000 -0500
 
+++ gcc-6.2.0-zip/gcc/common/config/zip/zip-common.c    2017-01-11 09:41:34.483106099 -0500
@@ -0,0 +1,52 @@
@@ -0,0 +1,52 @@
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+//
+//
+// Filename:   common/config/zip/zip-common.c
+// Filename:   common/config/zip/zip-common.c
+//
+//
Line 96... Line 259...
+// Creator:    Dan Gisselquist, Ph.D.
+// Creator:    Dan Gisselquist, Ph.D.
+//             Gisselquist Technology, LLC
+//             Gisselquist Technology, LLC
+//
+//
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+//
+//
+// Copyright (C) 2016, Gisselquist Technology, LLC
+// Copyright (C) 2016-2017, Gisselquist Technology, LLC
+//
+//
+// This program is free software (firmware): you can redistribute it and/or
+// This program is free software (firmware): you can redistribute it and/or
+// modify it under the terms of  the GNU General Public License as published
+// modify it under the terms of  the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or (at
+// by the Free Software Foundation, either version 3 of the License, or (at
+// your option) any later version.
+// your option) any later version.
Line 135... Line 298...
+
+
+#undef TARGET_OPTION_OPTIMIZATION_TABLE
+#undef TARGET_OPTION_OPTIMIZATION_TABLE
+#define        TARGET_OPTION_OPTIMIZATION_TABLE        zip_option_optimization_table
+#define        TARGET_OPTION_OPTIMIZATION_TABLE        zip_option_optimization_table
+
+
+struct gcc_targetm_common      targetm_common = TARGETM_COMMON_INITIALIZER;
+struct gcc_targetm_common      targetm_common = TARGETM_COMMON_INITIALIZER;
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h gcc-5.3.0-zip/gcc/config/aarch64/aarch64-linux.h
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/genzipops.c gcc-6.2.0-zip/gcc/config/zip/genzipops.c
--- gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h       2016-11-28 18:14:19.382586425 -0500
--- gcc-6.2.0/gcc/config/zip/genzipops.c        1969-12-31 19:00:00.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/aarch64/aarch64-linux.h    2015-07-24 12:00:26.000000000 -0400
+++ gcc-6.2.0-zip/gcc/config/zip/genzipops.c    2017-03-07 12:03:59.062584503 -0500
@@ -21,7 +21,7 @@
@@ -0,0 +1,444 @@
 #ifndef GCC_AARCH64_LINUX_H
 
 #define GCC_AARCH64_LINUX_H
 
 
 
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
 
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
 
 
 
 #undef  ASAN_CC1_SPEC
 
 #define ASAN_CC1_SPEC "%{%:sanitize(address):-funwind-tables}"
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/alpha/linux-elf.h gcc-5.3.0-zip/gcc/config/alpha/linux-elf.h
 
--- gcc-5.3.0-original/gcc/config/alpha/linux-elf.h     2016-11-28 18:14:19.382586425 -0500
 
+++ gcc-5.3.0-zip/gcc/config/alpha/linux-elf.h  2015-01-05 07:33:28.000000000 -0500
 
@@ -23,8 +23,8 @@
 
 #define EXTRA_SPECS \
 
 { "elf_dynamic_linker", ELF_DYNAMIC_LINKER },
 
 
 
-#define GLIBC_DYNAMIC_LINKER   "/tools/lib/ld-linux.so.2"
 
-#define UCLIBC_DYNAMIC_LINKER "/tools/lib/ld-uClibc.so.0"
 
+#define GLIBC_DYNAMIC_LINKER   "/lib/ld-linux.so.2"
 
+#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
 
 #if DEFAULT_LIBC == LIBC_UCLIBC
 
 #define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
 
 #elif DEFAULT_LIBC == LIBC_GLIBC
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/arm/linux-eabi.h gcc-5.3.0-zip/gcc/config/arm/linux-eabi.h
 
--- gcc-5.3.0-original/gcc/config/arm/linux-eabi.h      2016-11-28 18:14:19.382586425 -0500
 
+++ gcc-5.3.0-zip/gcc/config/arm/linux-eabi.h   2015-01-05 07:33:28.000000000 -0500
 
@@ -68,8 +68,8 @@
 
    GLIBC_DYNAMIC_LINKER_DEFAULT and TARGET_DEFAULT_FLOAT_ABI.  */
 
 
 
 #undef  GLIBC_DYNAMIC_LINKER
 
-#define GLIBC_DYNAMIC_LINKER_SOFT_FLOAT "/tools/lib/ld-linux.so.3"
 
-#define GLIBC_DYNAMIC_LINKER_HARD_FLOAT "/tools/lib/ld-linux-armhf.so.3"
 
+#define GLIBC_DYNAMIC_LINKER_SOFT_FLOAT "/lib/ld-linux.so.3"
 
+#define GLIBC_DYNAMIC_LINKER_HARD_FLOAT "/lib/ld-linux-armhf.so.3"
 
 #define GLIBC_DYNAMIC_LINKER_DEFAULT GLIBC_DYNAMIC_LINKER_SOFT_FLOAT
 
 
 
 #define GLIBC_DYNAMIC_LINKER \
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/arm/linux-elf.h gcc-5.3.0-zip/gcc/config/arm/linux-elf.h
 
--- gcc-5.3.0-original/gcc/config/arm/linux-elf.h       2016-11-28 18:14:19.382586425 -0500
 
+++ gcc-5.3.0-zip/gcc/config/arm/linux-elf.h    2015-06-23 05:26:54.000000000 -0400
 
@@ -62,7 +62,7 @@
 
 
 
 #define LIBGCC_SPEC "%{mfloat-abi=soft*:-lfloat} -lgcc"
 
 
 
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2"
 
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
 
 
 
 #define LINUX_TARGET_LINK_SPEC  "%{h*} \
 
    %{static:-Bstatic} \
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/bfin/linux.h gcc-5.3.0-zip/gcc/config/bfin/linux.h
 
--- gcc-5.3.0-original/gcc/config/bfin/linux.h  2016-11-28 18:14:19.382586425 -0500
 
+++ gcc-5.3.0-zip/gcc/config/bfin/linux.h       2015-01-05 07:33:28.000000000 -0500
 
@@ -45,7 +45,7 @@
 
   %{shared:-G -Bdynamic} \
 
   %{!shared: %{!static: \
 
    %{rdynamic:-export-dynamic} \
 
-   -dynamic-linker /tools/lib/ld-uClibc.so.0} \
 
+   -dynamic-linker /lib/ld-uClibc.so.0} \
 
    %{static}} -init __init -fini __fini"
 
 
 
 #undef TARGET_SUPPORTS_SYNC_CALLS
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/cris/linux.h gcc-5.3.0-zip/gcc/config/cris/linux.h
 
--- gcc-5.3.0-original/gcc/config/cris/linux.h  2016-11-28 18:14:19.382586425 -0500
 
+++ gcc-5.3.0-zip/gcc/config/cris/linux.h       2015-01-05 07:33:28.000000000 -0500
 
@@ -102,7 +102,7 @@
 
 #undef CRIS_DEFAULT_CPU_VERSION
 
 #define CRIS_DEFAULT_CPU_VERSION CRIS_CPU_NG
 
 
 
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
 
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
 
 
 
 #undef CRIS_LINK_SUBTARGET_SPEC
 
 #define CRIS_LINK_SUBTARGET_SPEC \
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/freebsd-spec.h gcc-5.3.0-zip/gcc/config/freebsd-spec.h
 
--- gcc-5.3.0-original/gcc/config/freebsd-spec.h        2016-11-28 18:14:19.382586425 -0500
 
+++ gcc-5.3.0-zip/gcc/config/freebsd-spec.h     2015-06-25 13:53:14.000000000 -0400
 
@@ -129,9 +129,9 @@
 
 #endif
 
 
 
 #if FBSD_MAJOR < 6
 
-#define FBSD_DYNAMIC_LINKER "/tools/libexec/ld-elf.so.1"
 
+#define FBSD_DYNAMIC_LINKER "/usr/libexec/ld-elf.so.1"
 
 #else
 
-#define FBSD_DYNAMIC_LINKER "/tools/libexec/ld-elf.so.1"
 
+#define FBSD_DYNAMIC_LINKER "/libexec/ld-elf.so.1"
 
 #endif
 
 
 
 /* NOTE: The freebsd-spec.h header is included also for various
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/frv/linux.h gcc-5.3.0-zip/gcc/config/frv/linux.h
 
--- gcc-5.3.0-original/gcc/config/frv/linux.h   2016-11-28 18:14:19.382586425 -0500
 
+++ gcc-5.3.0-zip/gcc/config/frv/linux.h        2015-01-05 07:33:28.000000000 -0500
 
@@ -34,7 +34,7 @@
 
 #define ENDFILE_SPEC \
 
   "%{shared|pie:crtendS.o%s;:crtend.o%s} crtn.o%s"
 
 
 
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
 
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
 
 
 
 #undef LINK_SPEC
 
 #define LINK_SPEC "\
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/gnu.h gcc-5.3.0-zip/gcc/config/i386/gnu.h
 
--- gcc-5.3.0-original/gcc/config/i386/gnu.h    2016-11-28 18:14:19.382586425 -0500
 
+++ gcc-5.3.0-zip/gcc/config/i386/gnu.h 2015-01-05 07:33:28.000000000 -0500
 
@@ -22,7 +22,7 @@
 
 #define GNU_USER_LINK_EMULATION "elf_i386"
 
 
 
 #undef GNU_USER_DYNAMIC_LINKER
 
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so"
 
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so"
 
 
 
 #undef STARTFILE_SPEC
 
 #if defined HAVE_LD_PIE
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu64.h
 
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h 2016-11-28 18:14:19.386586394 -0500
 
+++ gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu64.h      2015-01-05 07:33:28.000000000 -0500
 
@@ -22,6 +22,6 @@
 
 #define GNU_USER_LINK_EMULATION64 "elf_x86_64_fbsd"
 
 #define GNU_USER_LINK_EMULATIONX32 "elf32_x86_64_fbsd"
 
 
 
-#define GLIBC_DYNAMIC_LINKER32 "/tools/lib/ld.so.1"
 
-#define GLIBC_DYNAMIC_LINKER64 "/tools/lib/ld-kfreebsd-x86-64.so.1"
 
-#define GLIBC_DYNAMIC_LINKERX32 "/tools/lib/ld-kfreebsd-x32.so.1"
 
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1"
 
+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld-kfreebsd-x86-64.so.1"
 
+#define GLIBC_DYNAMIC_LINKERX32 "/lib/ld-kfreebsd-x32.so.1"
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu.h
 
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h   2016-11-28 18:14:19.386586394 -0500
 
+++ gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu.h        2015-01-05 07:33:28.000000000 -0500
 
@@ -19,4 +19,4 @@
 
 <http://www.gnu.org/licenses/>.  */
 
 
 
 #define GNU_USER_LINK_EMULATION "elf_i386_fbsd"
 
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
 
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/linux64.h gcc-5.3.0-zip/gcc/config/i386/linux64.h
 
--- gcc-5.3.0-original/gcc/config/i386/linux64.h        2016-11-28 18:14:19.386586394 -0500
 
+++ gcc-5.3.0-zip/gcc/config/i386/linux64.h     2015-01-05 07:33:28.000000000 -0500
 
@@ -27,6 +27,6 @@
 
 #define GNU_USER_LINK_EMULATION64 "elf_x86_64"
 
 #define GNU_USER_LINK_EMULATIONX32 "elf32_x86_64"
 
 
 
-#define GLIBC_DYNAMIC_LINKER32 "/tools/lib/ld-linux.so.2"
 
-#define GLIBC_DYNAMIC_LINKER64 "/tools/lib64/ld-linux-x86-64.so.2"
 
-#define GLIBC_DYNAMIC_LINKERX32 "/tools/libx32/ld-linux-x32.so.2"
 
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2"
 
+#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux-x86-64.so.2"
 
+#define GLIBC_DYNAMIC_LINKERX32 "/libx32/ld-linux-x32.so.2"
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/linux.h gcc-5.3.0-zip/gcc/config/i386/linux.h
 
--- gcc-5.3.0-original/gcc/config/i386/linux.h  2016-11-28 18:14:19.386586394 -0500
 
+++ gcc-5.3.0-zip/gcc/config/i386/linux.h       2015-01-05 07:33:28.000000000 -0500
 
@@ -20,4 +20,4 @@
 
 <http://www.gnu.org/licenses/>.  */
 
 
 
 #define GNU_USER_LINK_EMULATION "elf_i386"
 
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2"
 
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/ia64/linux.h gcc-5.3.0-zip/gcc/config/ia64/linux.h
 
--- gcc-5.3.0-original/gcc/config/ia64/linux.h  2016-11-28 18:14:19.386586394 -0500
 
+++ gcc-5.3.0-zip/gcc/config/ia64/linux.h       2015-01-05 07:33:28.000000000 -0500
 
@@ -55,7 +55,7 @@
 
 /* Define this for shared library support because it isn't in the main
 
    linux.h file.  */
 
 
 
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux-ia64.so.2"
 
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-ia64.so.2"
 
 
 
 #undef LINK_SPEC
 
 #define LINK_SPEC "\
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/knetbsd-gnu.h gcc-5.3.0-zip/gcc/config/knetbsd-gnu.h
 
--- gcc-5.3.0-original/gcc/config/knetbsd-gnu.h 2016-11-28 18:14:19.386586394 -0500
 
+++ gcc-5.3.0-zip/gcc/config/knetbsd-gnu.h      2015-01-05 07:33:28.000000000 -0500
 
@@ -32,4 +32,4 @@
 
 
 
 
 
 #undef GNU_USER_DYNAMIC_LINKER
 
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so.1"
 
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1"
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h gcc-5.3.0-zip/gcc/config/kopensolaris-gnu.h
 
--- gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h    2016-11-28 18:14:19.386586394 -0500
 
+++ gcc-5.3.0-zip/gcc/config/kopensolaris-gnu.h 2015-01-05 07:33:28.000000000 -0500
 
@@ -31,5 +31,4 @@
 
   while (0)
 
 
 
 #undef GNU_USER_DYNAMIC_LINKER
 
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so.1"
 
-
 
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1"
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/linux.h gcc-5.3.0-zip/gcc/config/linux.h
 
--- gcc-5.3.0-original/gcc/config/linux.h       2016-11-28 18:14:19.386586394 -0500
 
+++ gcc-5.3.0-zip/gcc/config/linux.h    2015-01-05 07:33:28.000000000 -0500
 
@@ -73,10 +73,10 @@
 
    GLIBC_DYNAMIC_LINKER must be defined for each target using them, or
 
    GLIBC_DYNAMIC_LINKER32 and GLIBC_DYNAMIC_LINKER64 for targets
 
    supporting both 32-bit and 64-bit compilation.  */
 
-#define UCLIBC_DYNAMIC_LINKER "/tools/lib/ld-uClibc.so.0"
 
-#define UCLIBC_DYNAMIC_LINKER32 "/tools/lib/ld-uClibc.so.0"
 
-#define UCLIBC_DYNAMIC_LINKER64 "/tools/lib/ld64-uClibc.so.0"
 
-#define UCLIBC_DYNAMIC_LINKERX32 "/tools/lib/ldx32-uClibc.so.0"
 
+#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
 
+#define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0"
 
+#define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0"
 
+#define UCLIBC_DYNAMIC_LINKERX32 "/lib/ldx32-uClibc.so.0"
 
 #define BIONIC_DYNAMIC_LINKER "/system/bin/linker"
 
 #define BIONIC_DYNAMIC_LINKER32 "/system/bin/linker"
 
 #define BIONIC_DYNAMIC_LINKER64 "/system/bin/linker64"
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h gcc-5.3.0-zip/gcc/config/lm32/uclinux-elf.h
 
--- gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h    2016-11-28 18:14:19.386586394 -0500
 
+++ gcc-5.3.0-zip/gcc/config/lm32/uclinux-elf.h 2015-01-05 07:33:28.000000000 -0500
 
@@ -67,7 +67,7 @@
 
    %{shared:-shared} \
 
    %{symbolic:-Bsymbolic} \
 
    %{rdynamic:-export-dynamic} \
 
-   -dynamic-linker /tools/lib/ld-linux.so.2"
 
+   -dynamic-linker /lib/ld-linux.so.2"
 
 
 
 #define TARGET_OS_CPP_BUILTINS() GNU_USER_TARGET_OS_CPP_BUILTINS()
 
 
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/m68k/linux.h gcc-5.3.0-zip/gcc/config/m68k/linux.h
 
--- gcc-5.3.0-original/gcc/config/m68k/linux.h  2016-11-28 18:14:19.386586394 -0500
 
+++ gcc-5.3.0-zip/gcc/config/m68k/linux.h       2015-01-05 07:33:28.000000000 -0500
 
@@ -71,7 +71,7 @@
 
    When the -shared link option is used a final link is not being
 
    done.  */
 
 
 
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
 
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
 
 
 
 #undef LINK_SPEC
 
 #define LINK_SPEC "-m m68kelf %{shared} \
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/microblaze/linux.h gcc-5.3.0-zip/gcc/config/microblaze/linux.h
 
--- gcc-5.3.0-original/gcc/config/microblaze/linux.h    2016-11-28 18:14:19.386586394 -0500
 
+++ gcc-5.3.0-zip/gcc/config/microblaze/linux.h 2015-05-28 10:08:19.000000000 -0400
 
@@ -28,7 +28,7 @@
 
 #undef TLS_NEEDS_GOT
 
 #define TLS_NEEDS_GOT 1
 
 
 
-#define DYNAMIC_LINKER "/tools/lib/ld.so.1"
 
+#define DYNAMIC_LINKER "/lib/ld.so.1"
 
 #undef  SUBTARGET_EXTRA_SPECS
 
 #define SUBTARGET_EXTRA_SPECS \
 
   { "dynamic_linker", DYNAMIC_LINKER }
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/mips/linux.h gcc-5.3.0-zip/gcc/config/mips/linux.h
 
--- gcc-5.3.0-original/gcc/config/mips/linux.h  2016-11-28 18:14:19.386586394 -0500
 
+++ gcc-5.3.0-zip/gcc/config/mips/linux.h       2015-01-05 07:33:28.000000000 -0500
 
@@ -22,20 +22,20 @@
 
 #define GNU_USER_LINK_EMULATIONN32 "elf32%{EB:b}%{EL:l}tsmipn32"
 
 
 
 #define GLIBC_DYNAMIC_LINKER32 \
 
-  "%{mnan=2008:/tools/lib/ld-linux-mipsn8.so.1;:/tools/lib/ld.so.1}"
 
+  "%{mnan=2008:/lib/ld-linux-mipsn8.so.1;:/lib/ld.so.1}"
 
 #define GLIBC_DYNAMIC_LINKER64 \
 
-  "%{mnan=2008:/tools/lib64/ld-linux-mipsn8.so.1;:/tools/lib64/ld.so.1}"
 
+  "%{mnan=2008:/lib64/ld-linux-mipsn8.so.1;:/lib64/ld.so.1}"
 
 #define GLIBC_DYNAMIC_LINKERN32 \
 
-  "%{mnan=2008:/tools/lib32/ld-linux-mipsn8.so.1;:/tools/lib32/ld.so.1}"
 
+  "%{mnan=2008:/lib32/ld-linux-mipsn8.so.1;:/lib32/ld.so.1}"
 
 
 
 #undef UCLIBC_DYNAMIC_LINKER32
 
 #define UCLIBC_DYNAMIC_LINKER32 \
 
-  "%{mnan=2008:/tools/lib/ld-uClibc-mipsn8.so.0;:/tools/lib/ld-uClibc.so.0}"
 
+  "%{mnan=2008:/lib/ld-uClibc-mipsn8.so.0;:/lib/ld-uClibc.so.0}"
 
 #undef UCLIBC_DYNAMIC_LINKER64
 
 #define UCLIBC_DYNAMIC_LINKER64 \
 
-  "%{mnan=2008:/tools/lib/ld64-uClibc-mipsn8.so.0;:/tools/lib/ld64-uClibc.so.0}"
 
+  "%{mnan=2008:/lib/ld64-uClibc-mipsn8.so.0;:/lib/ld64-uClibc.so.0}"
 
 #define UCLIBC_DYNAMIC_LINKERN32 \
 
-  "%{mnan=2008:/tools/lib32/ld-uClibc-mipsn8.so.0;:/tools/lib32/ld-uClibc.so.0}"
 
+  "%{mnan=2008:/lib32/ld-uClibc-mipsn8.so.0;:/lib32/ld-uClibc.so.0}"
 
 
 
 #define BIONIC_DYNAMIC_LINKERN32 "/system/bin/linker32"
 
 #define GNU_USER_DYNAMIC_LINKERN32 \
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/mn10300/linux.h gcc-5.3.0-zip/gcc/config/mn10300/linux.h
 
--- gcc-5.3.0-original/gcc/config/mn10300/linux.h       2016-11-28 18:14:19.386586394 -0500
 
+++ gcc-5.3.0-zip/gcc/config/mn10300/linux.h    2015-01-05 07:33:28.000000000 -0500
 
@@ -32,7 +32,7 @@
 
 #undef  ASM_SPEC
 
 #define ASM_SPEC ""
 
 
 
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
 
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
 
 
 
 #undef  LINK_SPEC
 
 #define LINK_SPEC "%{mrelax:--relax} %{shared:-shared} \
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/pa/pa-linux.h gcc-5.3.0-zip/gcc/config/pa/pa-linux.h
 
--- gcc-5.3.0-original/gcc/config/pa/pa-linux.h 2016-11-28 18:14:19.386586394 -0500
 
+++ gcc-5.3.0-zip/gcc/config/pa/pa-linux.h      2015-09-24 20:04:26.000000000 -0400
 
@@ -37,7 +37,7 @@
 
 /* Define this for shared library support because it isn't in the main
 
    linux.h file.  */
 
 
 
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
 
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
 
 
 
 #undef LINK_SPEC
 
 #define LINK_SPEC "\
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/rs6000/linux64.h gcc-5.3.0-zip/gcc/config/rs6000/linux64.h
 
--- gcc-5.3.0-original/gcc/config/rs6000/linux64.h      2016-11-28 18:14:19.386586394 -0500
 
+++ gcc-5.3.0-zip/gcc/config/rs6000/linux64.h   2015-03-09 19:18:57.000000000 -0400
 
@@ -357,14 +357,14 @@
 
 #undef LINK_OS_DEFAULT_SPEC
 
 #define LINK_OS_DEFAULT_SPEC "%(link_os_linux)"
 
 
 
-#define GLIBC_DYNAMIC_LINKER32 "/tools/lib/ld.so.1"
 
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1"
 
 #ifdef LINUX64_DEFAULT_ABI_ELFv2
 
-#define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv1:/tools/lib64/ld64.so.1;:/tools/lib64/ld64.so.2}"
 
+#define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv1:/lib64/ld64.so.1;:/lib64/ld64.so.2}"
 
 #else
 
-#define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv2:/tools/lib64/ld64.so.2;:/tools/lib64/ld64.so.1}"
 
+#define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv2:/lib64/ld64.so.2;:/lib64/ld64.so.1}"
 
 #endif
 
-#define UCLIBC_DYNAMIC_LINKER32 "/tools/lib/ld-uClibc.so.0"
 
-#define UCLIBC_DYNAMIC_LINKER64 "/tools/lib/ld64-uClibc.so.0"
 
+#define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0"
 
+#define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0"
 
 #if DEFAULT_LIBC == LIBC_UCLIBC
 
 #define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
 
 #elif DEFAULT_LIBC == LIBC_GLIBC
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/rs6000/sysv4.h gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h
 
--- gcc-5.3.0-original/gcc/config/rs6000/sysv4.h        2016-11-28 18:14:19.386586394 -0500
 
+++ gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h     2015-09-24 09:46:45.000000000 -0400
 
@@ -757,8 +757,8 @@
 
 
 
 #define LINK_START_LINUX_SPEC ""
 
 
 
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
 
-#define UCLIBC_DYNAMIC_LINKER "/tools/lib/ld-uClibc.so.0"
 
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
 
+#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
 
 #if DEFAULT_LIBC == LIBC_UCLIBC
 
 #define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
 
 #elif !defined (DEFAULT_LIBC) || DEFAULT_LIBC == LIBC_GLIBC
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/s390/linux.h gcc-5.3.0-zip/gcc/config/s390/linux.h
 
--- gcc-5.3.0-original/gcc/config/s390/linux.h  2016-11-28 18:14:19.386586394 -0500
 
+++ gcc-5.3.0-zip/gcc/config/s390/linux.h       2015-05-11 03:14:10.000000000 -0400
 
@@ -60,8 +60,8 @@
 
 #define MULTILIB_DEFAULTS { "m31" }
 
 #endif
 
 
 
-#define GLIBC_DYNAMIC_LINKER32 "/tools/lib/ld.so.1"
 
-#define GLIBC_DYNAMIC_LINKER64 "/tools/lib/ld64.so.1"
 
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1"
 
+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld64.so.1"
 
 
 
 #undef  LINK_SPEC
 
 #define LINK_SPEC \
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sh/linux.h gcc-5.3.0-zip/gcc/config/sh/linux.h
 
--- gcc-5.3.0-original/gcc/config/sh/linux.h    2016-11-28 18:14:19.386586394 -0500
 
+++ gcc-5.3.0-zip/gcc/config/sh/linux.h 2015-01-05 07:33:28.000000000 -0500
 
@@ -43,7 +43,7 @@
 
 
 
 #define TARGET_ASM_FILE_END file_end_indicate_exec_stack
 
 
 
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2"
 
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
 
 
 
 #undef SUBTARGET_LINK_EMUL_SUFFIX
 
 #define SUBTARGET_LINK_EMUL_SUFFIX "_linux"
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sparc/linux64.h gcc-5.3.0-zip/gcc/config/sparc/linux64.h
 
--- gcc-5.3.0-original/gcc/config/sparc/linux64.h       2016-11-28 18:14:19.386586394 -0500
 
+++ gcc-5.3.0-zip/gcc/config/sparc/linux64.h    2015-01-05 07:33:28.000000000 -0500
 
@@ -84,8 +84,8 @@
 
    When the -shared link option is used a final link is not being
 
    done.  */
 
 
 
-#define GLIBC_DYNAMIC_LINKER32 "/tools/lib/ld-linux.so.2"
 
-#define GLIBC_DYNAMIC_LINKER64 "/tools/lib64/ld-linux.so.2"
 
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2"
 
+#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux.so.2"
 
 
 
 #ifdef SPARC_BI_ARCH
 
 
 
@@ -193,7 +193,7 @@
 
 #else /* !SPARC_BI_ARCH */
 
 
 
 #undef LINK_SPEC
 
-#define LINK_SPEC "-m elf64_sparc -Y P,%R/tools/lib64 %{shared:-shared} \
 
+#define LINK_SPEC "-m elf64_sparc -Y P,%R/usr/lib64 %{shared:-shared} \
 
   %{!shared: \
 
     %{!static: \
 
       %{rdynamic:-export-dynamic} \
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sparc/linux.h gcc-5.3.0-zip/gcc/config/sparc/linux.h
 
--- gcc-5.3.0-original/gcc/config/sparc/linux.h 2016-11-28 18:14:19.386586394 -0500
 
+++ gcc-5.3.0-zip/gcc/config/sparc/linux.h      2015-01-05 07:33:28.000000000 -0500
 
@@ -83,7 +83,7 @@
 
    When the -shared link option is used a final link is not being
 
    done.  */
 
 
 
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2"
 
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
 
 
 
 #undef  LINK_SPEC
 
 #define LINK_SPEC "-m elf32_sparc %{shared:-shared} \
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/vax/linux.h gcc-5.3.0-zip/gcc/config/vax/linux.h
 
--- gcc-5.3.0-original/gcc/config/vax/linux.h   2016-11-28 18:14:19.386586394 -0500
 
+++ gcc-5.3.0-zip/gcc/config/vax/linux.h        2015-01-05 07:33:28.000000000 -0500
 
@@ -41,7 +41,7 @@
 
   %{!shared: \
 
     %{!static: \
 
       %{rdynamic:-export-dynamic} \
 
-      -dynamic-linker /tools/lib/ld.so.1} \
 
+      -dynamic-linker /lib/ld.so.1} \
 
     %{static:-static}}"
 
 
 
 #undef  WCHAR_TYPE
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/xtensa/linux.h gcc-5.3.0-zip/gcc/config/xtensa/linux.h
 
--- gcc-5.3.0-original/gcc/config/xtensa/linux.h        2016-11-28 18:14:19.386586394 -0500
 
+++ gcc-5.3.0-zip/gcc/config/xtensa/linux.h     2015-01-05 07:33:28.000000000 -0500
 
@@ -44,7 +44,7 @@
 
   %{mlongcalls:--longcalls} \
 
   %{mno-longcalls:--no-longcalls}"
 
 
 
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
 
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
 
 
 
 #undef LINK_SPEC
 
 #define LINK_SPEC \
 
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/netbsd.h gcc-5.3.0-zip/gcc/config/zip/netbsd.h
 
--- gcc-5.3.0-original/gcc/config/zip/netbsd.h  1969-12-31 19:00:00.000000000 -0500
 
+++ gcc-5.3.0-zip/gcc/config/zip/netbsd.h       2016-01-30 15:04:14.796899050 -0500
 
@@ -0,0 +1,82 @@
 
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+//
+//
+// Filename:   netbsd.h
+// Filename:   genzipops.c
+//
+//
+// Project:    Zip CPU backend for the GNU Compiler Collection
+// Project:    Zip CPU -- a small, lightweight, RISC CPU soft core
 
+//
 
+// Purpose:    This program generates the zip-ops.md machine description file.
 
+//
 
+//     While I understand that this is not GCC's preferred method of generating
 
+//     machine description files, there were just so many instructions to
 
+//     generate, and so many forms of them, and the GCC infrastructure didn't
 
+//     support the conditional execution model of the ZipCPU that ... I built
 
+//     it this way.
 
+//
 
+//     As of this writing, building zip-ops.md is not an automatic part of
 
+//     making GCC.  To build genzipops, just type:
 
+//
 
+//     g++ genzipops.c -o genzipops
 
+//
 
+//     And to run it, type:
 
+//
 
+//     genzipops > zip-ops.md
 
+//
 
+//     genzipops takes no arguments, and does nothing but write the machine
 
+//     descriptions to the standard output.
+//
+//
+// Purpose:
 
+//
+//
+// Creator:    Dan Gisselquist, Ph.D.
+// Creator:    Dan Gisselquist, Ph.D.
+//             Gisselquist Technology, LLC
+//             Gisselquist Technology, LLC
+//
+//
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+//
+//
+// Copyright (C) 2016, Gisselquist Technology, LLC
+// Copyright (C) 2017, Gisselquist Technology, LLC
+//
+//
+// This program is free software (firmware): you can redistribute it and/or
+// This program is free software (firmware): you can redistribute it and/or
+// modify it under the terms of  the GNU General Public License as published
+// modify it under the terms of  the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or (at
+// by the Free Software Foundation, either version 3 of the License, or (at
+// your option) any later version.
+// your option) any later version.
Line 585... Line 347...
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+// for more details.
+//
+//
+// You should have received a copy of the GNU General Public License along
+// You should have received a copy of the GNU General Public License along
+// with this program.  (It's in the $(ROOT)/doc directory, run make with no
+// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
+// target there if the PDF file isn't present.)  If not, see
+// target there if the PDF file isn't present.)  If not, see
+// <http://www.gnu.org/licenses/> for a copy.
+// <http://www.gnu.org/licenses/> for a copy.
+//
+//
+// License:    GPL, v3, as defined and found on www.gnu.org,
+// License:    GPL, v3, as defined and found on www.gnu.org,
+//             http://www.gnu.org/licenses/gpl.html
+//             http://www.gnu.org/licenses/gpl.html
+//
+//
+//
+//
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+#ifndef        ZIP_NETBSD_H
+//
+#define        ZIP_NETBSD_H
+//
+
+#include <unistd.h>
+/* Define default target values. */
+#include <stdlib.h>
+
+#include <stdio.h>
+#undef MACHINE_TYPE
+#include <string.h>
+#define        MACHINE_TYPE    "NetBSD/Zip ELF"
 
+
 
+#undef TARGET_OS_CPP_BUILTINS
 
+#define        TARGET_OS_CPP_BUILTINS()        \
 
+       do { NETBSD_OS_CPP_BUILTINS_ELF();              \
 
+       builtin_define("__ZIPCPU__");                   \
 
+       builtin_assert("cpu=zip");                      \
 
+       builtin_assert("machine=zip");                  \
 
+       } while(0);
 
+
 
+#undef CPP_SPEC
 
+#define        CPP_SPEC        NETBSD_CPP_SPEC
 
+
 
+#undef STARTFILE_SPEC
 
+#define        STARTFILE_SPEC  NETBSD_STARTFILE_SPEC
 
+
 
+#undef ENDFILE_SPEC
 
+#define        ENDFILE_SPEC    NETBSD_ENDFILE_SPEC
 
+
 
+#undef LIB_SPEC
 
+#define        LIB_SPEC        NETBSD_LIB_SPEC
 
+
+
+#undef TARGET_VERSION
+void   legal(FILE *fp) {
+#define        TARGET_VERSION  fprintf(stderr, " (%s)", MACHINE_TYPE);
+       fprintf(fp, ""
+
+";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n"
+/* Make gcc agree with <machine/ansi.h> */
+";;\n"
+
+";; Filename:  zip-ops.md\n"
+#undef WCHAR_TYPE
+";;\n"
+#define        WCHAR_TYPE      "int"
+";; Project:   Zip CPU -- a small, lightweight, RISC CPU soft core\n"
+
+";;\n"
+#undef WCHAR_TYPE_SIZE
+";; Purpose:   This is a computer generated machine description of the\n"
+#define        WCHAR_TYPE_SIZE 32
+";;            ZipCPU\'s operations.  It is computer generated simply for\n"
+
+";;    two reasons.  First, I can\'t seem to find a way to generate this\n"
+#undef WINT_TYPE
+";;    information within GCC\'s current constructs.  Specifically, the\n"
+#define        WINT_TYPE       "int"
+";;    CPU\'s instructions normally set the condition codes, unless they\n"
+
+";;    are conditional instructions when they don\'t.  Second, the ZipCPU is\n"
+/* Clean up after the generic Zip/ELF configuration. */
+";;    actually quite regular.  Almost all of the instructions have the same\n"
+#undef MD_EXEC_PREFIX
+";;    form.  This form turns into many, many RTL instructions.  Because the\n"
+#undef MD_STARTFILE_PREFIX
+";;    CPU doesn\'t match any of the others within GCC, that means either\n"
+
+";;    I have a *lot* of cut, copy, paste, and edit to do to create the file\n"
+#endif /* ZIP_NETBSD_H */
+";;    and upon any and every edit, or I need to build a program to generate\n"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/notes.txt gcc-5.3.0-zip/gcc/config/zip/notes.txt
+";;    the remaining .md constructs.  Hence, I chose the latter to minimize\n"
--- gcc-5.3.0-original/gcc/config/zip/notes.txt 1969-12-31 19:00:00.000000000 -0500
+";;    the amount of work I needed to do.\n"
+++ gcc-5.3.0-zip/gcc/config/zip/notes.txt      2016-08-17 23:00:25.714139174 -0400
+";;\n"
@@ -0,0 +1,6 @@
+";;\n"
+signum:
+";; Creator:   Dan Gisselquist, Ph.D.\n"
+       CMP       0,%1
+";;            Gisselquist Technology, LLC\n"
+       LDILO.GT  1,%1
+";;\n"
+       LDILO.LT -1,%1
+";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n"
+
+";;\n"
+
+";; Copyright (C) 2017, Gisselquist Technology, LLC\n"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/t-zip gcc-5.3.0-zip/gcc/config/zip/t-zip
+";;\n"
--- gcc-5.3.0-original/gcc/config/zip/t-zip     1969-12-31 19:00:00.000000000 -0500
+";; This program is free software (firmware): you can redistribute it and/or\n"
+++ gcc-5.3.0-zip/gcc/config/zip/t-zip  2016-02-04 19:00:59.939652587 -0500
+";; modify it under the terms of  the GNU General Public License as published\n"
@@ -0,0 +1,47 @@
+";; by the Free Software Foundation, either version 3 of the License, or (at\n"
+################################################################################
+";; your option) any later version.\n"
+##
+";;\n"
+## Filename:   t-zip
+";; This program is distributed in the hope that it will be useful, but WITHOUT\n"
+##
+";; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or\n"
+## Project:    Zip CPU backend for the GNU Compiler Collection
+";; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License\n"
+##
+";; for more details.\n"
+## Purpose:
+";;\n"
+##
+";; License:   GPL, v3, as defined and found on www.gnu.org,\n"
+## Creator:    Dan Gisselquist, Ph.D.
+";;            http://www.gnu.org/licenses/gpl.html\n"
+##             Gisselquist Technology, LLC
+";;\n"
+##
+";;\n"
+################################################################################
+";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n"
+##
+";;\n"
+## Copyright (C) 2016, Gisselquist Technology, LLC
+";;\n");
+##
+}
+## This program is free software (firmware): you can redistribute it and/or
+
+## modify it under the terms of  the GNU General Public License as published
+void   gen_heading(FILE *fp, const char *heading) {
+## by the Free Software Foundation, either version 3 of the License, or (at
+       fprintf(fp, ";\n;\n; %s\n;\n;\n", heading);
+## your option) any later version.
+}
+##
+
+## This program is distributed in the hope that it will be useful, but WITHOUT
+void   genzip_condop(FILE *fp, const char *md_opname,
+## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
+               const char *rtxstr, const char *insn_cond,
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+               const char *zip_op,
+## for more details.
+               const char *rtx_cond, const char *zip_cond) {
+##
+
+## You should have received a copy of the GNU General Public License along
+       fprintf(fp, "(define_insn \"%s_%s\"\n"
+## with this program.  (It's in the $(ROOT)/doc directory, run make with no
+               "\t[(cond_exec (%s (reg:CC CC_REG) (const_int 0))\n"
+## target there if the PDF file isn't present.)  If not, see
+               "\t\t\t%s)]\n"
+## <http://www.gnu.org/licenses/> for a copy.
+               "\t\"%s\"\t; Condition\n"
+##
+               "\t\"%s.%s\\t%%1,%%0\t; genzip, conditional operator\"\t; Template\n"
+## License:    GPL, v3, as defined and found on www.gnu.org,
+               "\t[(set_attr \"predicable\" \"no\") "
+##             http://www.gnu.org/licenses/gpl.html
+               "(set_attr \"ccresult\" \"unchanged\")])\n;\n;\n",
+##
+               md_opname, rtx_cond, rtx_cond, rtxstr, insn_cond, zip_op, zip_cond);
+##
+
+################################################################################
+}
+
+
+FPBIT = fp-bit.c
+void   genzipop_long(FILE *fp, const char *md_opname, const char *uncond_rtx, const char *insn_cond, const char *split_rtx, const char *dup_rtx, const char *zip_op) {
+DPBIT = dp-bit.c
+       char    heading[128];
+
+       sprintf(heading, "%s (genzipop_long)", zip_op);
+# dp-bit.c: $(srcdir)/config/fp-bit.c
+       fprintf(fp, ";\n;\n;\n; %s (genzipop_long)\n;\n;\n;\n", zip_op);
+       # cat $(srcdir)/config/fp-bit.c > dp-bit.c
+
+#
+       fprintf(fp, "(define_insn \"%s\"\n"
+# fp-bit.c: $(srcdir)/config/fp-bit.c
+"\t[%s\n"
+       # echo '#define FLOAT" > fp-bit.c
+"\t(clobber (reg:CC CC_REG))]\n"
+       # cat $(srcdir)/config/fp-bit.c >> fp-bit.c
+"\t\"%s\"\n"
+
+"\t\"%s\\t%%2,%%0\t; %s\"\n"
+
+"\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"set\")])\n;\n;\n",
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.c gcc-5.3.0-zip/gcc/config/zip/zip.c
+               md_opname, uncond_rtx, insn_cond, zip_op, md_opname);
--- gcc-5.3.0-original/gcc/config/zip/zip.c     1969-12-31 19:00:00.000000000 -0500
+
+++ gcc-5.3.0-zip/gcc/config/zip/zip.c  2016-11-19 08:28:56.703678695 -0500
+
@@ -0,0 +1,2293 @@
+       fprintf(fp, "(define_insn \"%s_raw\"\n"
 
+"\t[%s\n"
 
+"\t(set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]\n"
 
+"\t\"%s\"\n"
 
+"\t\"%s\\t%%1,%%0\t; %s_raw\"\n"
 
+"\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"set\")])\n;\n;\n",
 
+       md_opname, dup_rtx, insn_cond, zip_op, md_opname);
 
+
 
+       genzip_condop(fp, md_opname, dup_rtx, insn_cond, zip_op, "eq", "Z");
 
+       genzip_condop(fp, md_opname, dup_rtx, insn_cond, zip_op, "ne", "NZ");
 
+       genzip_condop(fp, md_opname, dup_rtx, insn_cond, zip_op, "lt", "LT");
 
+       genzip_condop(fp, md_opname, dup_rtx, insn_cond, zip_op, "ge", "GE");
 
+       genzip_condop(fp, md_opname, dup_rtx, insn_cond, zip_op, "ltu", "C");
 
+       genzip_condop(fp, md_opname, dup_rtx, insn_cond, zip_op, "geu", "NC");
 
+}
 
+
 
+void   genzipop(FILE *fp, const char *md_opname, const char *rtx_name, const char *insn_cond, const char *zip_op) {
 
+       char    rtxstr[512], splitstr[512], dupstr[512], altname[64];
 
+
 
+       sprintf(rtxstr,
 
+"(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
 
+"\t\t(%s (match_operand:SI 1 \"register_operand\" \"0\")\n"
 
+"\t\t\t(match_operand:SI 2 \"zip_opb_single_operand_p\" \"rO\")))", rtx_name);
 
+       sprintf(splitstr,
 
+           "(set (match_dup 0) (%s (match_dup 0) (match_dup 2)))", rtx_name);
 
+
 
+       sprintf(dupstr,
 
+"(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
 
+"\t\t(%s (match_dup 0)\n"
 
+"\t\t\t(match_operand:SI 1 \"zip_opb_single_operand_p\" \"rO\")))", rtx_name);
 
+
 
+       genzipop_long(fp, md_opname, rtxstr, insn_cond, splitstr, dupstr, zip_op);
 
+
 
+       sprintf(rtxstr,
 
+"(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
 
+"\t\t(%s (match_operand:SI 1 \"register_operand\" \"0\")\n"
 
+"\t\t\t(plus:SI (match_operand:SI 2 \"register_operand\" \"r\")\n"
 
+"\t\t\t\t(match_operand:SI 3 \"const_int_operand\" \"N\"))))", rtx_name);
 
+       sprintf(splitstr,
 
+           "(set (match_dup 0) (%s (match_dup 0)\n"
 
+"\t\t\t(plus:SI (match_dup 2) (match_dup 3))))", rtx_name);
 
+
 
+       sprintf(dupstr,
 
+"(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
 
+"\t\t(%s (match_dup 0)\n"
 
+"\t\t\t(plus:SI (match_operand:SI 1 \"register_operand\" \"r\")\n"
 
+"\t\t\t\t(match_operand:SI 2 \"const_int_operand\" \"N\"))))", rtx_name);
 
+
 
+       sprintf(altname, "%s_off", md_opname);
 
+
 
+       genzipop_long(fp, altname, rtxstr, insn_cond, splitstr, dupstr, zip_op);
 
+}
 
+
 
+void   gencmov(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
 
+       fprintf(fp, ";\n;\n"
 
+"(define_insn \"%s_%s\"\n"
 
+       "\t[(set (match_operand:SI 0 \"register_operand\" \"=r,r,r,Q\")\n"
 
+               "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
 
+               "\t\t\t(match_operand:SI 1 \"general_operand\" \"r,Q,i,r\")\n"
 
+               "\t\t\t(match_dup 0)))]\n"
 
+       "\t\"\"\n"
 
+       "\t\"@\n"
 
+       "\tMOV.%s\t%%1,%%0\t; cmov\n"
 
+       "\tLW.%s\t%%1,%%0\t; cmov\n"
 
+       "\tLDI.%s\t%%1,%%0\t; cmov\n"
 
+       "\tSW.%s\t%%1,%%0\t; cmov\"\n"
 
+       "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
 
+       md_opname, md_cond, md_cond, zip_cond, zip_cond, zip_cond, zip_cond);
 
+
 
+}
 
+
 
+void   gencadd(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
 
+       fprintf(fp, ";\n;\n"
 
+"(define_insn \"%s_%s\"\n"
 
+       "\t[(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
 
+               "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
 
+                       "\t\t\t(plus:SI (match_dup 0)\n"
 
+                               "\t\t\t\t(match_operand:SI 1 \"zip_opb_single_operand_p\" \"rO\"))\n"
 
+                       "\t\t\t(match_dup 0)))]\n"
 
+       "\t\"\"\n"
 
+       "\t\"ADD.%s\t%%1,%%0\t; cadd\"\n"
 
+       "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
 
+       md_opname, md_cond, md_cond, zip_cond);
 
+}
 
+
 
+void   gencnot(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
 
+       fprintf(fp, ";\n;\n"
 
+"(define_insn \"%s_%s\"\n"
 
+       "\t[(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
 
+               "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
 
+                       "\t\t\t(xor:SI (match_dup 0)\n"
 
+                               "\t\t\t\t(const_int -1))\n"
 
+                       "\t\t\t(match_dup 0)))]\n"
 
+       "\t\"\"\n"
 
+       "\t\"NOT.%s\t%%0\t; cnot\"\n"
 
+       "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
 
+       md_opname, md_cond, md_cond, zip_cond);
 
+}
 
+
 
+void   gencneg(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
 
+       fprintf(fp, ";\n;\n"
 
+"(define_insn \"%s_%s\"\n"
 
+       "\t[(set (match_operand:SI 0 \"register_operand\" \"+r\")\n"
 
+               "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
 
+                       "\t\t\t(neg:SI (match_dup 0))\n"
 
+                       "\t\t\t(match_dup 0)))]\n"
 
+       "\t\"\"\n"
 
+       "\t\"NEG.%s\t%%0\t; cneg\"\n"
 
+       "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
 
+       md_opname, md_cond, md_cond, zip_cond);
 
+}
 
+
 
+
 
+void   gencand(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
 
+       fprintf(fp, ";\n;\n"
 
+"(define_insn \"%s_%s\"\n"
 
+       "\t[(set (match_operand:SI 0 \"register_operand\" \"+r\")\n"
 
+               "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
 
+                       "\t\t\t(and:SI (match_dup 0) (match_operand:SI 1 \"zip_opb_single_operand_p\" \"rO\"))\n"
 
+                       "\t\t\t(match_dup 0)))]\n"
 
+       "\t\"\"\n"
 
+       "\t\"AND.%s\t%%1,%%0\t; cand\"\n"
 
+       "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
 
+       md_opname, md_cond, md_cond, zip_cond);
 
+}
 
+
 
+
 
+void   gencior(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
 
+       fprintf(fp, ";\n;\n"
 
+"(define_insn \"%s_%s\"\n"
 
+       "\t[(set (match_operand:SI 0 \"register_operand\" \"+r\")\n"
 
+               "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
 
+                       "\t\t\t(ior:SI (match_dup 0) (match_operand:SI 1 \"zip_opb_single_operand_p\" \"rO\"))\n"
 
+                       "\t\t\t(match_dup 0)))]\n"
 
+       "\t\"\"\n"
 
+       "\t\"OR.%s\t%%1,%%0\t; cior\"\n"
 
+       "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
 
+       md_opname, md_cond, md_cond, zip_cond);
 
+}
 
+
 
+void   gencxor(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
 
+       fprintf(fp, ";\n;\n"
 
+"(define_insn \"%s_%s\"\n"
 
+       "\t[(set (match_operand:SI 0 \"register_operand\" \"+r\")\n"
 
+               "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
 
+                       "\t\t\t(xor:SI (match_dup 0) (match_operand:SI 1 \"zip_opb_single_operand_p\" \"rO\"))\n"
 
+                       "\t\t\t(match_dup 0)))]\n"
 
+       "\t\"\"\n"
 
+       "\t\"XOR.%s\t%%1,%%0\t; cxor\"\n"
 
+       "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
 
+       md_opname, md_cond, md_cond, zip_cond);
 
+}
 
+
 
+void   usage(void) {
 
+       printf("USAGE: genzipops <new-zip-ops.md filename>\n");
 
+}
 
+
 
+const  char    *TMPPATH = ".zip-ops.md";
 
+const  char    *TAILPATH = "zip-ops.md";
 
+
 
+int main(int argc, char **argv) {
 
+       FILE    *fp = fopen(TMPPATH, "w");
 
+       const char      *newname = TAILPATH;
 
+
 
+       if ((argc>1)&&(argv[1][0] == '-')) {
 
+               usage();
 
+               exit(EXIT_FAILURE);
 
+       }
 
+
 
+       if (argc>1) {
 
+               if ((strlen(argv[1])>=strlen(TAILPATH))
 
+                       &&(strcmp(&argv[1][strlen(argv[1])-strlen(TAILPATH)],
 
+                               TAILPATH)==0)
 
+                       &&(access(argv[1], F_OK)==0))
 
+                               unlink(argv[1]);
 
+               newname = argv[1];
 
+       }
 
+
 
+       legal(fp);
 
+       genzipop(fp, "addsi3",  "plus:SI",    "",             "ADD");
 
+       genzipop(fp, "subsi3",  "minus:SI",   "",             "SUB");
 
+       genzipop(fp, "mulsi3",  "mult:SI",    "",             "MPY");
 
+       genzipop(fp, "divsi3",  "div:SI",     "(ZIP_DIVIDE)", "DIVS");
 
+       genzipop(fp, "udivsi3", "udiv:SI",    "(ZIP_DIVIDE)", "DIVU");
 
+       genzipop(fp, "andsi3",  "and:SI",     "",             "AND");
 
+       genzipop(fp, "iorsi3",  "ior:SI",     "",             "OR");
 
+       genzipop(fp, "xorsi3",  "xor:SI",     "",             "XOR");
 
+       genzipop(fp, "ashrsi3", "ashiftrt:SI","",             "ASR");
 
+       genzipop(fp, "ashlsi3", "ashift:SI",  "",             "LSL");
 
+       genzipop(fp, "lshrsi3", "lshiftrt:SI","",             "LSR");
 
+
 
+       genzipop_long(fp, "smulsi_highpart",
 
+               "(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
 
+               "\t\t(truncate:SI (ashiftrt:DI (mult:DI\n"
 
+               "\t\t\t(sign_extend:DI (match_operand:SI 1 \"register_operand\" \"0\"))\n"
 
+               "\t\t\t(sign_extend:DI (match_operand:SI 2 \"zip_opb_operand_p\" \"rO\")))\n"
 
+               "\t\t\t(const_int 32))))",
 
+               "(ZIP_HAS_DI)",
 
+               "(set (match_dup 0)\n"
 
+               "\t\t(truncate:SI (ashiftrt:DI (mult:DI\n"
 
+               "\t\t\t(sign_extend:DI (match_dup 1))\n"
 
+               "\t\t\t(sign_extend:DI (match_dup 2)))\n"
 
+               "\t\t\t(const_int 32))))",
 
+               //
 
+               "(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
 
+               "\t\t(truncate:SI (ashiftrt:DI (mult:DI\n"
 
+               "\t\t\t(sign_extend:DI (match_dup 0))\n"
 
+               "\t\t\t(sign_extend:DI (match_operand:SI 1 \"zip_opb_operand_p\" \"rO\")))\n"
 
+               "\t\t\t(const_int 32))))",
 
+               "MPYSHI");
 
+       genzipop_long(fp, "umulsi_highpart",
 
+               "(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
 
+               "\t\t(truncate:SI (ashiftrt:DI (mult:DI\n"
 
+               "\t\t\t(zero_extend:DI (match_operand:SI 1 \"register_operand\" \"0\"))\n"
 
+               "\t\t\t(zero_extend:DI (match_operand:SI 2 \"zip_opb_operand_p\" \"rO\")))\n"
 
+               "\t\t\t(const_int 32))))",
 
+               "(ZIP_HAS_DI)",
 
+               "(set (match_dup 0)\n"
 
+               "\t\t(truncate:SI (ashiftrt:DI (mult:DI\n"
 
+               "\t\t\t(zero_extend:DI (match_dup 1))\n"
 
+               "\t\t\t(zero_extend:DI (match_dup 2)))\n"
 
+               "\t\t\t(const_int 32))))",
 
+               //
 
+               "(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
 
+               "\t\t(truncate:SI (ashiftrt:DI (mult:DI\n"
 
+               "\t\t\t(zero_extend:DI (match_dup 0))\n"
 
+               "\t\t\t(zero_extend:DI (match_operand:SI 1 \"zip_opb_operand_p\" \"rO\")))\n"
 
+               "\t\t\t(const_int 32))))",
 
+               "MPYUHI");
 
+
 
+       gen_heading(fp, "Conditional move instructions");
 
+
 
+       gencmov(fp, "cmov", "eq", "Z");
 
+       gencmov(fp, "cmov", "ne", "NZ");
 
+       gencmov(fp, "cmov", "lt", "LT");
 
+       gencmov(fp, "cmov", "ge", "GE");
 
+       gencmov(fp, "cmov", "ltu", "C");
 
+       gencmov(fp, "cmov", "geu", "NC");
 
+
 
+       gen_heading(fp, "Conditional add instructions");
 
+
 
+       gencadd(fp, "cadd", "eq", "Z");
 
+       gencadd(fp, "cadd", "ne", "NZ");
 
+       gencadd(fp, "cadd", "lt", "LT");
 
+       gencadd(fp, "cadd", "ge", "GE");
 
+       gencadd(fp, "cadd", "ltu", "C");
 
+       gencadd(fp, "cadd", "geu", "NC");
 
+
 
+       gen_heading(fp, "Conditional negate instructions");
 
+
 
+       gencneg(fp, "cneg", "eq", "Z");
 
+       gencneg(fp, "cneg", "ne", "NZ");
 
+       gencneg(fp, "cneg", "lt", "LT");
 
+       gencneg(fp, "cneg", "ge", "GE");
 
+       gencneg(fp, "cneg", "ltu", "C");
 
+       gencneg(fp, "cneg", "geu", "NC");
 
+
 
+       gen_heading(fp, "Conditional not instructions");
 
+
 
+       gencnot(fp, "cnot", "eq", "Z");
 
+       gencnot(fp, "cnot", "ne", "NZ");
 
+       gencnot(fp, "cnot", "lt", "LT");
 
+       gencnot(fp, "cnot", "ge", "GE");
 
+       gencnot(fp, "cnot", "ltu", "C");
 
+       gencnot(fp, "cnot", "geu", "NC");
 
+
 
+       gen_heading(fp, "Conditional and instructions");
 
+
 
+       gencand(fp, "cand", "eq", "Z");
 
+       gencand(fp, "cand", "ne", "NZ");
 
+       gencand(fp, "cand", "lt", "LT");
 
+       gencand(fp, "cand", "ge", "GE");
 
+       gencand(fp, "cand", "ltu", "C");
 
+       gencand(fp, "cand", "geu", "NC");
 
+
 
+       gen_heading(fp, "Conditional ior instructions");
 
+
 
+       gencior(fp, "cior", "eq", "Z");
 
+       gencior(fp, "cior", "ne", "NZ");
 
+       gencior(fp, "cior", "lt", "LT");
 
+       gencior(fp, "cior", "ge", "GE");
 
+       gencior(fp, "cior", "ltu", "C");
 
+       gencior(fp, "cior", "geu", "NC");
 
+
 
+       gen_heading(fp, "Conditional xor instructions");
 
+
 
+       gencxor(fp, "cxor", "eq", "Z");
 
+       gencxor(fp, "cxor", "ne", "NZ");
 
+       gencxor(fp, "cxor", "lt", "LT");
 
+       gencxor(fp, "cxor", "ge", "GE");
 
+       gencxor(fp, "cxor", "ltu", "C");
 
+       gencxor(fp, "cxor", "geu", "NC");
 
+
 
+       fclose(fp);
 
+
 
+       if (rename(TMPPATH, newname) != 0) {
 
+               fprintf(stderr, "ERR: Could not create %s, leaving results in %s\n", newname, TMPPATH);
 
+               exit(EXIT_FAILURE);
 
+       } exit(EXIT_SUCCESS);
 
+}
 
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip.c gcc-6.2.0-zip/gcc/config/zip/zip.c
 
--- gcc-6.2.0/gcc/config/zip/zip.c      1969-12-31 19:00:00.000000000 -0500
 
+++ gcc-6.2.0-zip/gcc/config/zip/zip.c  2017-03-07 12:03:18.566583672 -0500
 
@@ -0,0 +1,2679 @@
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+//
+//
+// Filename:   zip.c
+// Filename:   zip.c
+//
+//
+// Project:    Zip CPU backend for the GNU Compiler Collection
+// Project:    Zip CPU backend for the GNU Compiler Collection
Line 719... Line 763...
+// Creator:    Dan Gisselquist, Ph.D.
+// Creator:    Dan Gisselquist, Ph.D.
+//             Gisselquist Technology, LLC
+//             Gisselquist Technology, LLC
+//
+//
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+//
+//
+// Copyright (C) 2016, Gisselquist Technology, LLC
+// Copyright (C) 2016-2017, Gisselquist Technology, LLC
+//
+//
+// This program is free software (firmware): you can redistribute it and/or
+// This program is free software (firmware): you can redistribute it and/or
+// modify it under the terms of  the GNU General Public License as published
+// modify it under the terms of  the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or (at
+// by the Free Software Foundation, either version 3 of the License, or (at
+// your option) any later version.
+// your option) any later version.
Line 755... Line 799...
+#include "lcm.h"
+#include "lcm.h"
+#include "cfgbuild.h"
+#include "cfgbuild.h"
+#include "cfgcleanup.h"
+#include "cfgcleanup.h"
+#include "predict.h"
+#include "predict.h"
+#include "basic-block.h"
+#include "basic-block.h"
 
+#include "bitmap.h"
+#include "df.h"
+#include "df.h"
+#include "hashtab.h"
+#include "hashtab.h"
+#include "hash-set.h"
+#include "hash-set.h"
+#include "machmode.h"
+#include "machmode.h"
+#include "symtab.h"
+#include "symtab.h"
Line 782... Line 827...
+#include "langhooks.h"
+#include "langhooks.h"
+#include "optabs.h"
+#include "optabs.h"
+#include "explow.h"
+#include "explow.h"
+#include "emit-rtl.h"
+#include "emit-rtl.h"
+#include "ifcvt.h"
+#include "ifcvt.h"
 
+#include "genrtl.h"
+
+
+// #include "tmp_p.h"
+// #include "tmp_p.h"
+#include "target.h"
+#include "target.h"
+#include "target-def.h"
+#include "target-def.h"
+// #include "tm-constrs.h"
+// #include "tm-constrs.h"
Line 794... Line 840...
+#include "diagnostic.h"
+#include "diagnostic.h"
+// #include "integrate.h"
+// #include "integrate.h"
+
+
+#include "zip-protos.h"
+#include "zip-protos.h"
+
+
+// static int  zip_arg_partial_bytes(CUMULATIVE_ARGS *, enum machine_mode, tree, bool);
 
+// static      bool    zip_pass_by_reference(CUMULATIVE_ARGS *, enum machine_mode, const_tree, bool);
 
+static bool    zip_return_in_memory(const_tree, const_tree);
+static bool    zip_return_in_memory(const_tree, const_tree);
+static bool    zip_frame_pointer_required(void);
+static bool    zip_frame_pointer_required(void);
+
+
+static void zip_function_arg_advance(cumulative_args_t ca, enum machine_mode mode,
+static void zip_function_arg_advance(cumulative_args_t ca, enum machine_mode mode,
+               const_tree type, bool named);
+               const_tree type, bool named);
Line 832... Line 876...
+static void    zip_override_options(void);
+static void    zip_override_options(void);
+static bool    zip_can_eliminate(int from ATTRIBUTE_UNUSED, int to);
+static bool    zip_can_eliminate(int from ATTRIBUTE_UNUSED, int to);
+static int     zip_memory_move_cost(machine_mode, reg_class_t, bool);
+static int     zip_memory_move_cost(machine_mode, reg_class_t, bool);
+static rtx     zip_legitimize_address(rtx x, rtx oldx, machine_mode mode);
+static rtx     zip_legitimize_address(rtx x, rtx oldx, machine_mode mode);
+static bool    zip_cannot_modify_jumps_p(void);
+static bool    zip_cannot_modify_jumps_p(void);
+#ifdef HAVE_cc0
 
+       void    zip_update_cc_notice(rtx exp, rtx_insn *insn);
 
+#error "We're not supposed to have CC0 anymore"
 
+#else
 
+static bool    zip_fixed_condition_code_regs(unsigned int *a, unsigned int *b);
+static bool    zip_fixed_condition_code_regs(unsigned int *a, unsigned int *b);
+#endif
 
+
+
+
+
+#define        ALL_DEBUG_OFF   false
+#define        ZIP_ALL_DEBUG_OFF       false
+#define        ALL_DEBUG_ON    false
+#define        ZIP_ALL_DEBUG_ON        false
 
+#define        ZIPDEBUGFLAG(A,B)       const bool A =                  \
 
+               ((ZIP_ALL_DEBUG_ON)||(B))&&(!ZIP_ALL_DEBUG_OFF)
+
+
+enum ZIP_BUILTIN_ID_CODE {
+enum ZIP_BUILTIN_ID_CODE {
+       ZIP_BUILTIN_RTU,
+       ZIP_BUILTIN_RTU,
+       ZIP_BUILTIN_HALT,
+       ZIP_BUILTIN_HALT,
+       ZIP_BUILTIN_IDLE,
+       ZIP_BUILTIN_IDLE,
Line 860... Line 901...
+};
+};
+
+
+static GTY (()) tree   zip_builtins[(int)ZIP_BUILTIN_MAX];
+static GTY (()) tree   zip_builtins[(int)ZIP_BUILTIN_MAX];
+static enum insn_code  zip_builtins_icode[(int)ZIP_BUILTIN_MAX];
+static enum insn_code  zip_builtins_icode[(int)ZIP_BUILTIN_MAX];
+
+
 
+#undef TARGET_ASM_ALIGNED_HI_OP
 
+#undef TARGET_ASM_ALIGNED_SI_OP
 
+#undef TARGET_ASM_ALIGNED_DI_OP
 
+#define        TARGET_ASM_ALIGNED_HI_OP        "\t.short\t"
 
+#define        TARGET_ASM_ALIGNED_SI_OP        "\t.int\t"
 
+#define        TARGET_ASM_ALIGNED_DI_OP        "\t.quad\t"
 
+
 
+#undef TARGET_ASM_UNALIGNED_HI_OP
 
+#undef TARGET_ASM_UNALIGNED_SI_OP
 
+#undef TARGET_ASM_UNALIGNED_DI_OP
 
+#define        TARGET_ASM_UNALIGNED_HI_OP      TARGET_ASM_ALIGNED_HI_OP
 
+#define        TARGET_ASM_UNALIGNED_SI_OP      TARGET_ASM_ALIGNED_SI_OP
 
+#define        TARGET_ASM_UNALIGNED_DI_OP      TARGET_ASM_ALIGNED_DI_OP
+
+
+#include "gt-zip.h"
+#include "gt-zip.h"
+
+
+/* The Global 'targetm' Variable. */
+/* The Global 'targetm' Variable. */
+struct gcc_target      targetm = TARGET_INITIALIZER;
+struct gcc_target      targetm = TARGET_INITIALIZER;
Line 920... Line 974...
+
+
+/* Worker function for TARGET_RETURN_IN_MEMORY. */
+/* Worker function for TARGET_RETURN_IN_MEMORY. */
+static bool
+static bool
+zip_return_in_memory(const_tree type, const_tree fntype ATTRIBUTE_UNUSED) {
+zip_return_in_memory(const_tree type, const_tree fntype ATTRIBUTE_UNUSED) {
+       const   HOST_WIDE_INT size = int_size_in_bytes(type);
+       const   HOST_WIDE_INT size = int_size_in_bytes(type);
+       return (size == -1)||(size > UNITS_PER_WORD);
+       return (size == -1)||(size > 2*UNITS_PER_WORD);
+}
+}
+
+
+/* Emit an error emssage when we're in an asm, and a fatal error for "normal"
+/* Emit an error emssage when we're in an asm, and a fatal error for "normal"
+ * insn.  Formatted output isn't easily implemented, since we use output operand
+ * insn.  Formatted output isn't easily implemented, since we use output operand
+ * lossage to output the actual message and handle the categorization of the
+ * lossage to output the actual message and handle the categorization of the
+ * error.  */
+ * error.  */
+
+
+static void
+static void
+zip_operand_lossage(const char *msgid, rtx op) {
+zip_operand_lossage(const char *msgid, rtx op) {
+       fprintf(stderr, "Operand lossage??\n");
 
+       debug_rtx(op);
+       debug_rtx(op);
+       zip_debug_rtx(op);
+       zip_debug_rtx(op);
+       output_operand_lossage("%s", msgid);
+       output_operand_lossage("%s", msgid);
+}
+}
+
+
+/* The PRINT_OPERAND_ADDRESS worker.   */
+/* The PRINT_OPERAND_ADDRESS worker.   */
+void
+void
+zip_print_operand_address(FILE *file, rtx x) {
+zip_print_operand_address(FILE *file, rtx x) {
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       ZIPDEBUGFLAG(dbg, false);
+
+
+       if (dbg) zip_debug_rtx(x);
+       if (dbg) zip_debug_rtx(x);
+       switch(GET_CODE(x)) {
+       switch(GET_CODE(x)) {
+               case REG:
+               case REG:
+                       gcc_assert(is_ZIP_REG(REGNO(x)));
+                       gcc_assert(is_ZIP_REG(REGNO(x)));
Line 1090... Line 1143...
+               if (CONSTANT_P(operand)) {
+               if (CONSTANT_P(operand)) {
+                       output_addr_const(file, operand);
+                       output_addr_const(file, operand);
+                       return;
+                       return;
+               }
+               }
+
+
 
+               zip_debug_rtx(x);
+               LOSE_AND_RETURN("unexpected operand", x);
+               LOSE_AND_RETURN("unexpected operand", x);
+       }
+       }
+}
+}
+
+
+static bool
+static bool
Line 1105... Line 1159...
+       // it.
+       // it.
+       //
+       //
+       // Use a GCC global to determine our answer
+       // Use a GCC global to determine our answer
+       if (cfun->calls_alloca)
+       if (cfun->calls_alloca)
+               return true;
+               return true;
 
+
 
+       // If the stack frame is too large to access saved registers with
 
+       // immediate offsets, then we *must* use a frame pointer
 
+       unsigned stack_size = 36;
 
+       stack_size += (ACCUMULATE_OUTGOING_ARGS ? crtl->outgoing_args_size : 0);
 
+
 
+       //
 
+       // if cfun->machine->size_for_adjusting_sp might ever be larger than
 
+       //       zip_max_anchor_offset, then we MUST have a frame pointer.
 
+       //
 
+       // cfun->machine->size_for_adjusting_sp =
 
+       //              get_frame_size
 
+       //              + saved_reg_size (will always be <= 36)
 
+       //              + outgoing_args_size;
 
+       //              + pretend_args_size;
 
+
 
+       if(crtl->args.pretend_args_size > 0)
 
+               stack_size += crtl->args.pretend_args_size;
 
+       stack_size += get_frame_size();
 
+       // Align our attempted stack size
 
+       stack_size = ((stack_size+3)&-4);
 
+
 
+       // Now here's our test
 
+       if (stack_size >= zip_max_anchor_offset)
 
+               return true;
+       return (frame_pointer_needed);
+       return (frame_pointer_needed);
+/*
+/*
+*/
+*/
+}
+}
+
+
Line 1154... Line 1233...
+ */
+ */
+static void
+static void
+zip_compute_frame(void) {
+zip_compute_frame(void) {
+       int     regno;
+       int     regno;
+       int     args_size;
+       int     args_size;
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       ZIPDEBUGFLAG(dbg, false);
+
+
+       if (dbg) fprintf(stderr, "ZIP-COMPUTE-FRAME: %s\n", current_function_name());
+       if (dbg) fprintf(stderr, "ZIP-COMPUTE-FRAME: %s\n", current_function_name());
+       // gcc_assert(crtl);
+       // gcc_assert(crtl);
+       gcc_assert(cfun);
+       gcc_assert(cfun);
+       gcc_assert(cfun->machine);
+       gcc_assert(cfun->machine);
Line 1172... Line 1251...
+               cfun->machine->pretend_size = crtl->args.pretend_args_size;
+               cfun->machine->pretend_size = crtl->args.pretend_args_size;
+       }
+       }
+
+
+       cfun->machine->local_vars_size = get_frame_size();
+       cfun->machine->local_vars_size = get_frame_size();
+
+
 
+       // Force frame alignment of the local variable section
 
+       cfun->machine->local_vars_size += 3;
 
+       cfun->machine->local_vars_size &= -4;
 
+
+       // Save callee-saved registers.
+       // Save callee-saved registers.
+       cfun->machine->saved_reg_size = 0;
+       cfun->machine->saved_reg_size = 0;
+       for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) {
+       for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) {
+               if (zip_save_reg(regno))
+               if (zip_save_reg(regno))
+                       cfun->machine->saved_reg_size ++;
+                       cfun->machine->saved_reg_size += 4;
+       }
+       }
+
+
+       cfun->machine->fp_needed = (zip_frame_pointer_required());
+       cfun->machine->fp_needed = (zip_frame_pointer_required());
+
+
+       if ((cfun->machine->fp_needed)&&
+       if ((cfun->machine->fp_needed)&&
+                       (!df_regs_ever_live_p(zip_FP))) {
+                       (!df_regs_ever_live_p(zip_FP))) {
+               cfun->machine->saved_reg_size ++;
+               cfun->machine->saved_reg_size += 4;
+       }
+       }
+
+
+       cfun->machine->sp_fp_offset = crtl->outgoing_args_size
+       cfun->machine->sp_fp_offset = crtl->outgoing_args_size
+                               + cfun->machine->local_vars_size;
+                               + cfun->machine->local_vars_size;
+       cfun->machine->size_for_adjusting_sp = cfun->machine->local_vars_size
+       cfun->machine->size_for_adjusting_sp = cfun->machine->local_vars_size
Line 1214... Line 1297...
+                       cfun->machine->size_for_adjusting_sp);
+                       cfun->machine->size_for_adjusting_sp);
+       }
+       }
+}
+}
+
+
+void
+void
+zip_expand_prologue(void) {
+zip_save_registers(rtx basereg_rtx, int sp_offset_to_first_register) {
+       rtx     insn;
+       rtx     insn;
 
+       ZIPDEBUGFLAG(dbg, false);
+
+
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       // Compute Frame has already been calculated before coming into here
+       zip_compute_frame();
+       //
+
+       // zip_compute_frame();
+       if (dbg)  fprintf(stderr, "PROLOGUE: Computing Prologue instructions\n");
+       if (dbg)  fprintf(stderr, "PROLOGUE::SAVE-REGISTER\n");
+       if (dbg)  fprintf(stderr, "PROLOGUE: SP-FP offset is %d\n",
 
+                       cfun->machine->sp_fp_offset);
 
+       if (cfun->machine->size_for_adjusting_sp != 0) {
 
+               insn = emit_insn(gen_subsi3_reg_clobber(stack_pointer_rtx,
 
+                               stack_pointer_rtx,
 
+                       gen_int_mode(cfun->machine->size_for_adjusting_sp,
 
+                               SImode)));
 
+                       // cfun->machine->sp_fp_offset
 
+
 
+               RTX_FRAME_RELATED_P(insn) = 1;
 
+       }
 
+
+
+       {
 
+               int offset = 0, regno;
+               int offset = 0, regno;
+               for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) {
+               for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) {
+                       if (zip_save_reg(regno)) {
+                       if (zip_save_reg(regno)) {
+                               if (dbg) fprintf(stderr,
+                               if (dbg) fprintf(stderr,
+                                       "PROLOGUE: Saving R%d in %d+%d(SP)\n",
+                               "PROLOGUE::SAVE-REGISTER Saving R%d in %d+%d(SP)\n",
+                                       regno, cfun->machine->sp_fp_offset,
+                               regno, sp_offset_to_first_register, offset);
+                                       offset);
 
+                               insn=emit_insn(gen_movsi_sto_off(
+                               insn=emit_insn(gen_movsi_sto_off(
+                                       stack_pointer_rtx,
+                               basereg_rtx,
+                                       GEN_INT(cfun->machine->sp_fp_offset
+                               GEN_INT(sp_offset_to_first_register +offset),
+                                               +offset++),
 
+                                       gen_rtx_REG(SImode, regno)));
+                                       gen_rtx_REG(SImode, regno)));
+                               RTX_FRAME_RELATED_P(insn) = 1;
+                               RTX_FRAME_RELATED_P(insn) = 1;
 
+                       offset += 4;
+                       }
+                       }
+               }
+       } if (dbg)  fprintf(stderr, "%d registers saved%s\n", offset,
+               if (dbg)  fprintf(stderr, "%d registers saved%s\n", offset,
 
+                       (crtl->saves_all_registers)?", should be all of them":", less than all");
+                       (crtl->saves_all_registers)?", should be all of them":", less than all");
 
+
+       }
+       }
+
+
 
+/*
 
+ * zip_expand_small_prologue()
 
+ *
 
+ * To be used when the sp_fp_offset is less then zip_max_opb_offset.
 
+ *
 
+ *
 
+ * Approach:
 
+ *     SUB size_for_adjusting_sp,SP
 
+ *     SW REG,0(SP)
 
+ *     SW REG,4(SP)
 
+ *     SW REG,8(SP)
 
+ *     ....
 
+ *     SW REG,#(SP)
 
+ *
 
+ * and if we need a frame register, we'll either do ...
 
+ *     MOV sp_fp_offset+SP,FP
 
+ * or if the offset is too large, we'll do ...
 
+ *     MOV SP,FP
 
+ *     ADD sp_fp_offset,FP
 
+ *
 
+ */
 
+void
 
+zip_expand_small_prologue(void) {
 
+       ZIPDEBUGFLAG(dbg, false);
 
+       rtx     insn;
 
+
 
+       zip_compute_frame();
 
+
 
+       if (dbg)  fprintf(stderr, "PROLOGUE:::EXPAND-SMALL-PROLOGUE(SP-FP offset is %d)\n",
 
+               cfun->machine->sp_fp_offset);
 
+
 
+       insn = emit_insn(gen_subsi3(stack_pointer_rtx, stack_pointer_rtx,
 
+                       gen_int_mode(cfun->machine->size_for_adjusting_sp,
 
+                               SImode)));
 
+       RTX_FRAME_RELATED_P(insn) = 1;
 
+
 
+       zip_save_registers(stack_pointer_rtx, cfun->machine->sp_fp_offset);
 
+
+       if (cfun->machine->fp_needed) {
+       if (cfun->machine->fp_needed) {
 
+               if (dbg)  fprintf(stderr, "PROLOGUE:::EXPAND-SMALL-PROLOGUE(FP-NEEDED)\n");
+               if (dbg) zip_debug_rtx(stack_pointer_rtx);
+               if (dbg) zip_debug_rtx(stack_pointer_rtx);
+               if (dbg) zip_debug_rtx(frame_pointer_rtx);
+               if (dbg) zip_debug_rtx(frame_pointer_rtx);
 
+               if (cfun->machine->sp_fp_offset < zip_max_mov_offset) {
 
+                       if (dbg)  fprintf(stderr,
 
+                               "PROLOGUE:::EXPAND-SMALL-PROLOGUE() "
 
+                               "gen_movsi_reg_off(FP, SP, %d), %d < %ld\n",
 
+                               cfun->machine->sp_fp_offset,
 
+                               cfun->machine->sp_fp_offset,
 
+                               zip_max_mov_offset);
+               insn = emit_insn(gen_movsi_reg_off(frame_pointer_rtx,
+               insn = emit_insn(gen_movsi_reg_off(frame_pointer_rtx,
+                               stack_pointer_rtx,
+                               stack_pointer_rtx,
+                               GEN_INT(cfun->machine->sp_fp_offset)));
+                               GEN_INT(cfun->machine->sp_fp_offset)));
+               RTX_FRAME_RELATED_P(insn) = 1;
+               RTX_FRAME_RELATED_P(insn) = 1;
+               if (dbg)  fprintf(stderr, "sp_fp_offset is %d\n", cfun->machine->sp_fp_offset);
+               } else {
 
+                       rtx     fp_rtx;
 
+
 
+                       fp_rtx = gen_rtx_REG(SImode, zip_FP);
 
+
 
+                       insn = emit_insn(gen_movsi(fp_rtx, stack_pointer_rtx));
 
+                       RTX_FRAME_RELATED_P(insn) = 1;
 
+
 
+                       insn = emit_insn(gen_addsi3(fp_rtx, fp_rtx,
 
+                               GEN_INT(cfun->machine->sp_fp_offset)));
 
+                       RTX_FRAME_RELATED_P(insn) = 1;
 
+               }
 
+       }
 
+}
 
+
 
+/*
 
+ * zip_expand_large_prologue()
 
+ *
 
+ * The prologue function will be called when the size_for_adjusting_sp is too
 
+ * large to fit into a single OPB-immediate as part of a subtract.
 
+ *
 
+ * Approach:
 
+ *     SUB (size_for_adjusting_sp-sp_fp_offset),SP
 
+ *     SW R0,(SP)
 
+ *     SW R5,4(SP)
 
+ *     SW R6,8SP)
 
+ *     SW R7,(SP)
 
+ *     ...
 
+ *     SW FP,(SP)
 
+ *
 
+ *     LDI sp_fp_offset,FP
 
+ *     SUB FP,SP
 
+ *     ADD SP,FP
 
+ */
 
+void
 
+zip_expand_large_prologue(void) {
 
+       ZIPDEBUGFLAG(dbg, false);
 
+       rtx     insn, fp_rtx;
 
+
 
+       gcc_assert(cfun->machine->fp_needed);
 
+
 
+       if (dbg)        fprintf(stderr, "PROLOGUE::expand-large(%d-%d)\n",
 
+                               cfun->machine->size_for_adjusting_sp,
 
+                               cfun->machine->sp_fp_offset);
 
+       insn = emit_insn(gen_subsi3(stack_pointer_rtx, stack_pointer_rtx,
 
+               gen_int_mode(cfun->machine->size_for_adjusting_sp
 
+                               -cfun->machine->sp_fp_offset, SImode)));
 
+       RTX_FRAME_RELATED_P(insn) = 1;
 
+
 
+       zip_save_registers(stack_pointer_rtx, 0);
 
+
 
+       fp_rtx = gen_rtx_REG(SImode, zip_FP);
 
+
 
+       insn = emit_insn(gen_movsi(fp_rtx,
 
+               gen_int_mode(cfun->machine->sp_fp_offset, SImode)));
 
+       RTX_FRAME_RELATED_P(insn) = 1;
 
+
 
+       insn = emit_insn(gen_subsi3(stack_pointer_rtx, stack_pointer_rtx,
 
+                       fp_rtx));
 
+       RTX_FRAME_RELATED_P(insn) = 1;
 
+
 
+       insn = emit_insn(gen_addsi3(fp_rtx, fp_rtx, stack_pointer_rtx));
 
+       RTX_FRAME_RELATED_P(insn) = 1;
 
+}
 
+
 
+void
 
+zip_expand_prologue(void) {
 
+       ZIPDEBUGFLAG(dbg, false);
 
+
 
+       zip_compute_frame();
 
+
 
+       if (dbg)  fprintf(stderr, "PROLOGUE: Computing Prologue instructions\n");
 
+       if (dbg)  fprintf(stderr, "PROLOGUE: SP-FP offset is %d\n",
 
+                       cfun->machine->sp_fp_offset);
 
+       if (cfun->machine->size_for_adjusting_sp != 0) {
 
+               if (cfun->machine->size_for_adjusting_sp <= zip_max_anchor_offset) {
 
+                       if (dbg)  fprintf(stderr, "PROLOGUE: "
 
+                                       "%d <= %ld, so going small\n",
 
+                                       cfun->machine->size_for_adjusting_sp,
 
+                                       zip_max_opb_imm);
 
+                       zip_expand_small_prologue();
 
+               } else {
 
+                       zip_expand_large_prologue();
 
+               }
+       }
+       }
+}
+}
+
+
+int
+int
+zip_use_return_insn(void)
+zip_use_return_insn(void)
Line 1282... Line 1482...
+       zip_compute_frame();
+       zip_compute_frame();
+       return (cfun->machine->size_for_adjusting_sp == 0)?1:0;
+       return (cfun->machine->size_for_adjusting_sp == 0)?1:0;
+}
+}
+
+
+/* As per the notes in M68k.c, quote the function epilogue should not depend
+/* As per the notes in M68k.c, quote the function epilogue should not depend
+ * upon the current stack pointer.  It should use the frame poitner only,
+ * upon the current stack pointer.  It should use the frame pointer only,
+ * if there is a frame pointer.  This is mandatory because of alloca; we also
+ * if there is a frame pointer.  This is mandatory because of alloca; we also
+ * take advantage of it to omit stack adjustments before returning ...
+ * take advantage of it to omit stack adjustments before returning ...
+ *
+ *
+ * Let's see if we can use their approach here.
+ * Let's see if we can use their approach here.
+ *
+ *
+ * We can't.  Consider our choices:
+ * We can't.  Consider our choices:
+ *     LOD (FP),R0
+ *     LW (FP),R0
+ *     LOD 1(FP),R4
+ *     LW 4(FP),R4
+ *     LOD 2(FP),R5
+ *     LW 8(FP),R5
+ *     LOD 3(FP),R6
+ *     LW 12(FP),R6
+ *     LOD 4(FP),FP
+ *     LW 16(FP),FP
+ *     ... Then what is the stack pointer?
+ *     ... Then what is the stack pointer?
+ * or
+ * or
+ *     LOD (FP),R0
+ *     LW (FP),R0
+ *     LOD 1(FP),R4
+ *     LW 4(FP),R4
+ *     LOD 2(FP),R5
+ *     LW 8(FP),R5
+ *     LOD 3(FP),R6
+ *     LW 12(FP),R6
+ *     MOV FP,SP
+ *     MOV FP,SP
+ *     LOD 4(SP),FP
+ *     LW 16(SP),FP
+ *     ... Which suffers unnecessary pipeline stalls, and certainly doesn't
+ *     ... Which suffers unnecessary pipeline stalls, and certainly doesn't
+ *     exploit our pipeline memory function
+ *     exploit our pipeline memory function
+ * or
+ * or
+ *     MOV FP,SP
+ *     MOV FP,SP
+ *     LOD (SP),R0
+ *     LW (SP),R0
+ *     LOD 1(SP),R4
+ *     LW 4(SP),R4
+ *     LOD 2(SP),R5
+ *     LW 8(SP),R5
+ *     LOD 3(SP),R6
+ *     LW 12(SP),R6
+ *     LOD 4(SP),FP
+ *     LW 16(SP),FP
+ * Which will be our choice.  Note that we do use the stack pointer, eventually.
+ * Which will be our choice.  Note that we do use the stack pointer, eventually.
+ *
+ *
+ */
+ */
+void
+void
+zip_expand_epilogue(void) {
+zip_expand_epilogue(void) {
+       int     regno, offset;
+       int     regno, offset;
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       ZIPDEBUGFLAG(dbg, false);
+       rtx     insn;
+       rtx     insn;
+
+
+       zip_compute_frame();
+       zip_compute_frame();
+
+
+       if (dbg) fprintf(stderr, "EPILOG::\n");
+       if (dbg) fprintf(stderr, "EPILOG::\n");
Line 1330... Line 1530...
+               // enough so that you must have a frame pointer, then you can't
+               // enough so that you must have a frame pointer, then you can't
+               // trust its offset enough to restore from it.  Hence, we start
+               // trust its offset enough to restore from it.  Hence, we start
+               // by moving the frame pointer to the stack pointer to recover
+               // by moving the frame pointer to the stack pointer to recover
+               // the stack pointer back to a usable value.
+               // the stack pointer back to a usable value.
+               if (dbg) fprintf(stderr, "EPILOG::Moving frame pointer to stack register\n");
+               if (dbg) fprintf(stderr, "EPILOG::Moving frame pointer to stack register\n");
+               insn = emit_insn(gen_movsi_reg(stack_pointer_rtx, frame_pointer_rtx));
+               insn = emit_insn(gen_movsi_raw(stack_pointer_rtx, frame_pointer_rtx));
+               RTX_FRAME_RELATED_P(insn) = 1;
+               RTX_FRAME_RELATED_P(insn) = 1;
+       }
+       }
+
+
+       if (cfun->machine->saved_reg_size != 0) {
+       if (cfun->machine->saved_reg_size != 0) {
+               if (cfun->machine->fp_needed)
+               if (cfun->machine->fp_needed)
Line 1342... Line 1542...
+               else
+               else
+                       offset = cfun->machine->sp_fp_offset;
+                       offset = cfun->machine->sp_fp_offset;
+               if (dbg) fprintf(stderr, "EPILOG::Saved_REG_Size = %d\n", cfun->machine->saved_reg_size);
+               if (dbg) fprintf(stderr, "EPILOG::Saved_REG_Size = %d\n", cfun->machine->saved_reg_size);
+               for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) {
+               for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) {
+                       if (zip_save_reg(regno)) {
+                       if (zip_save_reg(regno)) {
+                               if (dbg) fprintf(stderr, "EPILOG::RESTORING R%d\n", regno);
+                               if (dbg) fprintf(stderr, "EPILOG::RESTORING R%d from SP+%d\n", regno, offset);
+                               rtx reg = gen_rtx_REG(SImode, regno);
+                               rtx reg = gen_rtx_REG(SImode, regno);
+                               insn = emit_insn(gen_movsi_lod_off(
+                               insn = emit_insn(gen_movsi_lod_off(
+                                               reg,
+                                               reg,
+                                               stack_pointer_rtx,
+                                               stack_pointer_rtx,
+                                               GEN_INT(offset++)));
+                                               GEN_INT(offset)));
+                               add_reg_note(insn, REG_CFA_RESTORE, reg);
+                               add_reg_note(insn, REG_CFA_RESTORE, reg);
+                               RTX_FRAME_RELATED_P(insn) = 1;
+                               RTX_FRAME_RELATED_P(insn) = 1;
 
+                               offset += 4;
+                       }
+                       }
+               }
+               }
+       }
+       }
+
+
+       if (cfun->machine->fp_needed) {
+       if (cfun->machine->fp_needed) {
+               // Restore the stack pointer back to the original, the
+               // Restore the stack pointer back to the original, the
+               // difference being the difference from the frame pointer
+               // difference being the difference from the frame pointer
+               // to the original stack
+               // to the original stack
+               insn = emit_insn(gen_addsi3_reg_clobber(stack_pointer_rtx,
+               insn = emit_insn(gen_addsi3(stack_pointer_rtx,
+                       stack_pointer_rtx,
+                       stack_pointer_rtx,
+                       GEN_INT(cfun->machine->size_for_adjusting_sp
+                       GEN_INT(cfun->machine->size_for_adjusting_sp
+                               -cfun->machine->sp_fp_offset)));
+                               -cfun->machine->sp_fp_offset)));
+               RTX_FRAME_RELATED_P(insn) = 1;
+               RTX_FRAME_RELATED_P(insn) = 1;
+       } else {
+       } else {
+               // else now the difference is between the stack pointer and
+               // else now the difference is between the stack pointer and
+               // the original stack pointer.
+               // the original stack pointer.
+               if (dbg) fprintf(stderr, "EPILOG::ADDSI3(StackPtr, %d)\n",
+               if (dbg) fprintf(stderr, "EPILOG::ADDSI3(StackPtr, %d)\n",
+                               cfun->machine->size_for_adjusting_sp);
+                               cfun->machine->size_for_adjusting_sp);
+               insn = emit_insn(gen_addsi3_reg_clobber(stack_pointer_rtx,
+               insn = emit_insn(gen_addsi3(stack_pointer_rtx, stack_pointer_rtx,
+                       stack_pointer_rtx,
 
+                       GEN_INT(cfun->machine->size_for_adjusting_sp)));
+                       GEN_INT(cfun->machine->size_for_adjusting_sp)));
+               RTX_FRAME_RELATED_P(insn) = 1;
+               RTX_FRAME_RELATED_P(insn) = 1;
+       }
+       }
+       if (dbg) fprintf(stderr, "EPILOG::EMITTING-RETURN\n");
+       if (dbg) fprintf(stderr, "EPILOG::EMITTING-RETURN\n");
+
+
Line 1383... Line 1583...
+}
+}
+
+
+void
+void
+zip_sibcall_epilogue(void) {
+zip_sibcall_epilogue(void) {
+       int     regno, offset;
+       int     regno, offset;
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       ZIPDEBUGFLAG(dbg, false);
+       rtx     insn;
+       rtx     insn;
+
+
+       zip_compute_frame();
+       zip_compute_frame();
+
+
+       if (dbg) fprintf(stderr, "EPILOG::\n");
+       if (dbg) fprintf(stderr, "EPILOG::\n");
Line 1396... Line 1596...
+               // enough so that you must have a frame pointer, then you can't
+               // enough so that you must have a frame pointer, then you can't
+               // trust its offset enough to restore from it.  Hence, we start
+               // trust its offset enough to restore from it.  Hence, we start
+               // by moving the frame pointer to the stack pointer to recover
+               // by moving the frame pointer to the stack pointer to recover
+               // the stack pointer back to a usable value.
+               // the stack pointer back to a usable value.
+               if (dbg) fprintf(stderr, "SIBCALL-EPILOG::Moving frame pointer to stack register\n");
+               if (dbg) fprintf(stderr, "SIBCALL-EPILOG::Moving frame pointer to stack register\n");
+               insn = emit_insn(gen_movsi_reg(stack_pointer_rtx, frame_pointer_rtx));
+               insn = emit_insn(gen_movsi_raw(stack_pointer_rtx, frame_pointer_rtx));
+               RTX_FRAME_RELATED_P(insn) = 1;
+               RTX_FRAME_RELATED_P(insn) = 1;
+       }
+       }
+
+
+       if (cfun->machine->saved_reg_size != 0) {
+       if (cfun->machine->saved_reg_size != 0) {
+               if (cfun->machine->fp_needed)
+               if (cfun->machine->fp_needed)
Line 1413... Line 1613...
+                               if (dbg) fprintf(stderr, "SIBCALL-EPILOG::RESTORING R%d\n", regno);
+                               if (dbg) fprintf(stderr, "SIBCALL-EPILOG::RESTORING R%d\n", regno);
+                               rtx reg = gen_rtx_REG(SImode, regno);
+                               rtx reg = gen_rtx_REG(SImode, regno);
+                               insn = emit_insn(gen_movsi_lod_off(
+                               insn = emit_insn(gen_movsi_lod_off(
+                                               reg,
+                                               reg,
+                                               stack_pointer_rtx,
+                                               stack_pointer_rtx,
+                                               GEN_INT(offset++)));
+                                               GEN_INT(offset)));
+                               add_reg_note(insn, REG_CFA_RESTORE, reg);
+                               add_reg_note(insn, REG_CFA_RESTORE, reg);
+                               RTX_FRAME_RELATED_P(insn) = 1;
+                               RTX_FRAME_RELATED_P(insn) = 1;
 
+                               offset += 4;
+                       }
+                       }
+               }
+               }
+       }
+       }
+
+
+       if (cfun->machine->fp_needed) {
+       if (cfun->machine->fp_needed) {
+               // Restore the stack pointer back to the original, the
+               // Restore the stack pointer back to the original, the
+               // difference being the difference from the frame pointer
+               // difference being the difference from the frame pointer
+               // to the original stack
+               // to the original stack
+               insn = emit_insn(gen_addsi3_reg_clobber(stack_pointer_rtx,
+               insn = emit_insn(gen_addsi3(stack_pointer_rtx, stack_pointer_rtx,
+                       stack_pointer_rtx,
 
+                       GEN_INT(cfun->machine->size_for_adjusting_sp
+                       GEN_INT(cfun->machine->size_for_adjusting_sp
+                               -cfun->machine->sp_fp_offset)));
+                               -cfun->machine->sp_fp_offset)));
+               RTX_FRAME_RELATED_P(insn) = 1;
+               RTX_FRAME_RELATED_P(insn) = 1;
+       } else {
+       } else {
+               // else now the difference is between the stack pointer and
+               // else now the difference is between the stack pointer and
+               // the original stack pointer.
+               // the original stack pointer.
+               if (dbg) fprintf(stderr, "SIBCALL-EPILOG::ADDSI3(StackPtr, %d)\n",
+               if (dbg) fprintf(stderr, "SIBCALL-EPILOG::ADDSI3(StackPtr, %d)\n",
+                               cfun->machine->size_for_adjusting_sp);
+                               cfun->machine->size_for_adjusting_sp);
+               insn = emit_insn(gen_addsi3_reg_clobber(stack_pointer_rtx,
+               insn = emit_insn(gen_addsi3(stack_pointer_rtx,stack_pointer_rtx,
+                       stack_pointer_rtx,
 
+                       GEN_INT(cfun->machine->size_for_adjusting_sp)));
+                       GEN_INT(cfun->machine->size_for_adjusting_sp)));
+               RTX_FRAME_RELATED_P(insn) = 1;
+               RTX_FRAME_RELATED_P(insn) = 1;
+       }
+       }
+}
+}
+
+
 
+rtx
 
+zip_return_addr_rtx(int count, rtx frame ATTRIBUTE_UNUSED)
 
+{
 
+       //
 
+       // Don't try to compute anything other than frame zero.
 
+       //
 
+       if (count != 0)
 
+               return NULL_RTX;
 
+
 
+       // Make sure we've computed our frame, do we need to save registers?
 
+       zip_compute_frame();
 
+
 
+       if (zip_save_reg(zip_LR)) {
 
+               if (cfun->machine->fp_needed)
 
+                       return gen_rtx_MEM(SImode, frame_pointer_rtx);
 
+               else
 
+                       return gen_rtx_MEM(SImode, gen_rtx_PLUS(Pmode,
 
+                                       stack_pointer_rtx,
 
+                                       GEN_INT(cfun->machine->sp_fp_offset)));
 
+       } else {
 
+               return gen_rtx_REG(Pmode, zip_LR);
 
+
 
+       }
 
+}
 
+
+/* Implement RETURN_ADDR_RTX(COUNT, FRAMEADDR).
+/* Implement RETURN_ADDR_RTX(COUNT, FRAMEADDR).
+ *
+ *
+ * We currently only support calculating the return address for the current
+ * We currently only support calculating the return address for the current
+ * frame.
+ * frame.
+ */
+ */
Line 1521... Line 1745...
+       if ((from == zip_FP)&&(to == zip_SP))
+       if ((from == zip_FP)&&(to == zip_SP))
+               return !cfun->machine->fp_needed;
+               return !cfun->machine->fp_needed;
+       return true;
+       return true;
+}
+}
+
+
+/*
 
+static void
 
+zip_basic_check(void)
 
+{
 
+       gcc_assert(mode_base_align[SImode]==4);
 
+       if ((BITS_PER_UNIT != 32)
 
+                       ||(GET_MODE_SIZE(SImode)!=1)
 
+                       ||(GET_MODE_SIZE(DImode)!=1)
 
+                       ||(HARD_REGNO_NREGS(0,SImode)!=1)) {
 
+               printf("SIZEOF(SIMode) == %d\n", GET_MODE_SIZE(SImode));
 
+               printf("BITS_PER_UNIT  == %d\n", BITS_PER_UNIT);
 
+               gcc_assert(BITS_PER_UNIT==32);
 
+               gcc_assert(GET_MODE_SIZE(SImode)==1);
 
+               gcc_assert(HARD_REGNO_NREGS(0,SImode)==1);
 
+       }
 
+}
 
+*/
 
+
 
+#define        zip_basic_check()
 
+
 
+/* Compute the number of word sized registers needed to hold a function
+/* Compute the number of word sized registers needed to hold a function
+ * argument of mode INT_MODE and tree type TYPE.
+ * argument of mode INT_MODE and tree type TYPE.
+ */
+ */
+int
+int
+zip_num_arg_regs(enum machine_mode mode, const_tree type) {
+zip_num_arg_regs(enum machine_mode mode, const_tree type) {
+       int     size;
+       int     size;
+
+
+       zip_basic_check();
 
+
 
+       if (targetm.calls.must_pass_in_stack(mode, type))
+       if (targetm.calls.must_pass_in_stack(mode, type))
+               return 0;
+               return 0;
+
+
+       if ((type)&&(mode == BLKmode))
+       if ((type)&&(mode == BLKmode))
+               size = int_size_in_bytes(type);
+               size = int_size_in_bytes(type);
Line 1567... Line 1769...
+zip_function_arg_advance(cumulative_args_t ca, machine_mode mode,
+zip_function_arg_advance(cumulative_args_t ca, machine_mode mode,
+               const_tree type, bool named ATTRIBUTE_UNUSED) {
+               const_tree type, bool named ATTRIBUTE_UNUSED) {
+       CUMULATIVE_ARGS *cum;
+       CUMULATIVE_ARGS *cum;
+       int     nreg;
+       int     nreg;
+
+
+       zip_basic_check();
 
+
 
+       cum = get_cumulative_args(ca);
+       cum = get_cumulative_args(ca);
+       nreg = zip_num_arg_regs(mode, type);
+       nreg = zip_num_arg_regs(mode, type);
+       if (((*cum)+nreg) > NUM_ARG_REGS)
+       if (((*cum)+nreg) > NUM_ARG_REGS)
+               (*cum) = NUM_ARG_REGS;
+               (*cum) = NUM_ARG_REGS;
+       else
+       else
Line 1582... Line 1782...
+static rtx
+static rtx
+zip_function_arg(cumulative_args_t ca, machine_mode mode,
+zip_function_arg(cumulative_args_t ca, machine_mode mode,
+               const_tree type ATTRIBUTE_UNUSED, bool named) {
+               const_tree type ATTRIBUTE_UNUSED, bool named) {
+       CUMULATIVE_ARGS *cum;
+       CUMULATIVE_ARGS *cum;
+
+
+       zip_basic_check();
 
+
 
+
 
+       if (!named)
+       if (!named)
+               return NULL_RTX;
+               return NULL_RTX;
+       //if (targetm.calls.must_pass_in_stack(mode, type))
 
+               //return NULL_RTX;
 
+       cum = get_cumulative_args(ca);
+       cum = get_cumulative_args(ca);
+
+
+       if ((*cum) >= NUM_ARG_REGS)
+       if ((*cum) >= NUM_ARG_REGS)
+               return NULL_RTX;
+               return NULL_RTX;
+       return
+       return
Line 1679... Line 1874...
+}
+}
+
+
+void   zip_canonicalize_comparison(int *code, rtx *op0, rtx *op1,
+void   zip_canonicalize_comparison(int *code, rtx *op0, rtx *op1,
+               bool preserve_op0)
+               bool preserve_op0)
+{
+{
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       ZIPDEBUGFLAG(dbg, false);
 
+       bool    reverse = false;
+
+
+       if (dbg) fprintf(stderr, "CANONICALIZE ...%s\n", (preserve_op0)?"(Preserve Op0)":"");
+       if (dbg) fprintf(stderr, "CANONICALIZE ...%s\n", (preserve_op0)?"(Preserve Op0)":"");
+       if (dbg) zip_debug_rtx_pfx("CODE", gen_rtx_fmt_ee((rtx_code)*code, VOIDmode, gen_rtx_REG(CCmode,zip_CC), const0_rtx));
+       if (dbg) zip_debug_rtx_pfx("CODE", gen_rtx_fmt_ee((rtx_code)*code, VOIDmode, gen_rtx_REG(CCmode,zip_CC), const0_rtx));
+       if (dbg) zip_debug_rtx_pfx("OP0 ", *op0);
+       if (dbg) zip_debug_rtx_pfx("OP0 ", *op0);
+       if (dbg) zip_debug_rtx_pfx("OP1 ", *op1);
+       if (dbg) zip_debug_rtx_pfx("OP1 ", *op1);
+
+
+       if ((!preserve_op0)&&((*code == LE)||(*code == GTU)||(*code == GEU))) {
+       // Z    ->      Z
+               rtx tem = *op0;
+       // NZ   ->      !Z
 
+       // LT   ->      N
 
+       // GE   ->      !N
 
+       // LTU  ->      C
 
+       // GEU  ->      !C
 
+       //
 
+       // LTE  ->      GTE w/ swapped operands
 
+       // GT   ->      LT  w/ swapped operands
 
+       // GTU  ->      LTU w/ swapped operands
 
+       // LEU  ->      GEU w/ swapped operands
 
+       //
 
+
 
+       if ((CONST_INT_P(*op0))||(GET_CODE(*op0) == PLUS)) {
 
+               rtx     tmp = *op0;
+               *op0 = *op1;
+               *op0 = *op1;
+               *op1 = tem;
+               *op1 = tmp;
+               *code = (int)swap_condition((enum rtx_code)*code);
+               *code = (int)swap_condition((enum rtx_code)*code);
+       }
+       }
+
+
+       if ((*code == LE)||(*code == LEU)||(*code == GTU)) {
+       if (*code == GTU) {
+               int offset = 1; // (*code == GTU) ? 1 : -1;
+               if (REG_P(*op1)) {
+               bool    swap = false;
+                       //; Reverse the comparison
+
+                       reverse = true;
+               if (CONST_INT_P(*op1)) {
+               } else if (CONST_INT_P(*op1)) {
+                       *op1 = GEN_INT(INTVAL(*op1)+offset);
+                       //; A >  B
+                       swap = true;
+                       //; A >= B+1
+               } else if (REG_P(*op1)) {
+                       //; Add one to the integer constant,
+                       *op1 = plus_constant(GET_MODE(*op1), *op1, offset, true);
+                       //; And use a GEU comparison
+                       swap = true;
+                       *code = GEU;
+               } else if ((GET_CODE(*op1)==PLUS)&&(CONST_INT_P(XEXP(*op1,1)))){
+                       *op1 = GEN_INT(INTVAL(*op1)+1);
+                       *op1 = plus_constant(GET_MODE(*op1),XEXP(*op1,0),
+               } else {
+                               INTVAL(XEXP(*op1,1))+offset);
+                       //; Reverse the comparison
+                       swap = true;
+                       reverse = true;
+               } if (swap) {
+               }
+                       if (*code == LE)
+       } else if (*code == LEU) {
+                               (*code)= LT;
+               if (REG_P(*op1)) {
+                       else if (*code == LEU)
+                       reverse = true;
+                               (*code)= LTU;
+               } else if (CONST_INT_P(*op1)) {
+                       else // (*code == GTU)
+                       //; A <= B
+                               (*code) = GEU;
+                       //; A <  B+1
 
+                       //; Add one to the integer constant,
 
+                       //; And use a GTU comparison
 
+                       *op1 = GEN_INT(INTVAL(*op1)+1);
 
+                       *code = LTU;
 
+               } else {
 
+                       reverse = true;
 
+               }
 
+       } else if (*code == LE) {
 
+               if (REG_P(*op1)) {
 
+                       reverse = true;
 
+               } else if (CONST_INT_P(*op1)) {
 
+                       //; A <  B
 
+                       //; A <= B-1
 
+                       //; Add one to the integer constant,
 
+                       //; And use a GTU comparison
 
+                       *op1 = GEN_INT(INTVAL(*op1)-1);
 
+                       *code = LT;
 
+               } else {
 
+                       reverse = true;
+               }
+               }
 
+       } else if (*code == GT) {
 
+               if (REG_P(*op1)) {
 
+                       //; Reverse the comparison
 
+                       reverse = true;
 
+               } else if (CONST_INT_P(*op1)) {
 
+                       //; A >  B
 
+                       //; A >= B+1
 
+                       //; Add one to the integer constant,
 
+                       //; And use a GTU comparison
 
+                       *op1 = GEN_INT(INTVAL(*op1)+1);
 
+                       *code = GE;
 
+               } else {
 
+                       reverse = true;
 
+               }
 
+       }
 
+
 
+       if (reverse) {
 
+               rtx tem = *op0;
 
+               *op0 = *op1;
 
+               *op1 = tem;
 
+               *code = (int)swap_condition((enum rtx_code)*code);
+       }
+       }
+}
+}
+
+
+static bool
+static bool
+zip_fixed_condition_code_regs(unsigned int *a, unsigned int *b) {
+zip_fixed_condition_code_regs(unsigned int *a, unsigned int *b) {
Line 1728... Line 1977...
+}
+}
+
+
+
+
+/* totally buggy - we can't return pointers to nested functions */
+/* totally buggy - we can't return pointers to nested functions */
+static void
+static void
+zip_asm_trampoline_template(FILE *f) {
+zip_asm_trampoline_template(FILE *f)
+       // Whereas at one time I thought I wouldn't need it, now I know I
+{
+       // need this trampoline function, although it is for a completely
 
+       // different purpose than the one I was familiar with.
 
+       fprintf(f, "\tbrev\t0,r1\n");
+       fprintf(f, "\tbrev\t0,r1\n");
+       fprintf(f, "\tldilo\t0,r1\n");
+       fprintf(f, "\tldilo\t0,r1\n");
+       fprintf(f, "\tjmp r1\n");
+       fprintf(f, "\tjmp r1\n");
+}
+}
+
+
Line 1751... Line 1998...
+static tree
+static tree
+def_builtin(const char *name, enum insn_code icode, enum ZIP_BUILTIN_ID_CODE code,
+def_builtin(const char *name, enum insn_code icode, enum ZIP_BUILTIN_ID_CODE code,
+       tree type)
+       tree type)
+{
+{
+       tree t = add_builtin_function(name,type,code,BUILT_IN_MD, NULL, NULL_TREE);
+       tree t = add_builtin_function(name,type,code,BUILT_IN_MD, NULL, NULL_TREE);
+       zip_basic_check();
 
+
+
+       if(t) {
+       if(t) {
+               zip_builtins[code] = t;
+               zip_builtins[code] = t;
+               zip_builtins_icode[code] = icode;
+               zip_builtins_icode[code] = icode;
+       }
+       }
Line 1763... Line 2009...
+       return t;
+       return t;
+
+
+}
+}
+
+
+void   zip_init_builtins(void) {
+void   zip_init_builtins(void) {
+       zip_basic_check();
 
+
+
+  tree void_ftype_void = build_function_type_list(void_type_node, NULL_TREE);
+  tree void_ftype_void = build_function_type_list(void_type_node, NULL_TREE);
+#ifdef HAVE_zip_rtu
+#ifdef HAVE_zip_rtu
+  def_builtin("zip_rtu", CODE_FOR_zip_rtu, ZIP_BUILTIN_RTU, void_ftype_void);
+  def_builtin("zip_rtu", CODE_FOR_zip_rtu, ZIP_BUILTIN_RTU, void_ftype_void);
+#endif
+#endif
Line 1826... Line 2071...
+
+
+static rtx
+static rtx
+zip_expand_builtin(tree exp, rtx target,
+zip_expand_builtin(tree exp, rtx target,
+               rtx subtarget ATTRIBUTE_UNUSED,
+               rtx subtarget ATTRIBUTE_UNUSED,
+               machine_mode tmode ATTRIBUTE_UNUSED,
+               machine_mode tmode ATTRIBUTE_UNUSED,
+               int     ignore ATTRIBUTE_UNUSED) {
+               int     ignore ATTRIBUTE_UNUSED)
+
+{
+       tree    fndecl = TREE_OPERAND(CALL_EXPR_FN(exp), 0);
+       tree    fndecl = TREE_OPERAND(CALL_EXPR_FN(exp), 0);
+       bool    nonvoid = (TREE_TYPE(TREE_TYPE(fndecl)) != void_type_node);
+       bool    nonvoid = (TREE_TYPE(TREE_TYPE(fndecl)) != void_type_node);
+       enum    ZIP_BUILTIN_ID_CODE code=(enum ZIP_BUILTIN_ID_CODE)DECL_FUNCTION_CODE(fndecl);
+       enum    ZIP_BUILTIN_ID_CODE code=(enum ZIP_BUILTIN_ID_CODE)DECL_FUNCTION_CODE(fndecl);
+       enum    insn_code icode = zip_builtins_icode[code];
+       enum    insn_code icode = zip_builtins_icode[code];
+       rtx     pat, op[5];
+       rtx     pat, op[5];
Line 1867... Line 2112...
+       emit_insn(pat);
+       emit_insn(pat);
+       return (nonvoid ? target : const0_rtx);
+       return (nonvoid ? target : const0_rtx);
+}
+}
+
+
+static bool
+static bool
+zip_scalar_mode_supported_p(enum machine_mode mode) {
+zip_scalar_mode_supported_p(enum machine_mode mode)
+       zip_basic_check();
+{
+
+       if ((ZIP_HAS_DI)&&(mode == DImode))
+       return ((mode)==SImode)||((mode)==DImode); // ||((mode)==SFmode);
+               return true;
 
+       if ((mode==SImode)||(mode==HImode)||(mode==QImode))
 
+               return true;
 
+       if (mode==SFmode)       // &&(ZIP_FPU)
 
+               return true;    // If (!ZIP_CPU), will need to be emulated
 
+       if (mode==DFmode)       // Must always be emulated
 
+               return true;
 
+       return false;
+}
+}
+
+
+static bool
+static bool
+zip_libgcc_floating_mode_supported_p(enum machine_mode mode) {
+zip_libgcc_floating_mode_supported_p(enum machine_mode mode)
 
+{
+       return ((mode)==SFmode)||((mode)==DFmode);
+       return ((mode)==SFmode)||((mode)==DFmode);
+}
+}
+
+
+static int
+static int
+zip_address_cost(rtx addr ATTRIBUTE_UNUSED,
+zip_address_cost(rtx addr ATTRIBUTE_UNUSED,
Line 1891... Line 2144...
+zip_mode_dependent_address_p(const_rtx addr ATTRIBUTE_UNUSED,
+zip_mode_dependent_address_p(const_rtx addr ATTRIBUTE_UNUSED,
+       addr_space_t as ATTRIBUTE_UNUSED) {
+       addr_space_t as ATTRIBUTE_UNUSED) {
+       return false;
+       return false;
+}
+}
+
+
+/*
 
+static void
 
+zip_asm_output_anchor(rtx x) {
 
+       printf("ANCHOR: OP(%d)\n", GET_CODE(x));
 
+}
 
+*/
 
+
 
+static void
+static void
+zip_debug_print(const char *pfx, int lvl, const char *str) {
+zip_debug_print(const char *pfx, int lvl, const char *str) {
+       int     i;
+       int     i;
+       i = lvl;
+       i = lvl;
+       if ((true)||(lvl == 0))
+       if ((true)||(lvl == 0))
Line 1932... Line 2178...
+                       fprintf(stderr, "%s:BLK\n", str);
+                       fprintf(stderr, "%s:BLK\n", str);
+                       break;
+                       break;
+               case BImode:
+               case BImode:
+                       fprintf(stderr, "%s:BI\n", str);
+                       fprintf(stderr, "%s:BI\n", str);
+                       break;
+                       break;
+#ifdef HAVE_QImode
 
+               case QImode:
+               case QImode:
+                       fprintf(stderr, "%s:QI\n", str);
+                       fprintf(stderr, "%s:QI\n", str);
+                       break;
+                       break;
+#endif
 
+#ifdef HAVE_HImode
 
+               case HImode:
+               case HImode:
+                       fprintf(stderr, "%s:HI\n", str);
+                       fprintf(stderr, "%s:HI\n", str);
+                       break;
+                       break;
+#endif
+#ifdef HAVE_SImode
+               case SImode:
+               case SImode:
+                       fprintf(stderr, "%s:SI\n", str);
+                       fprintf(stderr, "%s:SI\n", str);
+                       break;
+                       break;
+               case CCmode:
+#endif
+                       fprintf(stderr, "%s:CC\n", str);
+#ifdef HAVE_DImode
+                       break;
 
+               case DImode:
+               case DImode:
+                       fprintf(stderr, "%s:DI\n", str);
+                       fprintf(stderr, "%s:DI\n", str);
+                       break;
+                       break;
 
+#endif
 
+               case CCmode:
 
+                       fprintf(stderr, "%s:CC\n", str);
 
+                       break;
+               default:
+               default:
+                       fprintf(stderr, "%s:?\n", str);
+                       fprintf(stderr, "%s:?\n", str);
+       }
+       }
+}
+}
+
+
Line 1970... Line 2216...
+               gcc_assert(0 && "Bad RTX Code");
+               gcc_assert(0 && "Bad RTX Code");
+               return;
+               return;
+       } switch(GET_CODE(x)) { // rtl.def
+       } switch(GET_CODE(x)) { // rtl.def
+       case PARALLEL:
+       case PARALLEL:
+               zip_debug_print(pfx, lvl, "(PARALLEL");
+               zip_debug_print(pfx, lvl, "(PARALLEL");
 
+               if (XVEC(x,0) != NULL)
+               for(int j=0; j<XVECLEN(x,0);j++)
+               for(int j=0; j<XVECLEN(x,0);j++)
+                       zip_debug_rtx_1(pfx, XVECEXP(x,0,j), lvl+1);
+                       zip_debug_rtx_1(pfx, XVECEXP(x,0,j), lvl+1);
+               zip_debug_print(pfx, lvl, ")");
+               zip_debug_print(pfx, lvl, ")");
+               debug_rtx(x);
+               debug_rtx(x);
+               break;
+               break;
Line 2056... Line 2303...
+               debug_rtx(x);
+               debug_rtx(x);
+               break;
+               break;
+       case REG: {
+       case REG: {
+               char buf[25], mstr[4];
+               char buf[25], mstr[4];
+               mstr[0] = '\0';
+               mstr[0] = '\0';
+               if (GET_MODE(x) == SImode)
+               if (GET_MODE(x) == QImode)
+                       strcpy(mstr, ":SI");
+                       strcpy(mstr, ":QI");
+               else if (GET_MODE(x) == DImode)
+               else if (GET_MODE(x) == HImode)
+                       strcpy(mstr, ":DI");
+                       strcpy(mstr, ":HI");
+               else if (GET_MODE(x) == VOIDmode)
+               else if (GET_MODE(x) == VOIDmode)
+                       strcpy(mstr, ":V");
+                       strcpy(mstr, ":V");
+               if (REGNO(x) == zip_PC)
+               if (REGNO(x) == zip_PC)
+                       sprintf(buf, "(PC%s)", mstr);
+                       sprintf(buf, "(PC%s)", mstr);
+               else if (REGNO(x) == zip_CC)
+               else if (REGNO(x) == zip_CC)
Line 2109... Line 2356...
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
+               zip_debug_print(pfx, lvl, ")");
+               zip_debug_print(pfx, lvl, ")");
+               break;
+               break;
+       case CONST_INT:
+       case CONST_INT:
+               { char buf[128];
+               { char buf[128];
+               if (GET_MODE(x)==SImode)
+               if (GET_MODE(x)==QImode)
+                       sprintf(buf, "(CONST_INT:SI %ld)", (long)INTVAL(x));
+                       sprintf(buf, "(CONST_INT:QI %ld)", (long)INTVAL(x));
+               else if (GET_MODE(x)==VOIDmode)
+               else if (GET_MODE(x)==VOIDmode)
+                       sprintf(buf, "(CONST_INT:V %ld)", (long)INTVAL(x));
+                       sprintf(buf, "(CONST_INT:V %ld, %016lx)", (long)INTVAL(x),
 
+                               (unsigned long)INTVAL(x));
+               else
+               else
+                       sprintf(buf, "(CONST_INT:? %ld)", (long)INTVAL(x));
+                       sprintf(buf, "(CONST_INT:? %ld)", (long)INTVAL(x));
+               zip_debug_print(pfx, lvl, buf);
+               zip_debug_print(pfx, lvl, buf);
+               } break;
+               } break;
+       case LABEL_REF:
+       case LABEL_REF:
Line 2125... Line 2373...
+               zip_debug_print(pfx, lvl, buf);
+               zip_debug_print(pfx, lvl, buf);
+               }
+               }
+               break;
+               break;
+       case SYMBOL_REF:
+       case SYMBOL_REF:
+               {
+               {
+                       char buf[128];
+                       char buf[1024];
+                       sprintf(buf, "(SYMBOL: %s)", XSTR(x,0));
+                       sprintf(buf, "(SYMBOL: %s)", XSTR(x,0));
+                       // fprintf(file, "%s", XSTR(x,0));
+                       // fprintf(file, "%s", XSTR(x,0));
+                       zip_debug_print(pfx, lvl, buf);
+                       zip_debug_print(pfx, lvl, buf);
+               }
+               }
+               break;
+               break;
Line 2245... Line 2493...
+               break;
+               break;
+       case SCRATCH:   //
+       case SCRATCH:   //
+               zip_debug_print_m(pfx, lvl, "(SCRATCH)", GET_MODE(x));
+               zip_debug_print_m(pfx, lvl, "(SCRATCH)", GET_MODE(x));
+               break;
+               break;
+       case SUBREG:
+       case SUBREG:
+               { char buf[25];
+               { char buf[64], mstr[8];
 
+               if (GET_MODE(x) == QImode)
 
+                       strcpy(mstr, ":QI");
 
+               else if (GET_MODE(x) == HImode)
 
+                       strcpy(mstr, ":HI");
 
+               else if (GET_MODE(x) == SImode)
 
+                       strcpy(mstr, ":SI");
 
+               else if (GET_MODE(x) == VOIDmode)
 
+                       strcpy(mstr, ":V");
 
+               else
 
+                       strcpy(mstr, ":?");
+               if (REG_P(XEXP(x,0))) {
+               if (REG_P(XEXP(x,0))) {
+                       sprintf(buf, "(SUBREG %d/%d)", REGNO(XEXP(x,0)),
+                       int hreg = REGNO(XEXP(x,0)), mod = GET_MODE(XEXP(x,0)),
+                               SUBREG_BYTE(x));
+                               sb = SUBREG_BYTE(x);
 
+                       if (mod==QImode)
 
+                       sprintf(buf,"(SUBREG%s (REG:QI %d)/%d)",mstr,hreg, sb);
 
+                       else if (mod==HImode)
 
+                       sprintf(buf,"(SUBREG%s (REG:HI %d)/%d)",mstr,hreg, sb);
 
+                       else if (mod==QImode)
 
+                       sprintf(buf,"(SUBREG%s (REG:QI %d)/%d)",mstr,hreg, sb);
 
+                       else if (mod==VOIDmode)
 
+                       sprintf(buf,"(SUBREG%s (REG:V %d)/%d)",mstr,hreg, sb);
 
+                       else
 
+                       sprintf(buf,"(SUBREG%s %d:?/%d)",mstr,hreg, sb);
+                       zip_debug_print(pfx, lvl, buf);
+                       zip_debug_print(pfx, lvl, buf);
+               } else if (MEM_P(XEXP(x,0))) {
+               } else if (MEM_P(XEXP(x,0))) {
+                       sprintf(buf, "(SUBREG /%d", SUBREG_BYTE(x));
+                       sprintf(buf, "(SUBREG%s /%d", mstr,SUBREG_BYTE(x));
+                       zip_debug_print(pfx, lvl, buf);
+                       zip_debug_print(pfx, lvl, buf);
+                       zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
+                       zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
+                       zip_debug_print(pfx, lvl, ")");
+                       zip_debug_print(pfx, lvl, ")");
+               } else {
+               } else {
+                       sprintf(buf, "(SUBREG UNK /%d", SUBREG_BYTE(x));
+                       sprintf(buf, "(SUBREG%s UNK /%d", mstr,SUBREG_BYTE(x));
+                       zip_debug_print(pfx, lvl, buf);
+                       zip_debug_print(pfx, lvl, buf);
+                       zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
+                       zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
+                       zip_debug_print(pfx, lvl, ")");
+                       zip_debug_print(pfx, lvl, ")");
+               }}
+               }}
+               break;
+               break;
Line 2280... Line 2548...
+               zip_debug_print_m(pfx, lvl, "(LSHIFTRT", GET_MODE(x));
+               zip_debug_print_m(pfx, lvl, "(LSHIFTRT", GET_MODE(x));
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
+               zip_debug_print(pfx, lvl, ")");
+               zip_debug_print(pfx, lvl, ")");
+               break;
+               break;
 
+       case ZERO_EXTRACT:
 
+               zip_debug_print_m(pfx, lvl, "(ZERO_EXTRACT", GET_MODE(x));
 
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
 
+               zip_debug_print(pfx, lvl, ")");
 
+               break;
 
+       case ZERO_EXTEND:
 
+               zip_debug_print_m(pfx, lvl, "(ZERO_EXTEND", GET_MODE(x));
 
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
 
+               zip_debug_print(pfx, lvl, ")");
 
+               break;
+       default:
+       default:
+               { char buf[128];
+               { char buf[128];
+               sprintf(buf, "(? = %d) -- calling DEBUG-RTX", GET_CODE(x));
+               sprintf(buf, "(? = %d) -- calling DEBUG-RTX", GET_CODE(x));
+               zip_debug_print(pfx, lvl, buf);
+               zip_debug_print(pfx, lvl, buf);
+               debug_rtx(x);
+               debug_rtx(x);
Line 2304... Line 2582...
+void
+void
+zip_debug_ccode(int ccode) {
+zip_debug_ccode(int ccode) {
+       switch(ccode) {
+       switch(ccode) {
+       case    EQ: fprintf(stderr, "EQ"); break;
+       case    EQ: fprintf(stderr, "EQ"); break;
+       case    NE: fprintf(stderr, "NE"); break;
+       case    NE: fprintf(stderr, "NE"); break;
+       case    GT: fprintf(stderr, "GT"); break;
 
+       case    GE: fprintf(stderr, "GE"); break;
+       case    GE: fprintf(stderr, "GE"); break;
+       case    LT: fprintf(stderr, "LT"); break;
+       case    LT: fprintf(stderr, "LT"); break;
+       case    LE: fprintf(stderr, "LE"); break;
 
+       case    GTU: fprintf(stderr, "GTU"); break;
 
+       case    GEU: fprintf(stderr, "GEU"); break;
 
+       case    LTU: fprintf(stderr, "LTU"); break;
+       case    LTU: fprintf(stderr, "LTU"); break;
+       case    LEU: fprintf(stderr, "LEU"); break;
+       case    GEU: fprintf(stderr, "GEU"); break;
 
+       case    GT: fprintf(stderr, "GT[!]"); break;
 
+       case    LE: fprintf(stderr, "LE[!]"); break;
 
+       case    GTU: fprintf(stderr, "GTU[!]"); break;
 
+       case    LEU: fprintf(stderr, "LEU[!]"); break;
+       default:
+       default:
+               fprintf(stderr, "%d", ccode); break;
+               fprintf(stderr, "%d", ccode); break;
+       }
+       }
+}
+}
+
+
Line 2336... Line 2614...
+
+
+
+
+static bool
+static bool
+zip_legitimate_opb(rtx x, bool strict)
+zip_legitimate_opb(rtx x, bool strict)
+{
+{
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       ZIPDEBUGFLAG(dbg, false);
+
+
+       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB\n");
+       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB\n");
+       if (dbg) zip_debug_rtx_pfx("Test: ", x);
+       if (dbg) zip_debug_rtx_pfx("Test: ", x);
+
+
+       if (NULL_RTX == x)
+       if (NULL_RTX == x)
+               return false;
+               return false;
+       else if ((GET_MODE(x) != SImode)&&(GET_MODE(x) != VOIDmode)) {
+       else if ((GET_MODE(x) != QImode)
 
+                       &&(GET_MODE(x) != HImode)
 
+                       &&(GET_MODE(x) != SImode)
 
+                       &&(GET_MODE(x) != VOIDmode)) {
+               if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> Mode failure\n");
+               if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> Mode failure\n");
+               return false;
+               return false;
+       } else if ((strict)&&(REG_P(x))) {
+       } else if ((strict)&&(REG_P(x))) {
+               if (REGNO(x)<zip_CC) {
+               if (REGNO(x)<zip_CC) {
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> (Reg)\n");
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> (Reg)\n");
Line 2364... Line 2645...
+               return true;
+               return true;
+       // } else if ((GET_CODE(x) == LABEL_REF)||(GET_CODE(x)==CODE_LABEL)) {
+       // } else if ((GET_CODE(x) == LABEL_REF)||(GET_CODE(x)==CODE_LABEL)) {
+               // return true;
+               // return true;
+       } else if (GET_CODE(x) == PLUS) {
+       } else if (GET_CODE(x) == PLUS) {
+               // Is it a valid register?
+               // Is it a valid register?
+               if ((!strict)&&(!register_operand((rtx)XEXP((rtx)x,0), GET_MODE(x)))) {
+               rtx     regrtx = XEXP(x, 0);
 
+               if ((!strict)&&(!REG_P(regrtx))) {
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No (No reg in +%s)\n",
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No (No reg in +%s)\n",
+                       (GET_CODE(XEXP(x,1))==REG)?", reg in op[1]":"");
+                       (GET_CODE(XEXP(x,1))==REG)?", reg in op[1]":"");
+                       return false;
+                       return false;
+               } else if ((strict)&&((!REG_P(XEXP(x,0)))||(REGNO(XEXP(x,0))>=zip_CC))) {
+               } else if ((strict)&&((!REG_P(XEXP(x,0)))||(REGNO(XEXP(x,0))>=zip_CC))) {
+                       return false;
+                       return false;
Line 2396... Line 2678...
+       return false;
+       return false;
+}
+}
+
+
+static bool
+static bool
+zip_legitimate_move_operand_p(machine_mode mode ATTRIBUTE_UNUSED, rtx x, bool strict) {
+zip_legitimate_move_operand_p(machine_mode mode ATTRIBUTE_UNUSED, rtx x, bool strict) {
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       const bool      dbg = ((ZIP_ALL_DEBUG_ON)||(false))&&(!ZIP_ALL_DEBUG_OFF);
+
+
+       if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND\n");
+       if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND\n");
+       if (dbg) zip_debug_rtx_pfx("VMov?: ", x);
+       if (dbg) zip_debug_rtx_pfx("VMov?: ", x);
+
+
+       if (!zip_legitimate_opb(x, strict))
+       if (!zip_legitimate_opb(x, strict))
Line 2419... Line 2701...
+}
+}
+
+
+int
+int
+zip_pd_mov_operand(rtx op)
+zip_pd_mov_operand(rtx op)
+{
+{
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       const bool      dbg = ((ZIP_ALL_DEBUG_ON)||(false))&&(!ZIP_ALL_DEBUG_OFF);
+
+
+       if (dbg) fprintf(stderr, "ZIP-VALID-MOV(predicate) for OPERAND\n");
+       if (dbg) fprintf(stderr, "ZIP-VALID-MOV(predicate) for OPERAND\n");
+       return zip_legitimate_move_operand_p(VOIDmode, op, !can_create_pseudo_p());
+       return zip_legitimate_move_operand_p(VOIDmode, op, !can_create_pseudo_p());
+}
+}
+
+
+int
+int
+zip_pd_mvimm_operand(rtx op)
+zip_pd_mvimm_operand(rtx op)
+{
+{
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       const bool      dbg = ((ZIP_ALL_DEBUG_ON)||(false))&&(!ZIP_ALL_DEBUG_OFF);
+
+
+       if (dbg) fprintf(stderr, "ZIP-VALID-MVIMM(predicate) for OPERAND\n");
+       if (dbg) fprintf(stderr, "ZIP-VALID-MVIMM(predicate) for OPERAND\n");
+       if (!CONST_INT_P(op))
+       if (!CONST_INT_P(op))
+               return false;
+               return false;
+       if (INTVAL(op) > zip_max_mov_offset)
+       if (INTVAL(op) > zip_max_mov_offset)
Line 2443... Line 2725...
+}
+}
+
+
+int
+int
+zip_pd_imm_operand(rtx op)
+zip_pd_imm_operand(rtx op)
+{
+{
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       const bool      dbg = ((ZIP_ALL_DEBUG_ON)||(false))&&(!ZIP_ALL_DEBUG_OFF);
+
+
+       if (dbg) fprintf(stderr, "ZIP-VALID-IMM(predicate) for OPERAND\n");
+       if (dbg) fprintf(stderr, "ZIP-VALID-IMM(predicate) for OPERAND\n");
+       if (!CONST_INT_P(op))
+       if (!CONST_INT_P(op))
+               return false;
+               return false;
+       if (INTVAL(op) > zip_max_anchor_offset)
+       if (INTVAL(op) > zip_max_anchor_offset)
Line 2458... Line 2740...
+}
+}
+
+
+int
+int
+zip_address_operand(rtx op)
+zip_address_operand(rtx op)
+{
+{
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       const bool      dbg = ((ZIP_ALL_DEBUG_ON)||(false))&&(!ZIP_ALL_DEBUG_OFF);
+
+
+       if (dbg) fprintf(stderr, "ZIP-ADDRESS for OPERAND\n");
+       if (dbg) fprintf(stderr, "ZIP-ADDRESS for OPERAND\n");
+       if ((REG_P(op))&&(REGNO(op)==zip_CC))
+       if ((REG_P(op))&&(REGNO(op)==zip_CC))
+               return false;
+               return false;
+       else if ((GET_CODE(op) == PLUS)&&(REG_P(XEXP(op,0)))
+       else if ((GET_CODE(op) == PLUS)&&(REG_P(XEXP(op,0)))
Line 2473... Line 2755...
+}
+}
+
+
+int
+int
+zip_pd_opb_operand(rtx op)
+zip_pd_opb_operand(rtx op)
+{
+{
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       ZIPDEBUGFLAG(dbg, false);
+
+
+       if (dbg) fprintf(stderr, "ZIP-OPB(predicate) for OPERAND\n");
+       if (dbg) fprintf(stderr, "ZIP-OPB(predicate) for OPERAND\n");
+       return zip_legitimate_opb(op, false); //, !can_create_pseudo_p());
+       return zip_legitimate_opb(op, false); //, !can_create_pseudo_p());
+}
+}
+
+
+int
+int
+zip_ct_address_operand(rtx op)
+zip_ct_address_operand(rtx op)
+{
+{
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       ZIPDEBUGFLAG(dbg, false);
+
+
+       if (dbg) fprintf(stderr, "ZIP-ADDRESS(constraint) for OPERAND\n");
+       if (dbg) fprintf(stderr, "ZIP-ADDRESS(constraint) for OPERAND\n");
+       return zip_legitimate_opb(op, !can_create_pseudo_p());
+       return zip_legitimate_opb(op, !can_create_pseudo_p());
+}
+}
+
+
+int
+int
+zip_const_address_operand(rtx x) {
+zip_const_address_operand(rtx x) {
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       ZIPDEBUGFLAG(dbg, false);
+
+
+       if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS?\n");
+       if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS?\n");
+       if (dbg) zip_debug_rtx(x);
+       if (dbg) zip_debug_rtx(x);
+       if ((GET_MODE(x) != SImode)&&(GET_MODE(x) != VOIDmode)) {
+       if ((GET_MODE(x) != SImode)&&(GET_MODE(x) != VOIDmode)) {
+               fprintf(stderr, "is ZIP-CONST-ADDRESS? -> NO, BAD MODE\n");
+               fprintf(stderr, "is ZIP-CONST-ADDRESS? -> NO, BAD MODE\n");
Line 2523... Line 2805...
+       return false;
+       return false;
+}
+}
+
+
+int
+int
+zip_ct_const_address_operand(rtx x) {
+zip_ct_const_address_operand(rtx x) {
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       ZIPDEBUGFLAG(dbg, false);
+
+
+       if (dbg) fprintf(stderr, "ZIP-CONST-ADDRESS(constraint)\n");
+       if (dbg) fprintf(stderr, "ZIP-CONST-ADDRESS(constraint)\n");
+       return zip_const_address_operand(x);
+       return zip_const_address_operand(x);
+}
+}
+
+
+int
+int
+zip_pd_const_address_operand(rtx x) {
+zip_pd_const_address_operand(rtx x) {
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       ZIPDEBUGFLAG(dbg, false);
+
+
+       if (dbg) fprintf(stderr, "ZIP-CONST-ADDRESS(predicate)\n");
+       if (dbg) fprintf(stderr, "ZIP-CONST-ADDRESS(predicate)\n");
+       return zip_const_address_operand(x);
+       return zip_const_address_operand(x);
+}
+}
+
+
+
+
+static bool
+static bool
+zip_legitimate_address_p(machine_mode mode ATTRIBUTE_UNUSED, rtx x, bool strict)
+zip_legitimate_address_p(machine_mode mode ATTRIBUTE_UNUSED, rtx x, bool strict)
+{
+{
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       ZIPDEBUGFLAG(dbg, false);
+
+
+       if (dbg) fprintf(stderr, "Zip-LEGITIMATE-ADDRESS-P\n");
+       if (dbg) fprintf(stderr, "Zip-LEGITIMATE-ADDRESS-P\n");
+       if (dbg) zip_debug_rtx(x);
+       if (dbg) zip_debug_rtx(x);
+
+
+       // Only insist the register be a valid register if strict is true
+       // Only insist the register be a valid register if strict is true
Line 2557... Line 2839...
+       return false;
+       return false;
+}
+}
+
+
+static rtx
+static rtx
+zip_legitimize_address(rtx x, rtx oldx ATTRIBUTE_UNUSED, machine_mode mode ATTRIBUTE_UNUSED) {
+zip_legitimize_address(rtx x, rtx oldx ATTRIBUTE_UNUSED, machine_mode mode ATTRIBUTE_UNUSED) {
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       ZIPDEBUGFLAG(dbg, false);
 
+
+
+
+       if (dbg) zip_debug_rtx_pfx("LEGITIMIZE: ", x);
+       if (dbg) zip_debug_rtx_pfx("LEGITIMIZE: ", x);
+       if (zip_legitimate_address_p(mode, x, !can_create_pseudo_p()))
+       if (zip_legitimate_address_p(mode, x, !can_create_pseudo_p()))
+               return x;
+               return x;
+
+
 
+       if (dbg) zip_debug_rtx_pfx("ILLEGITIMATE: ", x);
+       if (GET_CODE(x)==PLUS) {
+       if (GET_CODE(x)==PLUS) {
 
+               // if ((zip_legitimate_address_p(mode, XEXP(x,0),
 
+               //              !can_create_pseudo_p()))
 
+               //      &&(GETMODE(XEXP(x,1))==CONST_INT)) {
 
+               //}
+               if (!REG_P(XEXP(x,0)))
+               if (!REG_P(XEXP(x,0)))
+                       XEXP(x,0) = force_reg(GET_MODE(x),XEXP(x,0));
+                       XEXP(x,0) = force_reg(Pmode,XEXP(x,0));
+               if ((!zip_legitimate_address_p(mode, x, !can_create_pseudo_p()))
+               if ((!zip_legitimate_address_p(mode, x, !can_create_pseudo_p()))
+                       &&(!CONST_INT_P(XEXP(x,1))))
+                       &&(!CONST_INT_P(XEXP(x,1))))
+                       x = force_reg(GET_MODE(x),x);
+                       x = force_reg(GET_MODE(x),x);
+       } else if (MEM_P(x))
+       } else if (MEM_P(x))
+               x = force_reg(GET_MODE(x),x);
+               x = force_reg(GET_MODE(x),x);
Line 2579... Line 2867...
+}
+}
+
+
+void
+void
+zip_asm_output_def(FILE *stream, const char *name, const char *value)
+zip_asm_output_def(FILE *stream, const char *name, const char *value)
+{
+{
+       assemble_name(stream, name);
+       fprintf(stream, "\t.equ %s, %s\n", name, value);
+       fprintf(stream, "\t.equ ");
 
+       assemble_name(stream, value);
 
+       fputc('\n', stream);
 
+}
+}
+
+
+#define        USE_SUBREG
 
+#ifdef USE_SUBREG
 
+#define        SREG_P(RTX) ((SUBREG_P(RTX))&&(REG_P(XEXP(RTX,0))))
 
+#define        SMEM_P(RTX) ((SUBREG_P(RTX))&&(MEM_P(XEXP(RTX,0))))
 
+#else
 
+#define        SREG_P(RTX)     false
 
+#define        SMEM_P(RTX)     false
 
+#endif
 
+
 
+const char *zip_set_zero_or_one(rtx condition, rtx dst) {
+const char *zip_set_zero_or_one(rtx condition, rtx dst) {
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       ZIPDEBUGFLAG(dbg, false);
 
+
+       if (dbg) fprintf(stderr, "ZIP::SET-ZERO-OR-ONE\n");
+       if (dbg) fprintf(stderr, "ZIP::SET-ZERO-OR-ONE\n");
+       if (dbg) zip_debug_rtx_pfx("CND", condition);
+       if (dbg) zip_debug_rtx_pfx("CND", condition);
+       if (dbg) zip_debug_rtx_pfx("REG", dst);
+       if (dbg) zip_debug_rtx_pfx("REG", dst);
+       switch(GET_CODE(condition)) {
+       switch(GET_CODE(condition)) {
+       case EQ:        return "LDI\t0,%0\n\tLDILO.Z\t1,%0";
+       case EQ:        return "LDI\t0,%0\n\tLDILO.Z\t1,%0\t; set01_eq";
+       case NE:        return "LDI\t0,%0\n\tLDILO.NZ\t1,%0";
+       case NE:        return "LDI\t0,%0\n\tLDILO.NZ\t1,%0\t; set01_ne";
+       case LT:        return "LDI\t0,%0\n\tLDILO.LT\t1,%0";
+       case LT:        return "LDI\t0,%0\n\tLDILO.LT\t1,%0\t; set01_lt";
+       case GT:        return "LDI\t0,%0\n\tLDILO.GT\t1,%0";
+       case GT:        return "LDI\t1,%0\n\tLDILO.LT\t1,%0\n\tLDILO.Z\t1,%0\t; set01_gt";
+       case LE:        return "LDI\t1,%0\n\tLDILO.GT\t0,%0";
+       case LE:        return "LDI\t0,%0\n\tLDILO.LT\t1,%0\n\tLDILO.Z\t1,%0\t; set01_le";
+       case GE:        return "LDI\t0,%0\n\tLDILO.GE\t1,%0";
+       case GE:        return "LDI\t0,%0\n\tLDILO.GE\t1,%0\t; set01_ge";
+       case LTU:       return "LDI\t0,%0\n\tLDILO.C\t1,%0";
+       case LTU:       return "LDI\t0,%0\n\tLDILO.C\t1,%0\t; set01_ltu";
+       case GTU:       return "LDI\t1,%0\n\tLDILO.C\t0,%0\n\tLDILO.Z\t0,%0";
+       case GEU:       return "LDI\t0,%0\n\tLDILO.NC\t1,%0\t; set01_geu";
+       case LEU:       return "LDI\t0,%0\n\tLDILO.C\t1,%0\n\tLDILO.Z\t1,%0";
+       case GTU:       return "LDI\t1,%0\n\tLDILO.C\t0,%0\n\tLDILO.Z\t0,%0\t; set01_gtu";
+       case GEU:       return "LDI\t1,%0\n\tLDILO.C\t0,%0";
+       case LEU:       return "LDI\t0,%0\n\tLDILO.C\t1,%0\n\tLDILO.Z\t1,%0\t; set01_leu";
+       default:
+       default:
+               zip_debug_rtx(condition);
+               zip_debug_rtx(condition);
+               internal_error("CSTORE Unsupported condition");
+               internal_error("CSTORE Unsupported condition");
+               return NULL;
+               return NULL;
+       }
+       }
+}
+}
+
+
+/*
 
+const char *zip_binary_movsicc(rtx_code condition, const char *op, const int opno) {
 
+       static char     result[64] = "";
 
+       switch(condition) {
 
+               //
 
+               // Result already exists in the iffalse register
 
+               // Can't change it.  Therefore, on the
 
+               // condition ... move true register to the
 
+               // destination
 
+               //
 
+               case EQ:        sprintf(result, "%s.Z\t%%%d,%%0", op, opno); break;
 
+               case NE:        sprintf(result, "%s.NZ\t%%%d,%%0", op, opno); break;
 
+               case LT:        sprintf(result, "%s.LT\t%%%d,%%0", op, opno); break;
 
+               case GT:        sprintf(result, "%s.GT\t%%%d,%%0", op, opno); break;
 
+               // .LE doesn't exist on Zip CPU--turn this into two instructions
 
+               case LE:        sprintf(result, "%s.LT\t%%%d,%%0\n\t%s.Z\t%%%d,%%0", op, opno, op, opno); break;
 
+               case GE:        sprintf(result, "%s.GE\t%%%d,%%0", op, opno); break;
 
+               case LTU:       sprintf(result, "%s.C\t%%%d,%%0", op, opno); break;
 
+               //
 
+               // .GTU doesn't exist on the Zip CPU either. We also note that
 
+               // .C will never be set on an equal condition.  Therefore, we
 
+               // turn this into a XOR.NZ 2,CC, which will set the .C condition
 
+               // as long as .Z wasn't true.  We then undo this when we're
 
+               // done.  This is possible since none of these instructions
 
+               // (LDI/MOV/Lod conditional, nor Xor conditional) will ever set
 
+               // the condition codes.
 
+               //
 
+               // This is obviously not very optimal.  Avoid this by all means
 
+               // if you can
 
+               case GTU:       sprintf(result, "XOR.NZ\t2,CC\n%s.C\t%%%d,%%0\n\tXOR.NZ\t2,CC", op, opno); break;
 
+               // .LEU doesn't exist on Zip CPU either--turn this into another
 
+               // two instructions
 
+               case LEU:       sprintf(result, "%s.C\t%%%d,%%0\n\t%s.Z\t%%%d,%%0", op, opno, op, opno); break;
 
+               //
 
+               // .GEU doesn't exist on Zip CPU.  Implementing it her is
 
+               // painful.  We can change the condition codes to make it so,
 
+               // but the instruction requires the condition codes not be
 
+               // changed.  Hence, we must change them back if we do so.
 
+               //
 
+               // .C will be set on less than but not equal.  Hence !.C will
 
+               // be true on greater than or equal.
 
+               case GEU:       sprintf(result, "XOR\t2,CC\n%s.C\t%%%d,%%0\n\tXOR\t2,CC", op, opno); break;
 
+               default:
 
+                       internal_error("MOVSICC(BINARY) Unsupported condition");
 
+                       return NULL;
 
+       } return result;
 
+}
 
+*/
 
+
 
+int
+int
+zip_supported_condition(int c) {
+zip_supported_condition(int c) {
+       switch(c) {
+       switch(c) {
+       case NE: case LT: case EQ: case GT: case GE: case LTU:
+       case EQ: case NE: case LT: case GE: case LTU: case GEU:
+               return 1;
+               return 1;
+               break;
+               break;
+       default:
+       default:
+               break;
+               break;
+       } return 0;
+       } return 0;
+}
+}
+
+
+bool
+bool
+zip_signed_comparison(int c) {
+zip_signed_comparison(int c) {
+       switch(c) {
+       switch(c) {
+       case NE: case LT: case EQ: case GT: case GE:
+       case NE: case LT: case EQ: case GE:
+               return true;
+               return true;
+       default:
+       default:
+               break;
+               break;
+       } return false;
+       } return false;
+}
+}
+
+
+int
+int
+zip_expand_movsicc(rtx dst, rtx condition, rtx iftrue, rtx iffalse) {
+zip_expand_movdi(rtx dst, rtx src) {
+       rtx_insn *insn;
+       ZIPDEBUGFLAG(dbg, false);
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+
+       if (dbg) fprintf(stderr, "ZIP::MOVSICC\n");
+       if (dbg) fprintf(stderr, "\nZIP::MOVDI\n");
+       if (dbg) zip_debug_rtx_pfx("DST", dst);
+       if (dbg) zip_debug_rtx_pfx("DST", dst);
+       if (dbg) zip_debug_rtx_pfx("CND", condition);
+       if (dbg) zip_debug_rtx_pfx("SRC", src);
+       if (dbg) zip_debug_rtx_pfx("TRU", iftrue);
 
+       if (dbg) zip_debug_rtx_pfx("FAL", iffalse);
 
+
+
+       // Start with the condition
+       // MOV !REG->!REG
+       rtx     cmpa = XEXP(condition,0), cmpb=XEXP(condition,1);
+       if ((!REG_P(dst))&&(!REG_P(src))&&(can_create_pseudo_p())) {
+       enum rtx_code   cmpcode = GET_CODE(condition);
+               // This includes:
+
+               //      MOV MEM->MEM
+       // Want to always do the false expression, and only sometimes the
+               //      MOV IMM->MEM
+       // true expression.  If, however, the false is a constant and the
+               if (dbg) fprintf(stderr, "ZIP::MOVDI -- !REG->!REG\n");
+       // true and destination are the same thing, this doesn't work.
+
+       if (rtx_equal_p(dst, iftrue)) {
+               rtx tmp = gen_reg_rtx(DImode);
+               // If the true value is the same as the destination already,
+               emit_insn(gen_movdi(tmp, src));
+               // then swap so we only do the condition on true
+               emit_insn(gen_movdi(dst, tmp));
+               rtx tem = iffalse;
+               return 1;
+               iffalse = iftrue;
 
+               iftrue  = tem;
 
+               cmpcode = reverse_condition(cmpcode);
 
+       }
 
+
 
+       //; Do we need to swap or adjust the condition?
 
+       if (zip_supported_condition((int)cmpcode)) {
 
+               // Keep everything as is
 
+               if (dbg) fprintf(stderr, "ZIP::MOVSICC -- Condition is supported\n");
 
+       } else if ((zip_supported_condition(reverse_condition(cmpcode)))
 
+                       &&(!MEM_P(iffalse))
 
+                       &&(!rtx_equal_p(dst,iffalse))) {
 
+               rtx tem = iffalse;
 
+               iffalse = iftrue;
 
+               iftrue = tem;
 
+
 
+               cmpcode = reverse_condition(cmpcode);
 
+       } else if ((zip_supported_condition((int)swap_condition(cmpcode)))
 
+               &&((REG_P(cmpb))||(can_create_pseudo_p()))) {
 
+               rtx tem = cmpa;
 
+               cmpa = cmpb;
 
+               cmpa = tem;
 
+               cmpcode = swap_condition(cmpcode);
 
+
 
+               if ((GET_CODE(cmpa)==PLUS)&&(zip_signed_comparison((int)cmpcode))
 
+                       &&(REG_P(XEXP(cmpa,0)))
 
+                       &&(CONST_INT_P(XEXP(cmpa,1)))
 
+                       &&(abs(INTVAL(XEXP(cmpa,1)))<(1<<17))) {
 
+
 
+                       // If we were doing CMP x(Rb),Ra
 
+                       // and we just changed it to CMP Ra,x(Rb)
 
+                       // adjust it to CMP -x(Ra),Rb
 
+                       cmpb = plus_constant(SImode, cmpb, -INTVAL(XEXP(cmpa,1)));
 
+                       cmpa = XEXP(cmpa,0);
 
+               } else if (!REG_P(cmpa)) {
 
+                       // Otherwise, if we had anything else in Rb other than
 
+                       // a register ... such as a constant, then load it into
 
+                       // a register before comparing it.  So
 
+                       //      CMP x,Ra
 
+                       // became
 
+                       //      CMP Ra,x
 
+                       // now becomes
 
+                       //      LDI x,Rt
 
+                       //      CMP Ra,Rt
 
+                       // (We already tested for can_create_pseudo_p() above..)
 
+                       tem = gen_reg_rtx(SImode);
 
+                       emit_move_insn(tem, cmpa);
 
+                       cmpa = tem;
 
+               }
 
+       } else {
 
+               // Here's our last chance.
 
+               // This will adjust for less than equal types of stuff
 
+               int     cod = (int)cmpcode;
 
+               zip_canonicalize_comparison(&cod, &cmpa, &cmpb, false);
 
+               cmpcode = (enum rtx_code)cod;
 
+       }
+       }
+
+
+       if (dbg) fprintf(stderr, "ZIP::MOVSICC -- Post-Modes\n");
+       // MOV REG->REG
+       if (dbg) zip_debug_rtx_pfx("DST-P: ", dst);
+       if ((REG_P(dst))&&(REG_P(src))) {
+       if (dbg) zip_debug_rtx_pfx("CND-P: ", condition);
+               if (dbg) fprintf(stderr, "ZIP::MOVDI -- REG->REG\n");
+       if (dbg) zip_debug_rtx_pfx("TRU-P: ", iftrue);
 
+       if (dbg) zip_debug_rtx_pfx("FAL-P: ", iffalse);
 
+
+
+       if (!zip_supported_condition((int)cmpcode)) {
+               emit_insn(gen_movdi_raw(dst, src));
+               if (dbg) {
+               return 1;
+               fprintf(stderr, "ZIP::MOVSICC -- Unsupported condition: ");
 
+                       zip_debug_ccode(cmpcode);
 
+                       fprintf(stderr, "\n");
 
+               }
 
+               return 0;
 
+       }
+       }
+       gcc_assert(zip_supported_condition((int)cmpcode));
 
+
+
+       //; Always do the default move
+       // MOV REG->MEM (a store instruction)
+       bool    conditionally_do_false = false;
+       if ((MEM_P(dst))&&(REG_P(src))) {
+       conditionally_do_false = (MEM_P(iffalse))
+               rtx     addr = XEXP(dst,0);
+               &&(!rtx_equal_p(dst,iffalse))
+               long    offset = 0;
+               &&(zip_supported_condition(reverse_condition(cmpcode)));
+               if ((GET_CODE(addr)==PLUS)&&(CONST_INT_P(XEXP(addr,1))))
+       conditionally_do_false = conditionally_do_false || (rtx_equal_p(dst,iftrue));
+                       offset = INTVAL(XEXP(addr,1));
+       if ((conditionally_do_false)&&(!zip_supported_condition(reverse_condition(cmpcode)))) {
+
+               if (dbg) {
+               if (dbg) fprintf(stderr, "ZIP::MOVDI -- REG->MEM\n");
+                       fprintf(stderr, "ZIP::MOVSICC -- Cant support the reverse condition: ");
+               if (REG_P(addr)) {
+                       zip_debug_ccode(cmpcode);
+                       emit_insn(gen_movdi_raw(dst, src));
+                       fprintf(stderr, "\n");
+                       return 1;
 
+               } else if ((GET_CODE(addr)==PLUS)
 
+                       &&(REG_P(XEXP(addr,0)))
 
+                       &&(CONST_INT_P(XEXP(addr,1)))
 
+                       &&(offset>=(long)zip_min_anchor_offset)
 
+                       &&(offset+4<(long)zip_max_anchor_offset)) {
 
+                       // Demonstrated and works
 
+                       emit_insn(gen_movdi_raw(dst, src));
 
+                       return 1;
 
+               } else if (can_create_pseudo_p()) {
 
+                       rtx tmp = gen_reg_rtx(Pmode);
 
+                       emit_insn(gen_movsi(tmp, addr));
 
+                       emit_insn(gen_movdi_raw(gen_rtx_MEM(DImode, tmp), src));
 
+                       return 1;
+               }
+               }
+               return 0;
 
+       }
+       }
+
+
+       if ((!rtx_equal_p(dst, iffalse))&&(!conditionally_do_false)) {
+       // MOV MEM->REG (a load instruction)
+               if (dbg)
+       if ((REG_P(dst))&&(MEM_P(src))) {
+               fprintf(stderr, "ZIP::MOVSICC -- EMITTING MOVE FALSE->DST\n");
+               rtx addr = XEXP(src,0);
+               insn = emit_move_insn(dst, iffalse);
+               long    offset = 0;
+               if (dbg) zip_debug_rtx_pfx("BARE-U: ", insn);
+               if ((GET_CODE(addr)==PLUS)&&(CONST_INT_P(XEXP(addr,1))))
+       }
+                       offset = INTVAL(XEXP(addr,1));
+
+
+       rtx     cc_rtx = gen_rtx_REG(CCmode, zip_CC);
+               if (dbg) fprintf(stderr, "ZIP::MOVDI -- MEM->REG\n");
+
+               if (REG_P(addr)) {
+       //; Now let's get our comparison right
+                       if (dbg) fprintf(stderr, "ZIP::MOVDI -- MEM[R]->REG\n");
+       if (dbg) fprintf(stderr, "ZIP::MOVSICC -- EMITTING COMPARISON\n");
+                       emit_insn(gen_movdi_raw(dst, src));
+       insn = emit_insn(gen_rtx_SET(VOIDmode, cc_rtx,
+                       return 1;
+               gen_rtx_COMPARE(CCmode, cmpa, cmpb)));
+               } else if ((GET_CODE(addr)==PLUS)
+       if (dbg) zip_debug_rtx_pfx("BARE-C: ", insn);
+                       &&(REG_P(XEXP(addr,0)))
+
+                       &&(CONST_INT_P(XEXP(addr,1)))
+       //; Finally, let's load the value on true
+                       &&(offset>=(long)zip_min_anchor_offset)
+       if (!rtx_equal_p(dst, iftrue)) {
+                       &&(offset+4<(long)zip_max_anchor_offset)) {
+               if (dbg) fprintf(stderr, "ZIP::MOVSICC -- EMITTING BARE\n");
+                       if (dbg) fprintf(stderr, "ZIP::MOVDI -- MEM[#+R]->REG -- DONE\n");
+               insn=emit_insn(gen_movsicc_bare(dst,
+                       emit_insn(gen_movdi_raw(dst, src));
+                       gen_rtx_fmt_ee(cmpcode, SImode, NULL_RTX, NULL_RTX),
+                       return 1;
+                       iftrue, dst));
+               } else if (can_create_pseudo_p()) {
+               if (dbg) zip_debug_rtx_pfx("BARE-T: ", insn);
+                       if (dbg) fprintf(stderr, "ZIP::MOVDI -- LDI #,R, MEM[R]->REG\n");
+       }
+                       rtx tmp = gen_reg_rtx(Pmode);
+
+                       emit_insn(gen_movsi(tmp, addr));
+       if (conditionally_do_false) {
+                       emit_insn(gen_movdi_raw(dst,
+               gcc_assert(zip_supported_condition(reverse_condition(cmpcode)));
+                               gen_rtx_MEM(DImode, tmp)));
+               insn=emit_insn(gen_movsicc_bare(dst,
+                       return 1;
+                       gen_rtx_fmt_ee(reverse_condition(cmpcode), SImode,
+               } else if (dbg)
+                       NULL_RTX, NULL_RTX), iffalse, dst));
+                       fprintf(stderr, "ZIP::MOVDI -- MEM[?]->REG (no match)\n");
+               if (dbg) zip_debug_rtx_pfx("BARE-F: ", insn);
 
+       }
+       }
+
+
+       // Return true on success
+       // MOV #->REG (An LDI instruction, but for DIwords)
 
+       if ((CONST_INT_P(src))&&(REG_P(dst))) {
 
+               if (dbg) fprintf(stderr, "ZIP::MOVDI -- IMM->REG\n");
 
+               emit_insn(gen_movdi_raw(dst, src));
+       return 1;
+       return 1;
+}
+}
+
+
+const char *zip_addsicc(rtx dst, rtx condition, rtx ifsrc, rtx addv ATTRIBUTE_UNUSED) {
+       return 0;
 
+}
 
+
 
+const char *
 
+zip_addsicc(rtx dst, rtx condition, rtx ifsrc, rtx addv) {
+       // We know upon entry that REG_P(dst) must be true
+       // We know upon entry that REG_P(dst) must be true
+       if (!REG_P(dst))
+       if (!REG_P(dst))
+               internal_error("%s","ADDSICC into something other than register");
+               internal_error("%s","ADDSICC into something other than register");
 
+
 
+       if ((REG_P(dst))&&(REG_P(ifsrc))&&(REG_P(addv))
 
+               &&(REGNO(dst)!=REGNO(ifsrc))) {
 
+               switch (GET_CODE(condition)) {
 
+               case EQ: return "MOV.Z\t%2,%0\n\tADD.Z\t%3,%0";
 
+               case NE: return "MOV.NZ\t%2,%0\n\tADD.NZ\t%3,%0";
 
+               case LT: return "MOV.LT\t%2,%0\n\tADD.LT\t%3,%0";
 
+
 
+               case LE: return "MOV.LT\t%3,%0\n\tMOV.Z\t%3,%0\n\tADD.LT\t%3,%0\n\tADD.Z\t%3,%0";
 
+               case GE: return "MOV.GE\t%2,%0\n\tADD.GE\t%3,%0";
 
+
 
+               case GT: return "BLT\t%.Laddsi%=\n\tBZ\t%%.Laddsi%=\n\tMOV\t%2,%0\n\tADD\t%3,%0\n.Laddsi%=:";
 
+               case LTU: return "MOV.C\t%2,%0\n\tADD.C\t%3,%0";
 
+
 
+               case LEU: return "MOV.C\t%2,%0\n\tMOV.Z\t%2,%0\n\tADD.C\t%3,%0\n\tADD.Z\t%3,%0";
 
+               case GEU: return "MOV.NC\t%2,%0\n\tADD.NC\t%3,%0";
 
+               case GTU: return "BZ\t%.Laddsi%=\n\tMOV.NC\t%3,%0\n\tADD.NC\t%3,%0\n.Laddsi%=:";
 
+               default:
 
+                       internal_error("%s", "Zip/No usable addsi expansion");
 
+                       break;
 
+               }
 
+       }
 
+
+       if ((REG_P(ifsrc))&&(REGNO(dst)==REGNO(ifsrc))) {
+       if ((REG_P(ifsrc))&&(REGNO(dst)==REGNO(ifsrc))) {
+               switch (GET_CODE(condition)) {
+               switch (GET_CODE(condition)) {
+               case EQ: return "ADD.Z\t%3,%0";
+               case EQ: return "ADD.Z\t%3,%0";
+               case NE: return "ADD.NZ\t%3,%0";
+               case NE: return "ADD.NZ\t%3,%0";
+               case LT: return "ADD.LT\t%3,%0";
+               case LT: return "ADD.LT\t%3,%0";
+               case GT: return "ADD.GT\t%3,%0";
 
+               case LE: return "ADD.LT\t%3,%0\n\tADD.Z\t%3,%0";
+               case LE: return "ADD.LT\t%3,%0\n\tADD.Z\t%3,%0";
+               case GE: return "ADD.GE\t%3,%0";
+               case GE: return "ADD.GE\t%3,%0";
 
+               case GT: return "ADD.GE\t%3,%0\n\tSUB.Z\t%3,%0";
+               case LTU: return "ADD.C\t%3,%0";
+               case LTU: return "ADD.C\t%3,%0";
+               case LEU: return "ADD.C\t%3,%0\n\tADD.Z\t%3,%0";
+               case LEU: return "ADD.C\t%3,%0\n\tADD.Z\t%3,%0";
+               case GEU: return "XOR\t2,CC\n\tADD.C\t%3,%0\n\tXOR\t2,CC";
+               case GEU: return "ADD.NC\t%3,%0";
+               // Can do a GEU comparison, and then undo on the Zero condition
+               case GTU: return "SUB.Z\t%3,%0\n\tADD.NC\t%3,%0";
+               case GTU: return "XOR\t2,CC\n\tADD.C\t%3,%0\n\tSUB.Z\t%3,%0\n\tXOR\t2,CC";
 
+               default:
+               default:
+                       internal_error("%s", "Zip/No usable addsi expansion");
+                       internal_error("%s", "Zip/No usable addsi expansion");
+                       break;
+                       break;
+               }
+               }
+       } else {
+       } else {
+               // MOV A+REG,REG
+               // MOV A+REG,REG
+               switch (GET_CODE(condition)) {
+               switch (GET_CODE(condition)) {
+               case EQ: return "MOV.Z\t%3+%2,%0";
+               case EQ: return "MOV.Z\t%3+%2,%0";
+               case NE: return "MOV.NZ\t%3+%2,%0";
+               case NE: return "MOV.NZ\t%3+%2,%0";
+               case LT: return "MOV.LT\t%3+%2,%0";
+               case LT: return "MOV.LT\t%3+%2,%0";
+               case GT: return "MOV.GT\t%3+%2,%0";
+               case GT: return "BLT\t.Laddcc%=\n\tBZ\t.Laddcc%=\n\tMOV\t%3+%2,%0\n.Laddcc%=";
+               case LE: return "MOV.LT\t%3+%2,%0\n\tMOV.Z\t%3+%2,%0";
+               case LE: return "MOV.LT\t%3+%2,%0\n\tMOV.Z\t%3+%2,%0";
+               case GE: return "MOV.GE\t%3+%2,%0";
+               case GE: return "MOV.GE\t%3+%2,%0";
+               case LTU: return "MOV.C\t%3+%2,%0";
+               case LTU: return "MOV.C\t%3+%2,%0";
+               case LEU: return "MOV.C\t%3+%2,%0\n\tMOV.Z\t%3+%2,%0";
+               case LEU: return "MOV.C\t%3+%2,%0\n\tMOV.Z\t%3+%2,%0";
+               case GEU: return "XOR\t2,CC\n\tMOV.C\t%3+%2,%0\n\tXOR\t2,CC";
+               case GEU: return "MOV.NC\t%3+%2,%0";
+               // Can do a GEU comparison, and then undo on the Zero condition
+               case GTU: return "BZ\t.Laddcc%=\n\tMOV.NC\t%3+%2,%0\n\t.Laddcc%=:";
+               // EXCEPT: with a move instruction, what's there to undo?  We
 
+               // just clobbered our register!
 
+               // case GTU: return "XOR\t2,CC\n\tMOV.C\t%3,%0\n\tSUB.Z\t%3,%0XOR\t2,CC";
 
+               default:
+               default:
+                       internal_error("%s", "Zip/No usable addsi(reg,reg) expansion");
+                       internal_error("%s", "Zip/No usable addsi(reg,reg) expansion");
+                       break;
+                       break;
+               }
+               }
+       }
+       }
Line 2897... Line 3097...
+
+
+rtx_insn       *zip_ifcvt_info;
+rtx_insn       *zip_ifcvt_info;
+
+
+void
+void
+zip_ifcvt_modify_tests(ce_if_block *ce_info ATTRIBUTE_UNUSED, rtx *true_expr, rtx *false_expr) {
+zip_ifcvt_modify_tests(ce_if_block *ce_info ATTRIBUTE_UNUSED, rtx *true_expr, rtx *false_expr) {
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+       const bool      dbg = ((ZIP_ALL_DEBUG_ON)||(false))&&(!ZIP_ALL_DEBUG_OFF);
+       if (dbg) fprintf(stderr, "IFCVT-MODIFY-TESTS\n");
+       if (dbg) fprintf(stderr, "IFCVT-MODIFY-TESTS\n");
+       if (*true_expr) switch(GET_CODE(*true_expr)) {
+       if (*true_expr) switch(GET_CODE(*true_expr)) {
 
+               // These are our unsupported conditions
+               case LE:
+               case LE:
+               case GTU:
+               case GT:
+               case GEU:
 
+               case LEU:
+               case LEU:
 
+               case GTU:
+                       if (dbg) fprintf(stderr, "TRUE, missing expr\n");
+                       if (dbg) fprintf(stderr, "TRUE, missing expr\n");
+                       if (dbg) zip_debug_rtx(*true_expr);
+                       if (dbg) zip_debug_rtx(*true_expr);
+                       *true_expr = NULL_RTX;
+                       *true_expr = NULL_RTX;
+                       break;
+                       break;
+               default: // LT, GT, GTE, LTU, NE, EQ
+               default: // LT, GT, GTE, LTU, NE, EQ
+                       break;
+                       break;
+       }
+       }
+
+
+       if (*false_expr) switch(GET_CODE(*false_expr)) {
+       if (*false_expr) switch(GET_CODE(*false_expr)) {
+               case LE:
+               case LE:
+               case GTU:
+               case GT:
+               case GEU:
 
+               case LEU:
+               case LEU:
 
+               case GTU:
+                       if (dbg) fprintf(stderr, "FALSE, missing expr\n");
+                       if (dbg) fprintf(stderr, "FALSE, missing expr\n");
+                       if (dbg) zip_debug_rtx(*false_expr);
+                       if (dbg) zip_debug_rtx(*false_expr);
+                       *false_expr = NULL_RTX;
+                       *false_expr = NULL_RTX;
+               default:
+               default:
+                       break;
+                       break;
Line 2996... Line 3197...
+
+
+int    zip_insn_sets_cc(rtx_insn *insn) {
+int    zip_insn_sets_cc(rtx_insn *insn) {
+       return (get_attr_ccresult(insn)==CCRESULT_SET);
+       return (get_attr_ccresult(insn)==CCRESULT_SET);
+}
+}
+
+
+int    zip_is_conditional(rtx_insn *insn) {
+const char *
+       return (get_attr_conditional(insn)==CONDITIONAL_YES);
+zip_cbranchdi_const(rtx comparison,
 
+               rtx a ATTRIBUTE_UNUSED,
 
+               rtx b,
 
+               rtx label ATTRIBUTE_UNUSED) {
 
+       gcc_assert(CONST_INT_P(b));
 
+       long value = INTVAL(b);
 
+
 
+       // Look into the combine routines to find out why this routine never
 
+       // gets called.
 
+
 
+       switch(GET_CODE(comparison)) {
 
+       case EQ:
 
+               if (value < 0)
 
+                 return "CMP\t-1,%H1\t; cbranchdi/# EQ (neg)\n\tCMP.Z\t%2,%L1\n\tBZ\t%3";
 
+               else
 
+                 return "CMP\t0,%H1\t; cbranchdi/# EQ\n\tCMP.Z\t%2,%L1\n\tBZ\t%3";
 
+       case NE:
 
+               if (value < 0)
 
+                 return "CMP\t-1,%H1\t; cbranchdi/# NE (neg)\n\tCMP.Z\t%2,%L1\n\tBNZ\t%3";
 
+               else
 
+                 return "CMP\t0,%H1\t; cbranchdi/# NE\n\tCMP.Z\t%2,%L1\n\tBNZ\t%3";
 
+       case LE:
 
+               if (value == 0)
 
+                       return "CMP\t0,%H1\t; cbranchdi/# LE 0\n\tBLT\t%3\n\tCMP.Z\t0,%L1\n\tBZ\t%3";
 
+               else if (value == -1)
 
+                       return "CMP\t0,%H1\t; cbranchdi/# LE -1\n\tBLT\t%3";
 
+               else if (value < 0) {
 
+                       char    tmp[128];
 
+                       sprintf(tmp, "CMP\t-1,%%H1\t; cbranchdi/# LE (neg)\n"
 
+                               "\tBLT\t.Lcmpdile%%=\n"
 
+                               "\tBNZ\t%%3\n"
 
+                               "\tCMP\t%ld,%%L1\n"
 
+                               "\tBC\t%%3", (value+1l)&0x0ffffffff);
 
+                       return ggc_alloc_string(tmp, -1);
 
+               } else { //; value > 0
 
+                       char    tmp[128];
 
+                       sprintf(tmp, "CMP\t0,%%H1\t; cbranchdi/# LE\n"
 
+                               "\tBLT\t%%3\n"
 
+                               "\tBNZ\t.Lcmple%%=\n"
 
+                               "\tCMP\t%ld,%%L1\n"
 
+                               "\tBC\t%%3\n"
 
+                               ".Lcmple%%=:", value-1);
 
+                       return ggc_alloc_string(tmp, -1);
 
+               }
 
+       case LT:
 
+               if (value == 0)
 
+                       return "CMP\t0,%H1\t; cbranchdi/# LT 0\n\tBLT\t%3";
 
+               else if (value < 0)
 
+                       return "CMP\t-1,%H1\t; cbranchdi/# LT neg\n\tCMP.Z\t%2,%L1\n\tBC\t%3";
 
+               else
 
+                       return "CMP\t0,%H1\t; cbranchdi/# LT\n"
 
+                               "\tBLT\t%3\n"
 
+                               "\tBNZ\t.Lcmplt%=\n"
 
+                               "\tCMP\t%2,%L1\n"
 
+                               "\tBC\t%3\n"
 
+                               ".Lcmplt%=:";
 
+       case GT:
 
+               if (value == 0)
 
+                       return "CMP\t1,%H1\t; cbranchdi/# GT 0\n"
 
+                               "\tBGE\t%3\n"
 
+                               "\tBNZ\t.Lcmpgt%=\n"
 
+                               "\tCMP\t0,%L1\n"
 
+                               "\tBNZ\t%3\n"
 
+                               ".Lcmpgt%=:";
 
+               else if (value == -1)
 
+                       return "CMP\t0,%H1\t; cbranchdi/# GT -1\n"
 
+                               "\tBGE\t%3\n";
 
+               else if (value < 0) {
 
+                       char    tmp[128];
 
+                       sprintf(tmp, "CMP\t-1,%%H1\t; cbranchdi/# GT neg\n"
 
+                               "\tBLT\t.Lcmpgt%%=\n"
 
+                               "\tBNZ\t%%3\n"
 
+                               "\tCMP\t%ld,%%H3\n"
 
+                               "\tBNC\t%%3\n"
 
+                               ".Lcmpgt%%=:", value+1l);
 
+                       return ggc_alloc_string(tmp, -1);
 
+               } else {
 
+                       char    tmp[128];
 
+                       sprintf(tmp, "CMP\t0,%%H1\t; cbranchdi/# GT\n"
 
+                               "\tBLT\t.Lcmpgt%%=\n"
 
+                               "\tBNZ\t%%3\n"
 
+                               "\tCMP\t%ld,%%L1\n"
 
+                               "\tBNC\t%%3\n"
 
+                               ".Lcmpgt%%=:", value+1l);
 
+                       return ggc_alloc_string(tmp, -1);
 
+               }
 
+       case GE:
 
+               if (value == 0)
 
+                       return "CMP\t0,%H1\t; cbranchdi/# GE 0\n"
 
+                               "\tBLT\t.Lcmpge%=\n"
 
+                               "\tBNZ\t%3\n"
 
+                               "\tCMP\t0,%L1\n"
 
+                               "\tBNC\t%3\n"
 
+                               ".Lcmpge%=:";
 
+               else if (value == -1)
 
+                       return "CMP\t-1,%H1\t; cbranchdi/# GE -1\n"
 
+                               "\tBLT\t.Lcmpge%=\n"
 
+                               "\tBNZ\t%3\n"
 
+                               "\tCMP\t-1,%L1\n"
 
+                               "\tBZ\t%3\n"
 
+                               ".Lcmpge%=:";
 
+               else if (value < 0)
 
+                       return "CMP\t-1,%H1\t; cbranchdi/# GE <\n"
 
+                               "\tBLT\t.Lcmpge%=\n"
 
+                               "\tBNZ\t%3\n"
 
+                               "\tCMP\t%2,%L1\n"
 
+                               "\tBNC\t%3\n"
 
+                               ".Lcmpge%=:";
 
+               else
 
+                       return "CMP\t0,%H1\t; cbranchdi/# GE\n"
 
+                               "\tBLT\t.Lcmpge%=\n"
 
+                               "\tBNZ\t%3\n"
 
+                               "\tCMP\t%2,%L1\n"
 
+                               "\tBNC\t%3\n"
 
+                               ".Lcmpge%=:";
 
+       case LTU:
 
+               if (value == 0) { //; Impossible, cannot be < 0 unsignd
 
+                       return "; cbranchdi/# LTU 0 (Impossible!)";
 
+               } else
 
+                       return "CMP\t0,%H1\t; cbranchdi/#\n\tCMP.Z\t%2,%L1\n\tBC\t%3\n";
 
+       case LEU:
 
+               if (value == 0) { //; Only possible if == 0
 
+                       return "CMP\t0,%%H0\t; cbranchdi/# LEU 0\n"
 
+                               "\tCMP.Z\t0,%%L0\n"
 
+                               "\tBZ\t%3";
 
+               } else {
 
+                       //; Subtract one, and LTU works
 
+                       char    tmp[128];
 
+                       sprintf(tmp, "CMP\t0,%%H1\t; cbranchdi/# LEU\n"
 
+                               "\tCMP.Z\t%ld,%%L1\n"
 
+                               "\tBC\t%%3\n", value-1);
 
+                       return ggc_alloc_string(tmp, -1);
 
+               }
 
+       case GTU:
 
+               if (value == 0) {
 
+                       //; Equivalent to not equal to zero
 
+                       return "CMP\t0,%H1\t; cbranchdi/# GTU 0\n\tCMP.Z\t0,%L1\n\tBNZ\t%3";
 
+               } else {
 
+                       char    tmp[128];
 
+                       sprintf(tmp,
 
+                               "CMP\t0,%%H1\t; cbranchdi/# GTU\n"
 
+                               "\tBNZ\t%%3\n"
 
+                               "\tCMP\t%ld,%%L1\n"
 
+                               "\tBNC\t%%3\n", value+1);
 
+                       return ggc_alloc_string(tmp, -1);
 
+               }
 
+       case GEU:
 
+               if (value == 0) //; Unsigned, always true
 
+                       return "BRA\t%3\t; cbranchdi/# GEU 0";
 
+               else
 
+                       return "CMP\t0,%H1\t; cbranchdi/# GEU\n"
 
+                               "\tBNZ\t%3\n"
 
+                               "\tCMP\t%2,%L1\n"
 
+                               "\tBNC\t%3";
 
+       default:
 
+               gcc_unreachable();
 
+       }
 
+}
 
+
 
+const char *
 
+zip_cbranchdi_reg(rtx comparison,
 
+               rtx a ATTRIBUTE_UNUSED,
 
+               rtx b ATTRIBUTE_UNUSED,
 
+               rtx label ATTRIBUTE_UNUSED) {
 
+
 
+       switch(GET_CODE(comparison)) {
 
+               case EQ:
 
+                       return "CMP\t%H2,%H1\t; cbranchdi/r EQ\n\tCMP.Z\t%L2,%L1\n\tBZ\t%3";
 
+               case NE:
 
+                       return "CMP\t%H2,%H1\t; cbranchdi/r NE\n\tCMP.Z\t%L2,%L1\n\tBNZ\t%3";
 
+               case LE:
 
+                       return "CMP\t%H2,%H1\t; cbranchdi/r LE\n"
 
+                               "\tBLT\t%3\n"
 
+                               "\tBNZ\t.Ldi%=\n"
 
+                               "\tCMP\t%L1,%L2\n"
 
+                               "\tBNC\t%3\n"
 
+                               ".Ldi%=:";
 
+               case GT:
 
+                       return "CMP\t%H1,%H2\t; cbranchdi/r GT\n"
 
+                               "\tBLT\t%3\n"
 
+                               "\tBNZ\t.Ldi%=\n"
 
+                               "\tCMP\t%L1,%L2\n"
 
+                               "\tBC\t%3\n"
 
+                               ".Ldi%=:";
 
+               case LT:
 
+                       return "CMP\t%H2,%H1\t; cbranchdi/r LT\n"
 
+                               "\tBLT\t%3\n"
 
+                               "\tBNZ\t.Ldi%=\n"
 
+                               "\tCMP\t%L2,%L1\n"
 
+                               "\tBC\t%3\n"
 
+                               ".Ldi%=:";
 
+               case GE:
 
+                       return "CMP\t%H1,%H2\t; cbranchdi/r GE\n"
 
+                               "\tBLT\t%3\n"
 
+                               "\tBNZ\t.Ldi%=\n"
 
+                               "\tCMP\t%L2,%L1\n"
 
+                               "\tBNC\t%3\n"
 
+                               ".Ldi%=:";
 
+               case LTU:
 
+                       return "CMP\t%H2,%H1\t; cbranchdi/r LTU\n"
 
+                               "\tCMP.Z\t%L2,%L1\n"
 
+                               "\tBC\t%3\n";
 
+               case LEU:
 
+                       return "CMP\t%H1,%H2\t; cbranchdi/r LEU\n"
 
+                               "\tBC\t.Ldi%=\n"        //; H1 > H2, skip
 
+                               "\tCMP.Z\t%L1,%L2\n"    //; (H1==H2) test L1-L2
 
+                               "\tBNC\t%3\n"           //; If (L1>=L2)||(H1>H2)
 
+                               ".Ldi%=:";
 
+               case GTU:
 
+                       return "CMP\t%H1,%H2\t; cbranchdi/r GTU\n"
 
+                               "\tCMP.Z\t%L1,%L2\n"
 
+                               "\tBC\t%3";
 
+               case GEU:
 
+                       return "CMP\t%H2,%H1\t; cbranchdi/r GEU\n"
 
+                               "\tBC\t.Ldi%=\n"
 
+                               "\tCMP.Z\t%L2,%L1\n"
 
+                               "\tBNC\t%3\n"
 
+                               ".Ldi%=:";
 
+               default:
 
+                       gcc_unreachable();
 
+       }
 
+}
 
+
 
+const char *
 
+zip_cbranchdi(rtx comparison, rtx a, rtx b, rtx label) {
 
+       if (REG_P(b))
 
+               return zip_cbranchdi_reg(comparison, a, b, label);
 
+       else
 
+               return zip_cbranchdi_const(comparison, a, b, label);
+}
+}
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-float.md gcc-5.3.0-zip/gcc/config/zip/zip-float.md
+
--- gcc-5.3.0-original/gcc/config/zip/zip-float.md      1969-12-31 19:00:00.000000000 -0500
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zipdbg.h gcc-6.2.0-zip/gcc/config/zip/zipdbg.h
+++ gcc-5.3.0-zip/gcc/config/zip/zip-float.md   2016-11-10 10:17:53.248750791 -0500
--- gcc-6.2.0/gcc/config/zip/zipdbg.h   1969-12-31 19:00:00.000000000 -0500
@@ -0,0 +1,138 @@
+++ gcc-6.2.0-zip/gcc/config/zip/zipdbg.h       2017-02-17 16:47:25.727651898 -0500
 
@@ -0,0 +1,8 @@
 
+#define        DO_ZIP_DEBUGS
 
+#ifdef DO_ZIP_DEBUGS
 
+#include <stdio.h>
 
+#define        ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
 
+extern void    zip_debug_rtx(const_rtx);
 
+#else
 
+#define        ZIP_DEBUG_LINE(STR,RTX)
 
+#endif
 
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip-di.md gcc-6.2.0-zip/gcc/config/zip/zip-di.md
 
--- gcc-6.2.0/gcc/config/zip/zip-di.md  1969-12-31 19:00:00.000000000 -0500
 
+++ gcc-6.2.0-zip/gcc/config/zip/zip-di.md      2017-02-22 15:56:17.195319460 -0500
 
@@ -0,0 +1,528 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;;
+;; Filename:   zip-float.md
+;; Filename:   zip-di.md
+;;
+;;
+;; Project:    Zip CPU -- a small, lightweight, RISC CPU soft core
+;; Project:    Zip CPU -- a small, lightweight, RISC CPU soft core
+;;
+;;
+;; Purpose:    This is the machine description of the ZipCPU floating point
+;; Purpose:    This is the machine description of the Zip CPU as needed by the
+;;             unit (if installed).
+;;             GNU compiler collection (GCC).  Specifically, this is the
 
+;;     section of the description associated with 64-bit values and
 
+;;     arithmetic.
+;;
+;;
+;;
+;;
+;; Creator:    Dan Gisselquist, Ph.D.
+;; Creator:    Dan Gisselquist, Ph.D.
+;;             Gisselquist Technology, LLC
+;;             Gisselquist Technology, LLC
+;;
+;;
Line 3040... Line 3484...
+;;
+;;
+;;
+;;
+;
+;
+;
+;
+;
+;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+(define_expand "movdi"
+;;
+       [(set (match_operand:DI 0 "nonimmediate_operand" "")
+;; Floating point Op-codes
+               (match_operand:DI 1 "general_operand" ""))]
+;;
+       "(ZIP_HAS_DI)"
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+       {
 
+               if (zip_expand_movdi(operands[0], operands[1]))
 
+                       DONE;
 
+               FAIL;
 
+       }
 
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
+;
+;
+;
+;
+;
+;
+(define_insn "addsf3"
+(define_insn "movdi_raw"
+       [(set (match_operand:SF 0 "register_operand" "=r")
+       [(set (match_operand:DI 0 "nonimmediate_operand" "=r,Q,r,r")
+               (plus:SF (match_operand:SF 1 "register_operand" "0")
+               (match_operand:DI 1 "general_operand" "r,r,Q,i"))]
+                       (match_operand:SF 2 "register_operand" "r")))
+       "(ZIP_HAS_DI)"
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
 
+       "(ZIP_FPU)"
 
+       "FPADD  %2,%0"
 
+       [(set_attr "ccresult" "unknown")])
 
+(define_insn "subsf3"
 
+       [(set (match_operand:SF 0 "register_operand" "=r")
 
+               (minus:SF (match_operand:SF 1 "register_operand" "0")
 
+                       (match_operand:SF 2 "register_operand" "r")))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
 
+       "(ZIP_FPU)"
 
+       "FPSUB  %2,%0"
 
+       [(set_attr "ccresult" "unknown")])
 
+(define_insn "mulsf3"
 
+       [(set (match_operand:SF 0 "register_operand" "=r")
 
+               (mult:SF (match_operand:SF 1 "register_operand" "0")
 
+                       (match_operand:SF 2 "register_operand" "r")))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
 
+       "(ZIP_FPU)"
 
+       "FPMUL  %2,%0"
 
+       [(set_attr "ccresult" "unknown")])
 
+(define_insn "divsf3"
 
+       [(set (match_operand:SF 0 "register_operand" "=r")
 
+               (div:SF (match_operand:SF 1 "register_operand" "0")
 
+                       (match_operand:SF 2 "register_operand" "r")))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
 
+       "(ZIP_FPU)"
 
+       "FPDIV  %2,%0"
 
+       [(set_attr "ccresult" "unknown")])
 
+; (define_insn "floatsisf2"
 
+;      [(set (match_operand:SF 0 "register_operand" "=r"
 
+;              (float:SI (match_operand:SF 1 "register_operand" "r"))))
 
+;      (set (reg:CC CC_REG) (compare:CC (match_dup 1) (const_int 0)))]
 
+;      "(ZIP_FPU)"
 
+;      "FPI2F  %1,%0")
 
+; (define_insn "floatunssisf2" ... ?)
 
+; (define_insn "fix_truncsfsi2"
 
+;      [(set (match_operand:SI 0 "register_operand" "=r"
 
+;              (float:SF (match_operand:SF 1 "register_operand" "r"))))
 
+;      (set (reg:CC CC_REG) (compare:CC (match_dup 1) (const_int 0)))]
 
+;      "(ZIP_FPU)"
 
+;      "FPI2F  %1,%0")
 
+; (define_insn "nearbyintsf2" ... ?)
 
+; (define_insn "truncsfsi2" ... ?)
 
+(define_expand "negsf2"
 
+       [(set (match_operand:SF 0 "register_operand" "=r")
 
+               (neg:SF (match_operand:SF 1 "register_operand" "0")))
 
+       ]
 
+       ""
 
+       {
+       {
+               operands[0] = gen_rtx_SUBREG(SImode, operands[0], 0);
+               if ((REG_P(operands[0]))&&(REG_P(operands[1])))
+               if (can_create_pseudo_p()) {
+                       return  "MOV %H1,%H0\t; MOV:DI\n\tMOV %L1,%L0";
+                       rtx tmp = gen_reg_rtx(SImode);
+               else if (MEM_P(operands[0]))    //; StoreDI
+                       emit_insn(gen_movsi_ldi(tmp,gen_int_mode(0x80000000,SImode)));
+                       return  "SW %H1,%0\t; Store:DI\n\tSW %L1,4+%0";
+                       emit_insn(gen_xorsi3(operands[0], operands[0], tmp));
+               else if (MEM_P(operands[1]))    //; LoadDI
+                       DONE;
+                       return  "LW %1,%H0\t; Load:DI\n\tLW 4+%1,%L0";
+               } else {
+               else if (CONST_INT_P(operands[1])) {
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
+                       char    tmp[128];
+                       emit_insn(gen_iorsi3(operands[0], operands[0],
+                       HOST_WIDE_INT   v = INTVAL(operands[1]);
+                               gen_int_mode(1,SImode)));
+                       sprintf(tmp, "LDI\t0x%08x,%%H0\t; LDI #:DI,%%H0\n\tLDI\t0x%08x,%%L0",
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
+                               (unsigned)(v>>32),
+                       DONE;
+                               (unsigned)(v));
 
+                       return ggc_alloc_string(tmp, -1);
 
+               } else
 
+                       gcc_unreachable();
+               }
+               }
+       })
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
+(define_expand "abssf2"
+;
+       [(set (match_operand:SF 0 "register_operand" "=r")
+;
+               (abs:SF (match_operand:SF 1 "register_operand" "0")))
+;
 
+; ADD
 
+;
 
+;
 
+(define_insn "adddi3" ; Fastest/best instruction always goes first
 
+       [(set (match_operand:DI 0 "register_operand" "=r")
 
+               (plus:DI (match_operand:DI 1 "register_operand" "0")
 
+                       (match_operand:DI 2 "register_operand" "r")))
 
+       (clobber (reg:CC CC_REG))
+       ]
+       ]
+       ""
+       "(ZIP_HAS_DI)"
+       {
+       "ADD    %L2,%L0\n\tADD.C\t1,%H0\n\tADD\t%H2,%H0"
+               operands[0] = gen_rtx_SUBREG(SImode, operands[0], 0);
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+               if (can_create_pseudo_p()) {
 
+                       rtx tmp = gen_reg_rtx(SImode);
 
+                       emit_insn(gen_movsi_ldi(tmp,gen_int_mode(0x7fffffff,SImode)));
 
+                       emit_insn(gen_andsi3(operands[0], operands[0], tmp));
 
+                       DONE;
 
+               } else {
 
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
 
+                       emit_insn(gen_andsi3(operands[0], operands[0],
 
+                               gen_int_mode(-2,SImode)));
 
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
 
+                       DONE;
 
+               }
 
+       })
 
+;
+;
+;
+;
+; STILL MISSING:
 
+;
+;
 
+; SUB
+;
+;
+;
+;
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.h gcc-5.3.0-zip/gcc/config/zip/zip.h
+(define_insn "subdi3"
--- gcc-5.3.0-original/gcc/config/zip/zip.h     1969-12-31 19:00:00.000000000 -0500
+       [(set (match_operand:DI 0 "register_operand" "=r")
+++ gcc-5.3.0-zip/gcc/config/zip/zip.h  2016-11-19 08:26:58.092386679 -0500
+               (minus:DI (match_operand:DI 1 "register_operand" "0")
@@ -0,0 +1,4096 @@
+                       (match_operand:DI 2 "register_operand" "r")))
+////////////////////////////////////////////////////////////////////////////////
+       (clobber (reg:CC CC_REG))
+//
+       ]
+// Filename:   gcc/config/zip/zip.h
+       "(ZIP_HAS_DI)"
+//
+       "SUB    %L2,%L0\n\tSUB.C\t1,%H0\n\tSUB\t%H2,%H0"
+// Project:    Zip CPU backend for the GNU Compiler Collection
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+//
+;
+// Purpose:
+;
+//
+;
+// Creator:    Dan Gisselquist, Ph.D.
+; AND
+//             Gisselquist Technology, LLC
+;
+//
+;
+////////////////////////////////////////////////////////////////////////////////
+(define_insn "anddi3"
+//
+       [(set (match_operand:DI 0 "register_operand" "=r")
+// Copyright (C) 2016, Gisselquist Technology, LLC
+               (and:DI (match_operand:DI 1 "register_operand" "%0")
+//
+                       (match_operand:DI 2 "register_operand" "r")))
+// This program is free software (firmware): you can redistribute it and/or
+       (clobber (reg:CC CC_REG))
+// modify it under the terms of  the GNU General Public License as published
+       ]
+// by the Free Software Foundation, either version 3 of the License, or (at
+       "(ZIP_HAS_DI)"
+// your option) any later version.
+       "AND    %L2,%L0\t; AND:DI\n\tAND\t%H2,%H0"
+//
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+// This program is distributed in the hope that it will be useful, but WITHOUT
+;
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
+;
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+;
 
+; iOR
 
+;
 
+;
 
+(define_insn "iordi3"
 
+       [(set (match_operand:DI 0 "register_operand" "=r")
 
+               (ior:DI (match_operand:DI 1 "register_operand" "%0")
 
+                       (match_operand:DI 2 "register_operand" "r")))
 
+       (clobber (reg:CC CC_REG))
 
+       ]
 
+       "(ZIP_HAS_DI)"
 
+       "OR     %L2,%L0\t; OR:DI\n\tOR\t%H2,%H0"
 
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
 
+;
 
+;
 
+;
 
+; XOR
 
+;
 
+;
 
+(define_insn "xordi3"
 
+       [(set (match_operand:DI 0 "register_operand" "=r")
 
+               (xor:DI (match_operand:DI 1 "register_operand" "%0")
 
+                       (match_operand:DI 2 "register_operand" "r")))
 
+       (clobber (reg:CC CC_REG))
 
+       ]
 
+       "(ZIP_HAS_DI)"
 
+       "XOR    %L2,%L0\t; XOR:DI\n\tXOR\t%H2,%H0"
 
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
 
+;
 
+;
 
+; NEG
 
+;
 
+;
 
+(define_insn "negdi2"
 
+       [(set (match_operand:DI 0 "register_operand" "=r")
 
+               (neg:DI (match_operand:DI 1 "register_operand" "0")))
 
+       (clobber (reg:CC CC_REG))
 
+       ]
 
+       "(ZIP_HAS_DI)"
 
+       "XOR    -1,%L0\t; NEG:DI\n\tXOR\t-1,%H0\n\tADD\t1,%L0\n\tADD.C\t1,%H0"
 
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
 
+;
 
+;
 
+;
 
+; ABS
 
+;
 
+;
 
+(define_insn "absdi2"
 
+       [(set (match_operand:DI 0 "register_operand" "=r")
 
+               (abs:DI (match_operand:DI 1 "register_operand" "0")))
 
+       (clobber (match_scratch:SI 2 "=r"))
 
+       (clobber (reg:CC CC_REG))
 
+       ]
 
+       "(ZIP_HAS_DI)"
 
+       "CLR    %2      ; ABSDI
 
+       TEST    %H0
 
+       LDILO.LT        1,%2
 
+       XOR.LT  -1,%L0
 
+       XOR.LT  -1,%H0
 
+       ADD     %2,%L0
 
+       ADD.C   1,%H0"
 
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
 
+;
 
+;
 
+; NOT
 
+;
 
+;
 
+(define_insn "one_cmpldi2"
 
+       [(set (match_operand:DI 0 "register_operand" "=r")
 
+               (not:DI (match_operand:DI 1 "register_operand" "0")))
 
+       (clobber (reg:CC CC_REG))
 
+       ]
 
+       "(ZIP_HAS_DI)"
 
+       "XOR    -1,%L0\t; NOT:DI\n\tXOR\t-1,%H0"
 
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
 
+;
 
+;
 
+; Unsigned min/max
 
+;
 
+;
 
+(define_insn "umindi3"
 
+       [(set (match_operand:DI 0 "register_operand" "=r")
 
+               (umin:DI (match_operand:DI 1 "register_operand" "%0")
 
+                       (match_operand:DI 2 "register_operand" "r")))
 
+       (clobber (reg:CC CC_REG))
 
+       ]
 
+       "(ZIP_HAS_DI)"
 
+       "CMP    %H0,%H2 ; umin:DI
 
+       CMP.Z   %L0,%L2
 
+       MOV.C   %H2,%H0
 
+       MOV.C   %L2,%L0"
 
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
 
+(define_insn "umaxdi3"
 
+       [(set (match_operand:DI 0 "register_operand" "=r")
 
+               (umax:DI (match_operand:DI 1 "register_operand" "%0")
 
+                       (match_operand:DI 2 "register_operand" "r")))
 
+       (clobber (reg:CC CC_REG))
 
+       ]
 
+       "(ZIP_HAS_DI)"
 
+       "CMP    %H2,%H0 ; umax:DI
 
+       CMP.Z   %L2,%L0
 
+       MOV.C   %H2,%H0
 
+       MOV.C   %L2,%L0"
 
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
 
+;
 
+;
 
+; Multiply
 
+;
 
+;
 
+(define_expand "muldi3"
 
+       [(parallel [(set (match_operand:DI 0 "register_operand" "=r")
 
+               (mult:DI (match_operand:DI 1 "register_operand" "r")
 
+                       (match_operand:DI 2 "register_operand" "r")))
 
+       (clobber (match_dup 1))
 
+       (clobber (match_dup 2))
 
+       (clobber (match_scratch:SI 3 "=r"))
 
+       (clobber (reg:CC CC_REG))])]
 
+       "(ZIP_HAS_DI)")
 
+;
 
+(define_insn "muldi3_raw"
 
+       [(set (match_operand:DI 0 "register_operand" "=r")
 
+               (mult:DI (match_operand:DI 1 "register_operand" "r")
 
+                       (match_operand:DI 2 "register_operand" "r")))
 
+       (clobber (match_dup 1))
 
+       (clobber (match_dup 2))
 
+       (clobber (match_scratch:SI 3 "=r"))
 
+       (clobber (reg:CC CC_REG))]
 
+       "(ZIP_HAS_DI)"
 
+       {
 
+               int     regno[3];
 
+               regno[0] = REGNO(operands[0]);
 
+               regno[1] = REGNO(operands[1]);
 
+               regno[2] = REGNO(operands[2]);
 
+               //; We need to adjust what we are doing based upon which
 
+               //; registers are in common.  We have a couple of cases:
 
+               //;
 
+               if ((regno[0] == regno[1])&&(regno[0] == regno[2])) {
 
+                       //; RA = RA * RA
 
+                       //;
 
+                       //; (H0:L0) = (H0:L0) * (H0:L0)
 
+                       //; (H0:L0) = (H0*2^32 + L0) * (H0 * 2^32 + L0)
 
+                       //; (H0:L0) = (H0*H0*2^64 + (H0*L0+L0*H0)*2^32 + L0 *L0)
 
+                       //;     = (H0*L0+L0*H1):(L0*L0)
 
+                       //;    :L0  = LOPART(L0 * L0)
 
+                       //;  H0     = HIPART(L0 * L0)
 
+                       //;  H0    += LOPART(H0 * L0)
 
+                       //;  H0    += LOPART(L0 * H0)
 
+                       //;
 
+                       //;  Rx = L0
 
+                       //;  H0 *= L0  ( =   LOPART( HI * LO )
 
+                       //;  H0 <<= 1  ( = 2*LOPART( HI * LO ) )
 
+                       //;  Rx *= L0  ( =   HIPART( LO * LO )
 
+                       //;  L0 *= L0  ( =   LOPART( LO * LO )
 
+                       //;  H0 += Rx  ( = 2*LOPART( HI * LO ) + HIPART( LO *LO)
 
+                       //;
 
+                       return "; muldi3_raw/A (%H0:%L0) = (%H1:%L1) * (%H2:%L2)\n"
 
+                               "\tMOV\t%L0,%3\n"
 
+                               "\tMPY\t%L0,%H0\n"
 
+                               "\tLSL\t1,%H0\n"
 
+                               "\tMPYUHI\t%L0,%3\n"
 
+                               "\tMPY\t%L0,%L0\n"
 
+                               "\tADD\t%3,%H0";
 
+               } else if ((regno[0] != regno[1])&&(regno[1] == regno[2])) {
 
+                       //; RA = RB * RB
 
+                       //;
 
+                       //; (H0:L0) = (H1:L1) * (H1:L1)
 
+                       //; (H0:L0) = (H1*2^32 + L1) * (H1 * 2^32 + L1)
 
+                       //; (H0:L0) = (H1*H1*2^64 + (H1*L1+L1*H1)*2^32 + L1 * L1)
 
+                       //;     = (H1*L1+L1*H1):(L1*L1)
 
+                       //;    :L0  = LOPART(L1 * L1)
 
+                       //;  H0     = HIPART(L1 * L1)
 
+                       //;  H0    += LOPART(H1 * L1)
 
+                       //;  H0    += LOPART(L1 * H1)
 
+                       //;
 
+                       //; -------------------
 
+                       //;     L0  = L1
 
+                       //;     L0  = LOPART(L0 * L1)
 
+                       //;     H0  = H1
 
+                       //;     H0  = LOPART(H0 * L1)
 
+                       //;     H0 <<= 1;       i.e. *= 2
 
+                       //;     L1  = HIPART(L1 * L1)
 
+                       //;     H0 += L1
 
+                       //;
 
+                       return "; muldi3_raw/B (%H0:%L0) = (%H1:%L1) * (%H2:%L2)\n"
 
+                       "\tMOV\t%L1,%L0\n"
 
+                       "\tMPY\t%L1,%L0\n"
 
+                       "\tMOV\t%H1,%H0\n"
 
+                       "\tMPY\t%H1,%H0\n"
 
+                       "\tLSL\t1,%H0\n"
 
+                       "\tMPY\t%L1,%L1\n"
 
+                       "\tADD\t%L2,%H0";
 
+               } else if ((regno[0] == regno[1])&&(regno[1] != regno[2])) {
 
+                       //; RA = RA * RB, with scratch Rx
 
+                       //;
 
+                       //; (H0:L0) = (H0:L0) * (H1:L1)
 
+                       //; (H0:L0) = (H0*2^32 + L0) * (H1 * 2^32 + L1)
 
+                       //; (H0:L0) = (H0*H1*2^64 + (H0*L1+L0*H1)*2^32 + L0 *L1)
 
+                       //;     = (H0*L1+L0*H1):(L0*L1)
 
+                       //;     Rx  = L0
 
+                       //;    :L0  = LOPART(L1 * R0)
 
+                       //;  H0     = LOPART(H0 * L1)
 
+                       //;  H0    += H1 = LOPART(Rx * H1)
 
+                       //;  H0    += HIPART(L1 * Rx)
 
+                       //;
 
+                       return "; muldi3_raw/C (%H0:%L0) = (%H1:%L1) * (%H2:%L2)\n"
 
+                       "\tMOV\t%L0,%3\n"
 
+                       "\tMPY\t%L1,%L0\n"
 
+                       "\tMOV\t%L1,%H0\n"
 
+                       "\tMPY\t%H1,%H0\n"
 
+                       "\tMPY\t%3,%H1\n"
 
+                       "\tADD\t%H1,%H0\n"
 
+                       "\tMPY\t%3,%L1\n"
 
+                       "\tADD\t%L1,%H0";
 
+               } else {
 
+                       //; RA = RB * RC
 
+                       //;
 
+                       //; (H0:L0) = (H1:L1) * (H2:L2)
 
+                       //; (H0:L0) = (H1*2^32 + L1) * (H2 * 2^32 + L2)
 
+                       //; (H0:L0) = (H1*H2*2^64 + (H1*L2+L1*H2)*2^32 + L1 *L2)
 
+                       //;     = (H1*L2+L1*H2):(L1*L2)
 
+                       //;    :L0  = LOPART(L1 * L2)
 
+                       //;  H0     = HIPART(L1 * L2)
 
+                       //;  H0    += LOPART(H1 * L2)
 
+                       //;  H0    += LOPART(L1 * H2)
 
+                       //;
 
+                       //; We can re-order this to try to save some registers
 
+                       //;
 
+                       //;     H1 *= L0                // Was H1 * L2
 
+                       //;    :L0  = LOPART(L1 * L2)
 
+                       //;  H0     = LOPART(L1 * R1)
 
+                       //;  H0    += HIPART(L1 * H2)
 
+                       //;  H0    += H1
 
+                       //;
 
+                    return "; muldi3_raw/D (%H0:%L0) = (%H1:%L1) * (%H2:%L2)\n"
 
+                       "\tMPY  %L2,%H1 ; H1 = H1 * L2\n"
 
+                       "\tMPY  %L1,%H2 ; H2 = L1 * L2\n"
 
+                       "\tMOV  %L2,%L0 ; H0:L0 = L1 * L2\n"
 
+                       "\tMOV  %L2,%H0\n"
 
+                       "\tMPY  %L1,%L0\n"
 
+                       "\tMPYUHI       %L1,%H0\n"
 
+                       "\tADD  %H2,%H0 ; H0 += (H2 = L1 * H2)\n"
 
+                       "\tADD  %H1,%H0 ; H0 += (H1 = H1 * L2)";
 
+               }
 
+       }
 
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
 
+;
 
+;
 
+; Still missing DI instructions for smin:DI, smax:DI, movdicc, adddicc,
 
+;      div:di, divu:di (library routine)
 
+;
 
+;
 
+;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;;
 
+;; Conditional arithmetic instructions
 
+;;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;
 
+;
 
+;
 
+;
 
+(define_insn "cstoredi4" ; Store 0 or 1 in %0 based on cmp between %2&%3
 
+       [(set (match_operand:SI 0 "register_operand" "=r")
 
+               (if_then_else:SI (match_operator 1 "ordered_comparison_operator"
 
+                       [(match_operand:DI 2 "register_operand" "r")
 
+                               (match_operand:DI 3 "register_operand" "r")])
 
+                       (const_int 1) (const_int 0)))
 
+       (clobber (reg:CC CC_REG))]
 
+       "(ZIP_HAS_DI)&&(0)"
 
+       {
 
+               switch(GET_CODE(operands[1])) {
 
+               case EQ:        return "CLR\t%0\t; CSTORE-EQ\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.Z\t1,%0\n";
 
+               case NE:        return "CLR\t%0\t; CSTORE-NE\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.NZ\t1,%0\n";
 
+               //; Missing LT
 
+               //; Missing LE
 
+               //; Missing GT
 
+               //; Missing GE
 
+               case LTU:       return "CLR\t%0\t; CSTORE-LTU\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.C\t1,%0\n";
 
+               case LEU:
 
+                       return "CLR\t%0\t; CSTORE-LEU\n\tCMP\t%H2,%H3\n\tCMP.Z\t%L2,%L3\n\tLDILO.NC\t1,%0\n";
 
+               case GTU:       return "CLR\t%0\t; CSTORE-GTU\n\tCMP\t%H2,%H3\n\tCMP.Z\t%L2,%L3\n\tLDILO.C\t1,%0\n";
 
+               case GEU:
 
+                       return "CLR\t%0\t; CSTORE-GEU\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.NC\t1,%0\n";
 
+               default:
 
+                       gcc_unreachable();
 
+               }
 
+       }
 
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
 
+;
 
+;
 
+;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;;
 
+;; Comparison instructions, both compare and test
 
+;;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;
 
+;
 
+;
 
+(define_expand "cmpdi"
 
+       [(set (reg:CC CC_REG) (compare:CC
 
+               (match_operand:DI 0 "register_operand" "r")
 
+               (match_operand:DI 1 "nonmemory_operand" "")))]
 
+       ""
 
+       {
 
+               if (!REG_P(operands[1])) {
 
+                       if (can_create_pseudo_p()) {
 
+                               //; fprintf(stderr, "Generating pseudo register for compare\n");
 
+                               rtx tmp = gen_reg_rtx(DImode);
 
+                               emit_insn(gen_movdi(tmp,operands[1]));
 
+                               operands[1] = tmp;
 
+                               emit_insn(gen_cmpdi_reg(operands[0],tmp));
 
+                               DONE;
 
+                       } else FAIL;
 
+               }
 
+       })
 
+(define_insn "cmpdi_reg"
 
+       [(set (reg:CC CC_REG) (compare:CC
 
+               (match_operand:SI 0 "register_operand" "r")
 
+               (match_operand:SI 1 "register_operand" "r")))]
 
+       ""
 
+       "CMP\t%H1,%H0
 
+       CMP.Z\t%L1,%L0"
 
+       [(set_attr "ccresult" "set")])
 
+;
 
+;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;;
 
+;; Conditional move instructions, since these won't accept conditional
 
+;;     execution RTL
 
+;;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;
 
+(define_expand "cbranchdi4"
 
+       [(set (pc) (if_then_else
 
+               (match_operator 0 "ordered_comparison_operator"
 
+                       [(match_operand:DI 1 "register_operand" "r")
 
+                               (match_operand:DI 2 "nonimmediate_operand" "")])
 
+                       (label_ref (match_operand 3 "" ""))
 
+                       (pc)))
 
+       (clobber (reg:CC CC_REG))]
 
+       "(ZIP_HAS_DI)"
 
+       {
 
+               if (!REG_P(operands[2])) {
 
+                       if ((CONST_INT_P(operands[2]))
 
+                               &&(INTVAL(operands[2])> -(1l<<17))
 
+                               &&(INTVAL(operands[2])<(1l<<17)-1)) {
 
+                               emit_jump_insn(gen_cbranchdi4_internal(operands[0],
 
+                                       operands[1], operands[2], operands[3]));
 
+                               DONE;
 
+                       } if (can_create_pseudo_p()) {
 
+                               rtx tmp = gen_reg_rtx(DImode);
 
+                               emit_insn(gen_movsi(tmp, operands[2]));
 
+                               operands[2] = tmp;
 
+                       }
 
+               }
 
+
 
+               if (REG_P(operands[2])) {
 
+                       emit_jump_insn(gen_cbranchdi4_internal(operands[0],
 
+                               operands[1], operands[2], operands[3]));
 
+                       DONE;
 
+               }
 
+       })
 
+(define_insn "cbranchdi4_internal"
 
+       [(set (pc) (if_then_else
 
+               (match_operator 0 "ordered_comparison_operator"
 
+                       [(match_operand:DI 1 "register_operand" "r,r,r")
 
+                               (match_operand:DI 2 "nonmemory_operand" "K,x,r")])
 
+                       (label_ref (match_operand 3 "" ""))
 
+                       (pc)))
 
+       (clobber (reg:CC CC_REG))]
 
+       "(ZIP_HAS_DI)"
 
+       {
 
+               return zip_cbranchdi(operands[0], operands[1], operands[2], operands[3]);
 
+       }
 
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
 
+;
 
+;
 
+;
 
+;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;;
 
+;; Unimplemented (or not yet implemented) RTL Codes
 
+;;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;
 
+;
 
+;
 
+;
 
+;(define_insn "addvdi4"
 
+;      )
 
+;(define_insn "subvdi4"
 
+;      )
 
+;(define_insn "mulvdi4"
 
+;      )
 
+;(define_insn "umulvdi4"
 
+;      )
 
+;(define_insn "umulvdi4"
 
+;      )
 
+;(define_insn "negvdi3"
 
+;      )
 
+;
 
+;(define_insn "maddsidi4"
 
+;(define_insn "umaddsidi4"
 
+;(define_insn "msubsidi4"
 
+;(define_insn "umsubsidi4"
 
+;
 
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip-float.md gcc-6.2.0-zip/gcc/config/zip/zip-float.md
 
--- gcc-6.2.0/gcc/config/zip/zip-float.md       1969-12-31 19:00:00.000000000 -0500
 
+++ gcc-6.2.0-zip/gcc/config/zip/zip-float.md   2017-01-10 14:01:42.029341062 -0500
 
@@ -0,0 +1,138 @@
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;;
 
+;; Filename:   zip-float.md
 
+;;
 
+;; Project:    Zip CPU -- a small, lightweight, RISC CPU soft core
 
+;;
 
+;; Purpose:    This is the machine description of the ZipCPU floating point
 
+;;             unit (if installed).
 
+;;
 
+;;
 
+;; Creator:    Dan Gisselquist, Ph.D.
 
+;;             Gisselquist Technology, LLC
 
+;;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;;
 
+;; Copyright (C) 2015,2017, Gisselquist Technology, LLC
 
+;;
 
+;; This program is free software (firmware): you can redistribute it and/or
 
+;; modify it under the terms of  the GNU General Public License as published
 
+;; by the Free Software Foundation, either version 3 of the License, or (at
 
+;; your option) any later version.
 
+;;
 
+;; This program is distributed in the hope that it will be useful, but WITHOUT
 
+;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
 
+;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 
+;; for more details.
 
+;;
 
+;; License:    GPL, v3, as defined and found on www.gnu.org,
 
+;;             http://www.gnu.org/licenses/gpl.html
 
+;;
 
+;;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;;
 
+;;
 
+;
 
+;
 
+;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;;
 
+;; Floating point Op-codes
 
+;;
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+;
 
+;
 
+;
 
+(define_insn "addsf3"
 
+       [(set (match_operand:SF 0 "register_operand" "=r")
 
+               (plus:SF (match_operand:SF 1 "register_operand" "0")
 
+                       (match_operand:SF 2 "register_operand" "r")))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
 
+       "(ZIP_FPU)"
 
+       "FPADD  %2,%0"
 
+       [(set_attr "ccresult" "unknown")])
 
+(define_insn "subsf3"
 
+       [(set (match_operand:SF 0 "register_operand" "=r")
 
+               (minus:SF (match_operand:SF 1 "register_operand" "0")
 
+                       (match_operand:SF 2 "register_operand" "r")))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
 
+       "(ZIP_FPU)"
 
+       "FPSUB  %2,%0"
 
+       [(set_attr "ccresult" "unknown")])
 
+(define_insn "mulsf3"
 
+       [(set (match_operand:SF 0 "register_operand" "=r")
 
+               (mult:SF (match_operand:SF 1 "register_operand" "0")
 
+                       (match_operand:SF 2 "register_operand" "r")))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
 
+       "(ZIP_FPU)"
 
+       "FPMUL  %2,%0"
 
+       [(set_attr "ccresult" "unknown")])
 
+(define_insn "divsf3"
 
+       [(set (match_operand:SF 0 "register_operand" "=r")
 
+               (div:SF (match_operand:SF 1 "register_operand" "0")
 
+                       (match_operand:SF 2 "register_operand" "r")))
 
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
 
+       "(ZIP_FPU)"
 
+       "FPDIV  %2,%0"
 
+       [(set_attr "ccresult" "unknown")])
 
+; (define_insn "floatsisf2"
 
+;      [(set (match_operand:SF 0 "register_operand" "=r"
 
+;              (float:QI (match_operand:SF 1 "register_operand" "r"))))
 
+;      (set (reg:CC CC_REG) (compare:CC (match_dup 1) (const_int 0)))]
 
+;      "(ZIP_FPU)"
 
+;      "FPI2F  %1,%0")
 
+; (define_insn "floatunssisf2" ... ?)
 
+; (define_insn "fix_truncsfsi2"
 
+;      [(set (match_operand:QI 0 "register_operand" "=r"
 
+;              (float:SF (match_operand:SF 1 "register_operand" "r"))))
 
+;      (set (reg:CC CC_REG) (compare:CC (match_dup 1) (const_int 0)))]
 
+;      "(ZIP_FPU)"
 
+;      "FPI2F  %1,%0")
 
+; (define_insn "nearbyintsf2" ... ?)
 
+; (define_insn "truncsfsi2" ... ?)
 
+(define_expand "negsf2"
 
+       [(set (match_operand:SF 0 "register_operand" "=r")
 
+               (neg:SF (match_operand:SF 1 "register_operand" "0")))
 
+       ]
 
+       ""
 
+       {
 
+               operands[0] = gen_rtx_SUBREG(SImode, operands[0], 0);
 
+               if (can_create_pseudo_p()) {
 
+                       rtx tmp = gen_reg_rtx(SImode);
 
+                       emit_insn(gen_movsi_ldi(tmp,gen_int_mode(0x80000000,SImode)));
 
+                       emit_insn(gen_xorsi3(operands[0], operands[0], tmp));
 
+                       DONE;
 
+               } else {
 
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
 
+                       emit_insn(gen_iorsi3(operands[0], operands[0],
 
+                               gen_int_mode(1,SImode)));
 
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
 
+                       DONE;
 
+               }
 
+       })
 
+(define_expand "abssf2"
 
+       [(set (match_operand:SF 0 "register_operand" "=r")
 
+               (abs:SF (match_operand:SF 1 "register_operand" "0")))
 
+       ]
 
+       ""
 
+       {
 
+               operands[0] = gen_rtx_SUBREG(SImode, operands[0], 0);
 
+               if (can_create_pseudo_p()) {
 
+                       rtx tmp = gen_reg_rtx(SImode);
 
+                       emit_insn(gen_movsi_ldi(tmp,gen_int_mode(0x7fffffff,SImode)));
 
+                       emit_insn(gen_andsi3(operands[0], operands[0], tmp));
 
+                       DONE;
 
+               } else {
 
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
 
+                       emit_insn(gen_andsi3(operands[0], operands[0],
 
+                               gen_int_mode(-2,SImode)));
 
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
 
+                       DONE;
 
+               }
 
+       })
 
+;
 
+;
 
+; STILL MISSING:
 
+;
 
+;
 
+;
 
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip.h gcc-6.2.0-zip/gcc/config/zip/zip.h
 
--- gcc-6.2.0/gcc/config/zip/zip.h      1969-12-31 19:00:00.000000000 -0500
 
+++ gcc-6.2.0-zip/gcc/config/zip/zip.h  2017-03-03 09:30:57.671304970 -0500
 
@@ -0,0 +1,4114 @@
 
+////////////////////////////////////////////////////////////////////////////////
 
+//
 
+// Filename:   gcc/config/zip/zip.h
 
+//
 
+// Project:    Zip CPU backend for the GNU Compiler Collection
 
+//
 
+// Purpose:
 
+//
 
+// Creator:    Dan Gisselquist, Ph.D.
 
+//             Gisselquist Technology, LLC
 
+//
 
+////////////////////////////////////////////////////////////////////////////////
 
+//
 
+// Copyright (C) 2016-2017, Gisselquist Technology, LLC
 
+//
 
+// This program is free software (firmware): you can redistribute it and/or
 
+// modify it under the terms of  the GNU General Public License as published
 
+// by the Free Software Foundation, either version 3 of the License, or (at
 
+// your option) any later version.
 
+//
 
+// This program is distributed in the hope that it will be useful, but WITHOUT
 
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
 
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+// for more details.
+//
+//
+// You should have received a copy of the GNU General Public License along
+// You should have received a copy of the GNU General Public License along
+// with this program.  (It's in the $(ROOT)/doc directory, run make with no
+// with this program.  (It's in the $(ROOT)/doc directory, run make with no
+// target there if the PDF file isn't present.)  If not, see
+// target there if the PDF file isn't present.)  If not, see
Line 3194... Line 4168...
+#define        ZIP_USER        0        // Assume we are in supervisor mode
+#define        ZIP_USER        0        // Assume we are in supervisor mode
+#define        ZIP_MULTIPLY    1       // Assume we have multiply instructions
+#define        ZIP_MULTIPLY    1       // Assume we have multiply instructions
+#define        ZIP_DIVIDE      1       // Assume we have divide instructions
+#define        ZIP_DIVIDE      1       // Assume we have divide instructions
+#define        ZIP_FPU         0        // Assume we have no floating point instructions
+#define        ZIP_FPU         0        // Assume we have no floating point instructions
+#define        ZIP_PIPELINED   1       // Assume our instructions are pipelined
+#define        ZIP_PIPELINED   1       // Assume our instructions are pipelined
+#define        ZIP_VLIW        1       // Assume we have the VLIW feature
+#define        ZIP_THUMB       1       // Assume we have the THUMB feature
+#define        ZIP_ATOMIC      (ZIP_PIPELINED)
+#define        ZIP_ATOMIC      (ZIP_PIPELINED)
+#define        ZIP_PIC         0        // Attempting to produce PIC code, with GOT
+#define        ZIP_PIC         0        // Attempting to produce PIC code, with GOT
+#define        ZIP_HAS_DI      1
+#define        ZIP_HAS_DI      1
+// Should we use the peephole optimizations?
+// Should we use the peephole optimizations?
+#define        ZIP_PEEPHOLE    1       // 0 means no peephole optimizations.
+#define        ZIP_PEEPHOLE    1       // 0 means no peephole optimizations.
+// How about the new long multiply instruction set?
+#define        ZIP_NOT_AN_INSTRUCTION  "NAI\t;// This is not an instruction.  Getting here implies a compiler error.  Please contact help support\n"
+#define        ZIP_LONGMPY     1       // 0 means use the old instruction set
 
+#define        ZIP_NEW_CONDITION_CODE  0        // 0 means use the old condition codes
 
+
+
+// Zip has 16 registers in each user mode.
+// Zip has 16 registers in each user mode.
+//     Register 15 is the program counter (PC)
+//     Register 15 is the program counter (PC)
+//     Register 14 is the condition codes (CC)
+//     Register 14 is the condition codes (CC)
+//     Register 13 is the stack pointer   (SP)
+//     Register 13 is the stack pointer   (SP)
Line 3221... Line 4193...
+#define        zip_CC          14
+#define        zip_CC          14
+#define        zip_SP          13
+#define        zip_SP          13
+#define        zip_FP          12
+#define        zip_FP          12
+#define        zip_GOT         11
+#define        zip_GOT         11
+// #define     zip_AP          10      // We're using a PSEUDO REG instead
+// #define     zip_AP          10      // We're using a PSEUDO REG instead
 
+#define        zip_R5          5       // Used for the static chain, if it exists
+#define        zip_R1          1
+#define        zip_R1          1
+#define        zip_R0          0
+#define        zip_R0          0
 
+#define        zip_LR          zip_R0  // Link Register is also R0
+
+
+#define        ZIP_FIRST_ARG_REGNO     1
+#define        ZIP_FIRST_ARG_REGNO     1
+#define        ZIP_LAST_ARG_REGNO      5
+#define        ZIP_LAST_ARG_REGNO      5
+#define        NUM_ARG_REGS            (ZIP_LAST_ARG_REGNO-ZIP_FIRST_ARG_REGNO+1)
+#define        NUM_ARG_REGS            (ZIP_LAST_ARG_REGNO-ZIP_FIRST_ARG_REGNO+1)
+#define        MAX_PARM_REGS           (ZIP_LAST_ARG_REGNO-ZIP_FIRST_ARG_REGNO+1)
+#define        MAX_PARM_REGS           (ZIP_LAST_ARG_REGNO-ZIP_FIRST_ARG_REGNO+1)
Line 3240... Line 4214...
+#define        FILE_ASM_OP             "\t.file\n"
+#define        FILE_ASM_OP             "\t.file\n"
+
+
+/* Output and Generation of Labels */
+/* Output and Generation of Labels */
+#define        GLOBAL_ASM_OP           "\t.global\t"
+#define        GLOBAL_ASM_OP           "\t.global\t"
+
+
+#undef BITS_PER_UNIT
+#define        BITS_PER_WORD           32
+#define        BITS_PER_UNIT   (32)
 
+
 
+/* Assembler Commands for Alignment */
 
+#define        ASM_OUTPUT_ALIGN(STREAM,POWER)  \
 
+       { int pwr = POWER; fprintf(STREAM, "\t.p2align %d\n", (pwr<2)?2:pwr); }
 
+
+
+
+
+/* A C compound statement to output to stdio stream STREAM the assembler syntax
+/* A C compound statement to output to stdio stream STREAM the assembler syntax
+ * for an instruction operand X. */
+ * for an instruction operand X. */
+#define        PRINT_OPERAND(STREAM, X, CODE)  zip_print_operand(STREAM, X, CODE)
+#define        PRINT_OPERAND(STREAM, X, CODE)  zip_print_operand(STREAM, X, CODE)
Line 3280... Line 4249...
+
+
+
+
+/* The best alignment to use in cases where we have a choice. */
+/* The best alignment to use in cases where we have a choice. */
+#define        FASTEST_ALIGNMENT       BITS_PER_WORD
+#define        FASTEST_ALIGNMENT       BITS_PER_WORD
+
+
+/* MAX_FIXED_MODE_SIZE -- An integer expression for the size in bits of the
 
+ * largest integer machine mode that should actually be used.  All integer
 
+ * machine modes of this size and smaller can be used for structures and unions
 
+ * with the appropriate sizes.  If this macro is undefined,
 
+ * GET_MODE_BITSIZE(DImode) is assumed.
 
+ *
 
+ * ZipCPU -- The default looks good enough for us.
 
+ */
 
+
 
+/* Generate Code for Profiling
+/* Generate Code for Profiling
+ */
+ */
+#define        FUNCTION_PROFILER(FILE,LABELNO)         (abort(), 0)
+#define        FUNCTION_PROFILER(FILE,LABELNO)         (abort(), 0)
+
+
+
+
Line 3335... Line 4295...
+ * difference between the two is that LIB_SPEC is used at the end of the
+ * difference between the two is that LIB_SPEC is used at the end of the
+ * command given to the linker.
+ * command given to the linker.
+ *
+ *
+ * If this macro is not defined, a default is provided that loads the standard
+ * If this macro is not defined, a default is provided that loads the standard
+ * C library from the usual place.  See 'gcc.c'.
+ * C library from the usual place.  See 'gcc.c'.
 
+ *
 
+ * ZipCPU ... We need this at its default value.  It is necessary to build
 
+ * the various GCC libraries that depend upon one another and newlib.  Hence,
 
+ * as an example we *must* include the library containing strnlen or libgfortran
 
+ * will not.  Alternatively, we might figure out how to pass arguments to the
 
+ * compiler via the configure process ... but we'll just allow this to have its
 
+ * default value for now.
+ */
+ */
+#undef LIB_SPEC
+// #undef      LIB_SPEC
+// #define     LIB_SPEC        "%{!g:-lc} %{g:-lg} -lzip"
+// #define     LIB_SPEC        "%{!g:-lc} %{g:-lg} -lzip"
+#define        LIB_SPEC        ""
+// #define     LIB_SPEC        ""
+
+
+/* LIBGCC_SPEC ... Another C string constant that tells the GCC driver program
+/* LIBGCC_SPEC ... Another C string constant that tells the GCC driver program
+ * hoow and when to place a reference to 'libgcc.a' into the linker command
+ * hoow and when to place a reference to 'libgcc.a' into the linker command
+ * line.  This constant is placed both before and after the value of LIB_SPEC.
+ * line.  This constant is placed both before and after the value of LIB_SPEC.
+ *
+ *
Line 3421... Line 4388...
+ * command line parameters we've been given indicate that our CPU has.  That
+ * command line parameters we've been given indicate that our CPU has.  That
+ * way, code can be adjusted depending upon the CPU's capabilities.
+ * way, code can be adjusted depending upon the CPU's capabilities.
+ */
+ */
+#define        TARGET_CPU_CPP_BUILTINS()                       \
+#define        TARGET_CPU_CPP_BUILTINS()                       \
+       { builtin_define("__ZIPCPU__");                 \
+       { builtin_define("__ZIPCPU__");                 \
 
+       builtin_define("__IEEE_BIG_ENDIAN");                    \
 
+       builtin_define("_LDBL_EQ_DBL");                         \
+       if (ZIP_FPU) builtin_define("__ZIPFPU__");      \
+       if (ZIP_FPU) builtin_define("__ZIPFPU__");      \
 
+       else builtin_define("_SOFT_FLOAT");                     \
+       if (ZIP_ATOMIC) builtin_define("__ZIPATOMIC__");        \
+       if (ZIP_ATOMIC) builtin_define("__ZIPATOMIC__");        \
+       }
+       }
+       // If (zip_param_has_fpu)  builtin_define("__ZIPFPU__");
+       // If (zip_param_has_fpu)  builtin_define("__ZIPFPU__");
+       // If (zip_param_has_div)  builtin_define("__ZIPDIV__");
+       // If (zip_param_has_div)  builtin_define("__ZIPDIV__");
+       // If (zip_param_has_mpy)  builtin_define("__ZIPMPY__");
+       // If (zip_param_has_mpy)  builtin_define("__ZIPMPY__");
Line 3483... Line 4453...
+ * any RTL has begun.  The intention is to allow the initialization of the
+ * any RTL has begun.  The intention is to allow the initialization of the
+ * function pointer init_machine_status.
+ * function pointer init_machine_status.
+ */
+ */
+// #warning "I may need to define this to handle function return addresses ..."
+// #warning "I may need to define this to handle function return addresses ..."
+
+
 
+
+/* 17.05 Storage Layout */
+/* 17.05 Storage Layout */
+
+
 
+
+/* Storage Layout */
+/* Storage Layout */
+#define        BITS_BIG_ENDIAN         0        // MSB has highest number
+#define        BITS_BIG_ENDIAN         0        // MSB has highest number
+#define        BYTES_BIG_ENDIAN        1       // 1 if MSB is lowest number
+#define        BYTES_BIG_ENDIAN        1       // 1 if MSB is lowest number
+#define        WORDS_BIG_ENDIAN        1       // 1 if MSW is lowest number
+#define        WORDS_BIG_ENDIAN        1       // 1 if MSW is lowest number
+#define        FLOAT_WORDS_BIG_ENDIAN  1
+#define        FLOAT_WORDS_BIG_ENDIAN  1
+#define        BITS_PER_WORD           32
+#define        UNITS_PER_WORD          4       // Storage units in a word, pwr of 2:1-8
+// #define     MAX_BITS_PER_WORD       // defaults to BITS_PER_WORD
 
+#define        UNITS_PER_WORD          1       // Storage units in a word, pwr of 2:1-8
 
+#define        MIN_UNITS_PER_WORD      1       // Default is UNITS_PER_WORD
 
+/* POINTER_SIZE ... Width of a pointer in bits.  You must specify a value no
+/* POINTER_SIZE ... Width of a pointer in bits.  You must specify a value no
+ * wider than the width of Pmode.  If it is not equal to the width of Pmode,
+ * wider than the width of Pmode.  If it is not equal to the width of Pmode,
+ * you must define POINTERS_EXTEND_UNSIGNED. If you do not specify a value the
+ * you must define POINTERS_EXTEND_UNSIGNED. If you do not specify a value the
+ * default is BITS_PER_WORD.
+ * default is BITS_PER_WORD.
+ *
+ *
+ * ZipCPU --- All of our pointers are 32-bits, the width of our address bus.
+ * ZipCPU --- All of our pointers are 32-bits, the width of our address bus.
+ */
+ */
+#define        POINTER_SIZE            32      // Ptr width in bits
+#define        POINTER_SIZE            32      // Ptr width in bits
 
+
+/* POINTERS_EXTEND_UNSIGNED ... A C expression that determines how pointers
+/* POINTERS_EXTEND_UNSIGNED ... A C expression that determines how pointers
+ * should be extended from ptr_mode to either Pmode or word_mode.  It is greater
+ * should be extended from ptr_mode to either Pmode or word_mode.  It is greater
+ * than zero if pointers should be zero-extended, zero if they should be sign
+ * than zero if pointers should be zero-extended, zero if they should be sign
+ * extended, and negative if some other conversion is needed.  In the last case,
+ * extended, and negative if some other conversion is needed.  In the last case,
+ * the extension is done by the target's ptr_extend instruction.
+ * the extension is done by the target's ptr_extend instruction.
+ *
+ *
+ * You need not define this macro if the ptr_mode, Pmode, and word_mode are all
+ * You need not define this macro if the ptr_mode, Pmode, and word_mode are all
+ * the same width.
+ * the same width.
+ *
+ *
+ * ZipCPU --- While we shouldn't need this, QImode and HImode have the same
+ * ZipCPU --- We don't need to define this macro, since PMode and ptr_mode, and
+ * number of bits as SImode.  Therefore, one might wish to convert between the
+ * our word_mode (SImode) all have the same width.
+ * two.  Hence, we specify how we would do that here.
 
+ */
+ */
+#define        POINTERS_EXTEND_UNSIGNED        1
+// #define     POINTERS_EXTEND_UNSIGNED        1
+
+
+/* PROMOTE_MODE(m,unsignedp,type) ... A macro to update m and unsignedp when an
+/* PROMOTE_MODE(m,unsignedp,type) ... A macro to update m and unsignedp when an
+ * object whose type is type and which has he specified mode and signedness is
+ * object whose type is type and which has he specified mode and signedness is
+ * to be stored in a register.  This macro is only called when type is a scalar
+ * to be stored in a register.  This macro is only called when type is a scalar
+ * type.
+ * type.
Line 3537... Line 4506...
+ * 64-bits. On such machines, set unsignedp according to which kind of extension
+ * 64-bits. On such machines, set unsignedp according to which kind of extension
+ * is more efficient.
+ * is more efficient.
+ *
+ *
+ * Do not define this macro if it would never modify m.
+ * Do not define this macro if it would never modify m.
+ *
+ *
+ * ZipCPU --- We need to always (if possible) promote everything to SImode where
+ * ZipCPU ---
+ * we can handle things.  HImode and QImode just don't make sense on this CPU.
 
+ */
+ */
+#define        PROMOTE_MODE(M,U,T)     if ((GET_MODE_CLASS(M)==MODE_INT)&&(GET_MODE_SIZE(M)<2)) (M)=SImode;
+#define        PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
 
+       do {                                                    \
 
+               if ((GET_MODE_CLASS(MODE) == MODE_INT)          \
 
+                               && (GET_MODE_SIZE(MODE) < 4)) { \
 
+                       (MODE) = SImode;                        \
 
+                       (UNSIGNEDP) = 1;                        \
 
+               }                                               \
 
+       } while(0)
+
+
+// TARGET_PROMOTE_FUNCTION_MODE
+// TARGET_PROMOTE_FUNCTION_MODE
 
+#define        TARGET_PROMOTE_FUNCTION_MODE    default_promote_function_mode_always_promote
 
+
+/* PARM_BOUNDARY ... Normal alignment required for function parameters on the
+/* PARM_BOUNDARY ... Normal alignment required for function parameters on the
+ * stack, in bits.  All stack parameters receive at least this much alignment
+ * stack, in bits.  All stack parameters receive at least this much alignment
+ * regardless of data type.  On most machines, this is the same as the size of
+ * regardless of data type.  On most machines, this is the same as the size of
+ * an integer.
+ * an integer.
+ */
+ */
Line 3595... Line 4572...
+/* BIGGEST_FIELD_ALIGNMENT ... Biggest alignment that any structure or union
+/* BIGGEST_FIELD_ALIGNMENT ... Biggest alignment that any structure or union
+ * field can require on this machine, in bits.  If defined, this overrides
+ * field can require on this machine, in bits.  If defined, this overrides
+ * BIGGEST_ALIGNMENT for structure and union fields only, unless the field
+ * BIGGEST_ALIGNMENT for structure and union fields only, unless the field
+ * alignment has been set by the __attribute__((aligned(n))) construct.
+ * alignment has been set by the __attribute__((aligned(n))) construct.
+ */
+ */
+#define        BIGGEST_FIELD_ALIGNMENT BITS_PER_UNIT
+#define        BIGGEST_FIELD_ALIGNMENT BITS_PER_WORD
+
+
+/* ADJUST_FIELD_ALIGN
+/* ADJUST_FIELD_ALIGN(FIELD, COMPUTED) ... An expression for the alignment of
 
+ * a structure field FIELD if the alignment computed in the usual way (including
 
+ * applying BIGGEST_ALIGNMENT and BIGGEST_FIELD_ALIGNMENT) is COMPUTED.
+ */
+ */
+#define        ADJUST_FIELD_ALIGN(A,B) BITS_PER_WORD
+// #define     ADJUST_FIELD_ALIGN(A,B) BITS_PER_WORD
+
+
+/* MAX_STACK_ALIGNMENT
+/* MAX_STACK_ALIGNMENT ... Biggest stack alignment guaranteed by the backend.
 
+ * Use this macro to specify the maximum alignment of a variable on the stack.
 
+ *
 
+ * If not defined, the default value is STACK_BOUNDARY
+ */
+ */
+#define        MAX_STACK_ALIGNMENT     BITS_PER_WORD
+// #define     MAX_STACK_ALIGNMENT     BITS_PER_WORD
+
+
+/* MAX_OFILE_ALIGNMENT
+/* MAX_OFILE_ALIGNMENT
+ */
+ */
+
+
+/* DATA_ALIGNMENT(TYPE, BASIC-ALIGN) ... If defined, a C expression to compute
+/* DATA_ALIGNMENT(TYPE, BASIC-ALIGN) ... If defined, a C expression to compute
Line 3615... Line 4597...
+ * BASIC-ALIGN is the alignment that the object would ordinarily have.  The
+ * BASIC-ALIGN is the alignment that the object would ordinarily have.  The
+ * value of this macro is used instead of that alignment to align the object.
+ * value of this macro is used instead of that alignment to align the object.
+ *
+ *
+ * If this macro is not defined, then BASIC-ALIGN is used.
+ * If this macro is not defined, then BASIC-ALIGN is used.
+ *
+ *
+ * ZipCPU -- in hindsight, if this macro is not defined then the compiler is
+ * ZipCPU --
+ * broken.  So we define it to be our fastest alignment, or 32-bits.
 
+ */
+ */
+#define        DATA_ALIGNMENT(TYPE, ALIGN)     BITS_PER_WORD
+// #define     DATA_ALIGNMENT(TYPE, ALIGN)     BITS_PER_WORD
+
+
+
+
+/* DATA_ABI_ALIGNMENT(TYPE,BASIC-ALIGN)
+/* DATA_ABI_ALIGNMENT(TYPE,BASIC-ALIGN)
+ */
+ */
+
+
Line 3640... Line 4621...
+ */
+ */
+#define        CONSTANT_ALIGNMENT(EXP, ALIGN)  BITS_PER_WORD
+#define        CONSTANT_ALIGNMENT(EXP, ALIGN)  BITS_PER_WORD
+
+
+/* LOCAL_ALIGNMENT(TYPE,BASIC-ALIGN) ... If defined ...
+/* LOCAL_ALIGNMENT(TYPE,BASIC-ALIGN) ... If defined ...
+ */
+ */
+#define        LOCAL_ALIGNMENT(TYP,ALIGN)      BITS_PER_WORD
+// #define     LOCAL_ALIGNMENT(TYP,ALIGN)      BITS_PER_WORD
+
+
+/* TARGET_VECTOR_ALIGNMENT
+/* TARGET_VECTOR_ALIGNMENT
+ */
+ */
+
+
+/* STACK_SLOT_ALIGNMENT
+/* STACK_SLOT_ALIGNMENT
+ */
+ */
+#define        STACK_SLOT_ALIGNMENT(T,M,B)     BITS_PER_WORD
+#define        STACK_SLOT_ALIGNMENT(T,M,B)     BITS_PER_WORD
+
+
+/* LOCAL_DECL_ALIGNMEN(DECL)
+/* LOCAL_DECL_ALIGNMEN(DECL)
+ */
+ */
+#define        LOCAL_DECL_ALIGNMENT(DECL)      BITS_PER_WORD
+// #define     LOCAL_DECL_ALIGNMENT(DECL)      BITS_PER_WORD
+
+
+/* MINIMUM_ALIGNMENT
+/* MINIMUM_ALIGNMENT
+ */
+ */
+#define        MINIMUM_ALIGNMENT(EXP,MOD,ALIGN)        BITS_PER_WORD
+// #define     MINIMUM_ALIGNMENT(EXP,MOD,ALIGN)        BITS_PER_WORD
+
+
+/* EMPTY_FIELD_BOUNDARY
+/* EMPTY_FIELD_BOUNDARY
+ * Alignment of field after 'int : 0' in a structure.
+ * Alignment of field after 'int : 0' in a structure.
+ */
+ */
+#define        EMPTY_FIELD_BOUNDARY    BITS_PER_WORD
+#define        EMPTY_FIELD_BOUNDARY    BITS_PER_WORD
Line 3671... Line 4652...
+
+
+/* STRICT_ALIGNMENT ... Set this nonzero if move instructions will actually
+/* STRICT_ALIGNMENT ... Set this nonzero if move instructions will actually
+ * fail to work when given unaligned data.  If instructions will merely go
+ * fail to work when given unaligned data.  If instructions will merely go
+ * slower in that case, define this macro as 0.
+ * slower in that case, define this macro as 0.
+ *
+ *
+ * ZipCPU -- Since we have defined our smallest addressable unit to be a 32-bit
+ * ZipCPU --
+ * word (one byte, on our machine), and since reading any amount of 32-bit words
 
+ * is easy, then there really are no instructions that will ever fail.
 
+ */
+ */
+#define        STRICT_ALIGNMENT        0
+#define        STRICT_ALIGNMENT        1
+
+
+/* PCC_BITFIELD_TYPE_MATTERS -- define this if you wish to imitate the the way
+/* PCC_BITFIELD_TYPE_MATTERS -- define this if you wish to imitate the the way
+ * other C compilers handle alignment of bit-fields and the structures that
+ * other C compilers handle alignment of bit-fields and the structures that
+ * contain them.
+ * contain them.
+ *
+ *
Line 3710... Line 4689...
+ * largest integer machine mode that should actually be used.  All integer
+ * largest integer machine mode that should actually be used.  All integer
+ * machine modes of this size or smaller can be used for structures and unions
+ * machine modes of this size or smaller can be used for structures and unions
+ * with the appropriate sizes.  If this macro is undefined,
+ * with the appropriate sizes.  If this macro is undefined,
+ * GET_MODE_BITSIZE(DImode) is assumed.
+ * GET_MODE_BITSIZE(DImode) is assumed.
+ *
+ *
+ * ZipCPU ... Get_MOD_BITSIZE(DImode) will be 64, and this is really not the
+ * ZipCPU ... Get_MODE_BITSIZE(DImode) will be 64, and this really is the
+ * size on bits of the largest integer machine mode.  However, that's the case
+ * size in bits of the largest integer machine mode.  However, that's the case
+ * with most DI implementations: A long is two words, spliced together.  We'd
+ * with most DI implementations: A long is two words, spliced together.  We'd
+ * like to support that eventually, but we need to get there.  Hence, let's use
+ * like to support that eventually, but we need to get there.  Hence, let's use
+ * compile time flag (ZIP_HAS_DI) that we can enable when we're ready.
+ * compile time flag (ZIP_HAS_DI) that we can enable when we're ready.
+ */
+ */
+#if (ZIP_HAS_DI != 0)
+#undef MAX_FIXED_MODE_SIZE
+#define        MAX_FIXED_MODE_SIZE     64
+#ifdef ZIP_HAS_DI
 
+# define MAX_FIXED_MODE_SIZE   GET_MODE_BITSIZE(DImode)
+#else
+#else
+#define        MAX_FIXED_MODE_SIZE     32
+# define MAX_FIXED_MODE_SIZE   GET_MODE_BITSIZE(SImode)
+#endif
+#endif
+
+
+
+
 
+
+/* 17.06 Layout of Source Language Data Types */
+/* 17.06 Layout of Source Language Data Types */
+
+
+#undef CHAR_TYPE_SIZE
 
+#undef SHORT_TYPE_SIZE
 
+#undef INT_TYPE_SIZE
 
+#undef LONG_TYPE_SIZE
+#undef LONG_TYPE_SIZE
+#undef LONG_LONG_TYPE_SIZE
+#undef LONG_LONG_TYPE_SIZE
+//
+//
+#define        CHAR_TYPE_SIZE  32
 
+#define        SHORT_TYPE_SIZE 32
 
+#define        INT_TYPE_SIZE   32
 
+#define        LONG_TYPE_SIZE  64
+#define        LONG_TYPE_SIZE  64
+#define        LONG_LONG_TYPE_SIZE     64
+#define        LONG_LONG_TYPE_SIZE     64
+// BOOL_TYPE_SIZE defaults to CHAR_TYPE_SIZE
 
+#undef FLOAT_TYPE_SIZE
 
+#undef DOUBLE_TYPE_SIZE
 
+#undef LONG_DOUBLE_TYPE_SIZE
 
+#define        FLOAT_TYPE_SIZE         32
 
+#define        DOUBLE_TYPE_SIZE        64      // This'll need to be done via emulation
 
+#define        LONG_DOUBLE_TYPE_SIZE   64      // This'll need to be done via emulation
 
+// SHORT_FRAC_TYPE_SIZE
+// SHORT_FRAC_TYPE_SIZE
+// LONG_FFRACT_TYPE_SIZE
+// LONG_FFRACT_TYPE_SIZE
+// LONG_LONG_FRACT_TIME_SIZE
+// LONG_LONG_FRACT_TIME_SIZE
+#undef SHORT_ACCUM_TYPE_SIZE
 
+#undef ACCUM_TYPE_SIZE
 
+#undef LONG_ACCUM_TYPE_SIZE
 
+#define        SHORT_ACCUM_TYPE_SIZE   SHORT_TYPE_SIZE
 
+#define        ACCUM_TYPE_SIZE         INT_TYPE_SIZE
 
+#define        LONG_ACCUM_TYPE_SIZE    LONG_TYPE_SIZE
 
+
+
+/* LIBGCC2_GNU_PREFIX ... This macro corresponds to the TARGET_GNU_PREFIX target
+/* LIBGCC2_GNU_PREFIX ... This macro corresponds to the TARGET_GNU_PREFIX target
+ * hook and should be defined if that hook is overriden to be true.  It causes
+ * hook and should be defined if that hook is overriden to be true.  It causes
+ * function names in libgcc to be changed to use a __gnu_ prefix for their name
+ * function names in libgcc to be changed to use a __gnu_ prefix for their name
+ * rather than the default __.  A port which uses this macro should also arrange
+ * rather than the default __.  A port which uses this macro should also arrange
Line 3793... Line 4755...
+/* DEFAULT_SIGNED_CHAR ... An expression whose value is 1 or 0, according to
+/* DEFAULT_SIGNED_CHAR ... An expression whose value is 1 or 0, according to
+ * whether the type char should be signed or unsigned by default.  The user
+ * whether the type char should be signed or unsigned by default.  The user
+ * can always override this default with the options -fsigned-char and
+ * can always override this default with the options -fsigned-char and
+ * -funsigned-char.
+ * -funsigned-char.
+ *
+ *
+ * ZipCPU--let's go with the default behavior.
+ * ZipCPU--Our hardware produces unsigned characters (and shorts) by default,
 
+ * so let's stick to that.
+ */
+ */
+#define        DEFAULT_SIGNED_CHAR     1
+#define        DEFAULT_SIGNED_CHAR     0
+
+
+/* TARGET_DEFAULT_SHORT_ENUMS(VOID) ... This target hook should return true if
+/* TARGET_DEFAULT_SHORT_ENUMS(VOID) ... This target hook should return true if
+ * the compiler should give an enum type only as many bytes as it takes to
+ * the compiler should give an enum type only as many bytes as it takes to
+ * represent the range of possible values of that type.  It should return
+ * represent the range of possible values of that type.  It should return
+ * false if all enum types should be allocated like int.
+ * false if all enum types should be allocated like int.
Line 3838... Line 4801...
+/* WCHAR_TYPE ... A C expression for a string describing the name of the data
+/* WCHAR_TYPE ... A C expression for a string describing the name of the data
+ * type to use for wide characters.  The typedef name wchar_t is defined using
+ * type to use for wide characters.  The typedef name wchar_t is defined using
+ * the contents of  the string.  If you don't define this macro, the default is
+ * the contents of  the string.  If you don't define this macro, the default is
+ * 'int'--good enough for ZipCPU.
+ * 'int'--good enough for ZipCPU.
+ */
+ */
 
+// #define     WCHAR_TYPE      "int"
+
+
+/* WCHAR_TYPE_SIZE ... A C expression for the size in bits of the data type for
+/* WCHAR_TYPE_SIZE ... A C expression for the size in bits of the data type for
+ * wide characters.  This is used in cpp, which cannot make use of WCHAR_TYPE.
+ * wide characters.  This is used in cpp, which cannot make use of WCHAR_TYPE.
 
+ *
 
+ * ZipCPU -- This defaults to INT_TYPE_SIZE, which will work for us
+ */
+ */
+#undef WCHAR_TYPE_SIZE
+// #define     WCHAR_TYPE_SIZE 32
+#define        WCHAR_TYPE_SIZE 32
 
+
+
+/* WINT_TYPE ... A C expression for a string describing the name of the data
+/* WINT_TYPE ... A C expression for a string describing the name of the data
+ * type to use for wide characters passed to printf and returned from getwc.
+ * type to use for wide characters passed to printf and returned from getwc.
+ * The typedef name wint_t is defined using the contents of the string.  See
+ * The typedef name wint_t is defined using the contents of the string.  See
+ *
+ *
+ * ZipCPU -- If you don't define this macro, the default is "unsigned int"--also
+ * ZipCPU -- The default should work well enough for us.
+ * best for us again.
 
+ */
+ */
 
+// #define     WINT_TYPE       "int"
+
+
+/* INTMAX_TYPE ... A C expression for a string describing the name of the
+/* INTMAX_TYPE ... A C expression for a string describing the name of the
+ * data type that can represent any value of any standard or extended signed
+ * data type that can represent any value of any standard or extended signed
+ * integer type.  The typedef name intmax_t is defined using the contents of
+ * integer type.  The typedef name intmax_t is defined using the contents of
+ * the string.
+ * the string.
Line 3872... Line 4837...
+#define        SIG_ATOMIC_TYPE "int"
+#define        SIG_ATOMIC_TYPE "int"
+#else
+#else
+#define        SIG_ATOMIC_TYPE NULL    // We have no atomic types, but registers
+#define        SIG_ATOMIC_TYPE NULL    // We have no atomic types, but registers
+#endif
+#endif
+#undef INT8_TYPE
+#undef INT8_TYPE
+#define        INT8_TYPE               NULL    // We have no 8-bit integer type
+#define        INT8_TYPE               "char"
+#undef INT16_TYPE
+#undef INT16_TYPE
+#define        INT16_TYPE              NULL
+#define        INT16_TYPE              "short int"
+#undef INT32_TYPE
+#undef INT32_TYPE
+#define        INT32_TYPE              "int"
+#define        INT32_TYPE              "int"
+#undef UINT8_TYPE
+#undef UINT8_TYPE
+#define        UINT8_TYPE              NULL
+#define        UINT8_TYPE              "unsigned char"
+#undef UINT16_TYPE
+#undef UINT16_TYPE
+#define        UINT16_TYPE             NULL
+#define        UINT16_TYPE             "short unsigned int"
+#undef UINT32_TYPE
+#undef UINT32_TYPE
+#define        UINT32_TYPE             "unsigned int"
+#define        UINT32_TYPE             "unsigned int"
+#undef INT_LEAST8_TYPE
+#undef INT_LEAST8_TYPE
+#define        INT_LEAST8_TYPE         "int"
+#define        INT_LEAST8_TYPE         "char"
+#undef INT_LEAST16_TYPE
+#undef INT_LEAST16_TYPE
+#define        INT_LEAST16_TYPE        "int"
+#define        INT_LEAST16_TYPE        "short int"
+#undef INT_LEAST32_TYPE
+#undef INT_LEAST32_TYPE
+#define        INT_LEAST32_TYPE        "int"
+#define        INT_LEAST32_TYPE        "int"
+#undef UINT_LEAST8_TYPE
+#undef UINT_LEAST8_TYPE
+#define        UINT_LEAST8_TYPE        "unsigned int"
+#define        UINT_LEAST8_TYPE        "unsigned char"
+#undef UINT_LEAST16_TYPE
+#undef UINT_LEAST16_TYPE
+#define        UINT_LEAST16_TYPE       "unsigned int"
+#define        UINT_LEAST16_TYPE       "short unsigned int"
+#undef UINT_LEAST32_TYPE
+#undef UINT_LEAST32_TYPE
+#define        UINT_LEAST32_TYPE       "unsigned int"
+#define        UINT_LEAST32_TYPE       "unsigned int"
+#undef INT_FAST8_TYPE
+#undef INT_FAST8_TYPE
+#define        INT_FAST8_TYPE          "int"
+#define        INT_FAST8_TYPE          "char"
+#undef INT_FAST16_TYPE
+#undef INT_FAST16_TYPE
+#define        INT_FAST16_TYPE         "int"
+#define        INT_FAST16_TYPE         "short int"
+#undef INT_FAST32_TYPE
+#undef INT_FAST32_TYPE
+#define        INT_FAST32_TYPE         "int"
+#define        INT_FAST32_TYPE         "int"
+#undef UINT_FAST8_TYPE
+#undef UINT_FAST8_TYPE
+#define        UINT_FAST8_TYPE         "unsigned int"
+#define        UINT_FAST8_TYPE         "unsigned char"
+#undef UINT_FAST16_TYPE
+#undef UINT_FAST16_TYPE
+#define        UINT_FAST16_TYPE        "unsigned int"
+#define        UINT_FAST16_TYPE        "short unsigned int"
+#undef UINT_FAST32_TYPE
+#undef UINT_FAST32_TYPE
+#define        UINT_FAST32_TYPE        "unsigned int"
+#define        UINT_FAST32_TYPE        "unsigned int"
+#undef INTPTR_TYPE
+#undef INTPTR_TYPE
+#define        INTPTR_TYPE             "unsigned int"
+#define        INTPTR_TYPE             "unsigned int"
+#undef UINTPTR_TYPE
+#undef UINTPTR_TYPE
Line 4076... Line 5041...
+ * hold a value of mode MODE.
+ * hold a value of mode MODE.
+ *
+ *
+ * On a machine where all registers are exactly one word, a suitable definition
+ * On a machine where all registers are exactly one word, a suitable definition
+ * is given of ((GET_MODE_SIZE(MODE)+UNITS_PER_WORD-1)/UNITS_PER_WORD.
+ * is given of ((GET_MODE_SIZE(MODE)+UNITS_PER_WORD-1)/UNITS_PER_WORD.
+ *
+ *
+ * On ZipCPU, we might do
 
+ *     ((((MODE)==DImode)||((MODE)==DFmode))?2:1)
 
+ * but I think the default (above) code should work as well.  Hence, let's stick
 
+ * with the default, lest someone try to create larger modes (TImode, OImode,
 
+ * XImode) and expect us to follow them properly some how.
 
+ *
 
+ * Okay, now in hind sight, we know that the default doesn't work for our
 
+ * architecture, since GET_MODE_SIZE(SImode)=4, not 1.  Thus, let's rearrange
 
+ * this expression to work in bits rather than in bytes and we'll know more
 
+ * of what we are doing.
 
+ */
+ */
+#undef HARD_REGNO_NREGS
+#undef HARD_REGNO_NREGS
+#define        HARD_REGNO_NREGS(REGNO, MODE)   ((GET_MODE_SIZE(MODE)+UNITS_PER_WORD-1)\
+#define        HARD_REGNO_NREGS(REGNO, MODE)   ((GET_MODE_SIZE(MODE)+UNITS_PER_WORD-1)\
+               / (UNITS_PER_WORD))
+               / (UNITS_PER_WORD))
+
+
Line 4150... Line 5105...
+ */
+ */
+#define        MODES_TIEABLE_P(M1,M2)  1
+#define        MODES_TIEABLE_P(M1,M2)  1
+
+
+/* TARGET_HARD_REGNO_SCRATCH_OK(REGNO)
+/* TARGET_HARD_REGNO_SCRATCH_OK(REGNO)
+ * This target hook should return true if it is OK to use a hard register
+ * This target hook should return true if it is OK to use a hard register
+ * REGNO has a scratch register in peephole2.  One common use of this macro is
+ * REGNO as a scratch register in peephole2.  One common use of this macro is
+ * to prevent using of a register that is not saved by a prologue in an
+ * to prevent using of a register that is not saved by a prologue in an
+ * interrupt handler.  The default version of this hook always returns true.
+ * interrupt handler.  The default version of this hook always returns true.
+ *
+ *
+ * ZipCPU --- the default works for us as well.  If you are in an interrupt
+ * ZipCPU --- the default works for us as well.  If you are in an interrupt
+ * context, you have an entirely new set of registers (the supervisor set), so
+ * context, you have an entirely new set of registers (the supervisor set), so
Line 4173... Line 5128...
+ *
+ *
+ * Zip CPU has no stack-like registers, as their definition is different from
+ * Zip CPU has no stack-like registers, as their definition is different from
+ * the ZipCPU stack pointer register.
+ * the ZipCPU stack pointer register.
+ */
+ */
+
+
+// #define     ZIP_REG_BYTE_SIZE       1
 
+
 
+/* 17.08 Register Classes */
+/* 17.08 Register Classes */
+
+
+/* enum reg_class ... An enumerate type that must be defined with all the
+/* enum reg_class ... An enumerate type that must be defined with all the
+ * register class names as enumerated values.  NO_REGS must be first.  ALL_REGS
+ * register class names as enumerated values.  NO_REGS must be first.  ALL_REGS
+ * must be the last register class, followed by one more enumerated value,
+ * must be the last register class, followed by one more enumerated value,
Line 4418... Line 5371...
+ * user set of registers.  However, we're not building for that mode (now),
+ * user set of registers.  However, we're not building for that mode (now),
+ * so we'll leave this at the default of NO_REGS.
+ * so we'll leave this at the default of NO_REGS.
+ */
+ */
+
+
+/* TARGET_CSTORE_MODE(ICODE) ... Defines the machine mode to use for the
+/* TARGET_CSTORE_MODE(ICODE) ... Defines the machine mode to use for the
+ * boolean result of conditional store patterns.  The OCIDE argument is the
+ * boolean result of conditional store patterns.  The ICODE argument is the
+ * instruction code for the cstore being performed.  Not defining this hook is
+ * instruction code for the cstore being performed.  Not defining this hook is
+ * the same as accepting the mode encoded into operand 0 of the cstore expander
+ * the same as accepting the mode encoded into operand 0 of the cstore expander
+ * patterns.
+ * patterns.
+ *
+ *
+ * ??? ZipCPU --- I don't follow this documentation.  We'll leave this at the
+ * ??? ZipCPU --- I don't follow this documentation.  We'll leave this at the
Line 4490... Line 5443...
+
+
+/* STACK_ALIGNMENT_NEEDED ... Define to zero to disable final alignment of the
+/* STACK_ALIGNMENT_NEEDED ... Define to zero to disable final alignment of the
+ * stack during reload.  The nonzero default for this macro is suitable for most
+ * stack during reload.  The nonzero default for this macro is suitable for most
+ * ports.
+ * ports.
+ *
+ *
+ * ZipCPU --- we'll leave this at the default, although if any alignment code
+ * ZipCPU --- Yes, our stack needs to be aligned.  The default should work
+ * shows up on the stack we may need to adjust it.
+ * nicely.
+ */
+ */
+
+
+/* STACK_POINTER_OFFSET ... Offset from the SP register to the first location at
+/* STACK_POINTER_OFFSET ... Offset from the SP register to the first location at
+ * which outgoing arguments are placed.  If not specified, the default value
+ * which outgoing arguments are placed.  If not specified, the default value
+ * of zero is used.  This is the proper value for most machines.
+ * of zero is used.  This is the proper value for most machines.
Line 4554... Line 5507...
+ * of the COUNT frame, or the frame pointer of the COUNT-1 frame if
+ * of the COUNT frame, or the frame pointer of the COUNT-1 frame if
+ * RETURN_ADDR_IN_PREVIOUS_FRAME is nonzero.  The value of the expression must
+ * RETURN_ADDR_IN_PREVIOUS_FRAME is nonzero.  The value of the expression must
+ * always be the correct address when COUNT is nonzero, but may be NULL_RTX if
+ * always be the correct address when COUNT is nonzero, but may be NULL_RTX if
+ * there is no way to determine the return address of other frames.
+ * there is no way to determine the return address of other frames.
+ *
+ *
+ * ZipCPU --- I have no idea how we'd do this, so let's just return NULL_RTX.
+ * ZipCPU --- Our answer for the current frame is ... it depends.  If we can
 
+ * force the use of a frame in every debug context, we could compute this for
 
+ * COUNT != 0.  For now, we'll just look at the registers we save and return
 
+ * where the return address is in the current frame.  To do that, though, we
 
+ * need some help from C.
+ */
+ */
+#undef RETURN_ADDR_RTX
+#undef RETURN_ADDR_RTX
+#define        RETURN_ADDR_RTX(COUNT,FRAMEADDR)        NULL_RTX
+#define        RETURN_ADDR_RTX(COUNT,FRAMEADDR)        zip_return_addr_rtx(COUNT,FRAMEADDR)
+
+
+/* RETURN_ADDR_IN_PREVIOUS_FRAME ... Define this macro to nonzero value if the
+/* RETURN_ADDR_IN_PREVIOUS_FRAME ... Define this macro to nonzero value if the
+ * return address of a particular stack frame is accessed from the frame pointer
+ * return address of a particular stack frame is accessed from the frame pointer
+ * of the previous stack frame.  The zero default for this macro is suitable
+ * of the previous stack frame.  The zero default for this macro is suitable
+ * for most ports.
+ * for most ports.
Line 4579... Line 5536...
+ * ZipCPU --- While our incoming return address could theoretically be in any
+ * ZipCPU --- While our incoming return address could theoretically be in any
+ * register, our machine description file is going to place it into register
+ * register, our machine description file is going to place it into register
+ * R0, so that's what we return here.
+ * R0, so that's what we return here.
+ */
+ */
+#undef INCOMING_RETURN_ADDR_RTX
+#undef INCOMING_RETURN_ADDR_RTX
+#define        INCOMING_RETURN_ADDR_RTX        gen_rtx_REG(SImode, zip_R0)
+#define        INCOMING_RETURN_ADDR_RTX        gen_rtx_REG(SImode, zip_LR)
+
+
+
+
+/* DWARF_ALT_FRAME_RETURN_COLUMN
+/* DWARF_ALT_FRAME_RETURN_COLUMN
+ */
+ */
+
+
Line 4632... Line 5589...
+ * least 2 data registers, but should define 4 if their are enough free
+ * least 2 data registers, but should define 4 if their are enough free
+ * registers.
+ * registers.
+ *
+ *
+ * You must define this macro if you want to support call frame exception
+ * You must define this macro if you want to support call frame exception
+ * handling like that provided by DWARF 2.
+ * handling like that provided by DWARF 2.
 
+ *
 
+ * ZipCPU -- We copy much of our definition from Moxie.
+ */
+ */
+#define        EH_RETURN_DATA_REGNO(N) (((N<ZIP_FIRST_ARG_REGNO)||(N>ZIP_LAST_ARG_REGNO))?(N-1):INVALID_REGNUM)
+#define        EH_RETURN_DATA_REGNO(N) ((N<3)?(N+ZIP_FIRST_ARG_REGNO):INVALID_REGNUM)
+
+
+/* EH_RETURN_STACKADJ_RTX ... A C expression whose value is RTL representing
+/* EH_RETURN_STACKADJ_RTX ... A C expression whose value is RTL representing
+ * a location in which to store a stack adjustment to be applied before function
+ * a location in which to store a stack adjustment to be applied before function
+ * return.  This is used to unwind the stack to an exception handler's call
+ * return.  This is used to unwind the stack to an exception handler's call
+ * frame.  It will be assigned zero on code paths that return normally.
+ * frame.  It will be assigned zero on code paths that return normally.
Line 4662... Line 5621...
+ * EH_RETURN_STACKADJ_RTX will have already been assigned, so it may be used
+ * EH_RETURN_STACKADJ_RTX will have already been assigned, so it may be used
+ * to calculate the location of the target call frame.
+ * to calculate the location of the target call frame.
+ *
+ *
+ * If you want to support call frame exception handling, you must define either
+ * If you want to support call frame exception handling, you must define either
+ * this macro or the eh_return instruction pattern.
+ * this macro or the eh_return instruction pattern.
 
+ *
 
+ * ZipCPU --- We again copy from Moxie
+ */
+ */
+// #warning "I don't know what to do here."
+#define        EH_RETURN_HANDLER_RTX   \
 
+       gen_frame_mem(Pmode, plus_constant(Pmode, frame_pointer_rtx, UNITS_PER_WORD))
+
+
+/*
+/*
+ *
+ *
+ *
+ *
+ *
+ *
Line 4803... Line 5765...
+ * Do not define this macro unless there is no other way to get the return
+ * Do not define this macro unless there is no other way to get the return
+ * address from the stack.
+ * address from the stack.
+ *
+ *
+ * ZipCPU---we need this.
+ * ZipCPU---we need this.
+ */
+ */
+#define        RETURN_ADDRESS_REGNUM   zip_R0
+#define        RETURN_ADDRESS_REGNUM   zip_LR
+
+
+
+
+/* STATIC_CHAIN_REGNUM ... Register numbers used for passing a function's
+/* STATIC_CHAIN_REGNUM ... Register numbers used for passing a function's
+ * static chain pointer.  If register windows are used, the register number as
+ * static chain pointer.  If register windows are used, the register number as
+ * seen by the called function is STATIC_CHAIN_INCOMING_REGNUM, while the
+ * seen by the called function is STATIC_CHAIN_INCOMING_REGNUM, while the
+ * register number as seen by the calling function is STATIC_CHAIN_REGNUM.  If
+ * register number as seen by the calling function is STATIC_CHAIN_REGNUM.  If
+ * these register are the same, STATIC_CHAIN_INCOMING_REGNUM need not be
+ * these register are the same, STATIC_CHAIN_INCOMING_REGNUM need not be
+ * defined.
+ * defined.
+ *
+ *
+ * ZipCPU doesn't have register windows, so we don't need to define this.
+ * ZipCPU --- even without register windows, we still need to pick an
 
+ * (arbitrary) register to pass the pointer to the static chain in the case of
 
+ * nested functions.  Let's arbitrarily pick R5, and ... see how that works for
 
+ * us.
+ */
+ */
+// #warning "I have no reason to believe this will even work"
+#define        STATIC_CHAIN_REGNUM     zip_R5
+#define        STATIC_CHAIN_REGNUM     zip_GOT
 
+
+
+/* TARGET_STATIC_CHAIN ... This hook replaces the use of STATIC_CHAIN_REGNUM et
+/* TARGET_STATIC_CHAIN ... This hook replaces the use of STATIC_CHAIN_REGNUM et
+ * al for targets that may use different static chain locations for different
+ * al for targets that may use different static chain locations for different
+ * nested functions.  This may be required if the target has function attributes
+ * nested functions.  This may be required if the target has function attributes
+ * that affect the calling conventions of the function and those calling
+ * that affect the calling conventions of the function and those calling
+ * conventions use different static chain locations.
+ * conventions use different static chain locations.
+ *
+ *
+ * ZipCPU --- don't need this.
+ * ZipCPU --- don't need this.
+ */
+ */
+// #define     STATIC_CHAIN_REGNUM     zip_R11
+// #define     TARGET_STATIC_CHAIN     zip_R11
+
+
+
+
+/* DWARF_FRAME_REGISTERS ... This macro specifies  the maximum number of hard
+/* DWARF_FRAME_REGISTERS ... This macro specifies  the maximum number of hard
+ * registers that can be saved in a call frame.  This is used to size data
+ * registers that can be saved in a call frame.  This is used to size data
+ * structures used in DWARF2 exception handling.
+ * structures used in DWARF2 exception handling.
Line 5275... Line 6239...
+ * ZipCPU --- Default sounds good to me.
+ * ZipCPU --- Default sounds good to me.
+ */
+ */
+
+
+
+
+/* TARGET_SCALAR_MODE_SUPPORTED_P(MODE) ... Define this to return nonzero if
+/* TARGET_SCALAR_MODE_SUPPORTED_P(MODE) ... Define this to return nonzero if
+ * the port is prepared to handl instructions involving scalar mode MODE.  For
+ * the port is prepared to handle instructions involving scalar mode MODE.  For
+ * a scalar mode to be considered supported, all the basic arithmetic and
+ * a scalar mode to be considered supported, all the basic arithmetic and
+ * comparisons must work.
+ * comparisons must work.
+ *
+ *
+ * The default version of this hook returns true for any mode required to
+ * The default version of this hook returns true for any mode required to
+ * handle the basic C types (as defined by the port).  Included here are the
+ * handle the basic C types (as defined by the port).  Included here are the
+ * double-word arithmetic supported by the code in optabs.c.
+ * double-word arithmetic supported by the code in optabs.c.
 
+ *
 
+ * ZipCPU --- This controls whether a data type of the given mode can even be
 
+ * declared in C/C++.  Without support for such a mode, you can't even declare
 
+ * a data type of this type.  Hence, we should support SFmode and DFmode, even
 
+ * though the hardware *may* support SFmode, and it will *never* support DFmode.
+ */
+ */
+#undef TARGET_SCALAR_MODE_SUPPORTED_P
+#undef TARGET_SCALAR_MODE_SUPPORTED_P
+#define        TARGET_SCALAR_MODE_SUPPORTED_P  zip_scalar_mode_supported_p
+#define        TARGET_SCALAR_MODE_SUPPORTED_P  zip_scalar_mode_supported_p
+
+
+/* TARGET_VECTOR_MODE_SUPPORTED_P(MODE) ... Define this to return nonzero if the
+/* TARGET_VECTOR_MODE_SUPPORTED_P(MODE) ... Define this to return nonzero if the
Line 5297... Line 6266...
+#undef TARGET_VECTOR_MODE_SUPPORTED_P
+#undef TARGET_VECTOR_MODE_SUPPORTED_P
+#define        TARGET_VECTOR_MODE_SUPPORTED_P  hook_bool_mode_false
+#define        TARGET_VECTOR_MODE_SUPPORTED_P  hook_bool_mode_false
+
+
+/* TARGET_ARRAY_MODE_SUPPORTED_P(MODE, NELEMS) ... Return true if GCC should
+/* TARGET_ARRAY_MODE_SUPPORTED_P(MODE, NELEMS) ... Return true if GCC should
+ * try to use a scalar mode to store an array of NELEMS elements, given that
+ * try to use a scalar mode to store an array of NELEMS elements, given that
+ * each element has mode MODE.  Returning true here overrides the usual MAX_FIXED_MODE limit and allows GCC to use any defined integer mode.
+ * each element has mode MODE.  Returning true here overrides the usual
 
+ * MAX_FIXED_MODE limit and allows GCC to use any defined integer mode.
+ *
+ *
+ * ZipCPU---Sounds good.
+ * ZipCPU---Sounds good.
+ */
+ */
+// #undef      TARGET_ARRAY_MODE_SUPPORTED_P
+// #undef      TARGET_ARRAY_MODE_SUPPORTED_P
+// #define     TARGET_ARRAY_MODE_SUPPORTED_P   zip_array_mode_supported_p
+// #define     TARGET_ARRAY_MODE_SUPPORTED_P   zip_array_mode_supported_p
Line 5498... Line 6468...
+ */
+ */
+
+
+/* TRAMPOLINE_SIZE ... A C expression for the size (in bytes) of the trampoline
+/* TRAMPOLINE_SIZE ... A C expression for the size (in bytes) of the trampoline
+ * as an integer.
+ * as an integer.
+ *
+ *
+ * ZipCPU--it's three instructions, or 96 bits.  However, 32-bits is our minimal
+ * ZipCPU--it's three instructions, or 96 bits: BREV, LDILO, and JMP
+ * addressible unit, so what size do we offer here?  We'll stick with the number
 
+ * of bytes, but we may need to change this later.
 
+ *
+ *
+ */
+ */
+// #warning "May need to redefine trampoline_size in words, not bytes"
+// #warning "May need to redefine trampoline_size in words, not bytes"
+#undef TRAMPOLINE_SIZE
+#undef TRAMPOLINE_SIZE
+#define        TRAMPOLINE_SIZE 3
+#define        TRAMPOLINE_SIZE 3*UNITS_PER_WORD
+
+
+/* TRAMPOLINE_ALIGNMENT ... alignment required for trampolines, in bits.
+/* TRAMPOLINE_ALIGNMENT ... alignment required for trampolines, in bits.
+ *
+ *
+ * Well that's well known in ZipCPU --- 32-bits.
+ * Well that's well known in ZipCPU --- 32-bits.
+ */
+ */
+#undef TRAMPOLINE_ALIGNMENT
+#undef TRAMPOLINE_ALIGNMENT
+#define        TRAMPOLINE_ALIGNMENT    32
+#define        TRAMPOLINE_ALIGNMENT    UNITS_PER_WORD
+
+
+/* void TARGET_TRAMPOLINE_INIT(RTX,TREE,RTX CH) ... This hook is called to
+/* void TARGET_TRAMPOLINE_INIT(RTX,TREE,RTX CH) ... This hook is called to
+ * initialize a trampoline.  m_tramp is an RTX for the memory block for the
+ * initialize a trampoline.  m_tramp is an RTX for the memory block for the
+ * trampoline; TREE is the FUNCTION_DECL for the nested fucntion;  CH is an
+ * trampoline; TREE is the FUNCTION_DECL for the nested fucntion;  CH is an
+ * rtx for the static chain value that should be passed to the function when
+ * rtx for the static chain value that should be passed to the function when
Line 5544... Line 6512...
+ * macro would typically be a series of asm statements.   Both BEG and END are
+ * macro would typically be a series of asm statements.   Both BEG and END are
+ * pointer expressions.
+ * pointer expressions.
+ *
+ *
+ * ZipCPU --- Ouch!  We have no way to do this (yet)!
+ * ZipCPU --- Ouch!  We have no way to do this (yet)!
+ */
+ */
 
+#define        CLEAR_INSN_CACHE(BEG,END)       gcc_assert(0);
+
+
+/* TRANSFER_FROM_TRAMPOLINE ... Define this macro is trampolines need a special
+/* TRANSFER_FROM_TRAMPOLINE ... Define this macro is trampolines need a special
+ * subroutine to do their work.  The macro should expand to a series of asm
+ * subroutine to do their work.  The macro should expand to a series of asm
+ * statements which will be compiled with GCC.  They go in a library function
+ * statements which will be compiled with GCC.  They go in a library function
+ * named __transfer_from_trampoline.
+ * named __transfer_from_trampoline.
Line 5805... Line 6774...
+/* TARGET_MIN_ANCHOR_OFFSET ... The minimum offset that should be applied to
+/* TARGET_MIN_ANCHOR_OFFSET ... The minimum offset that should be applied to
+ * a section anchor.  On most targets, it should be the smallest offset that
+ * a section anchor.  On most targets, it should be the smallest offset that
+ * can be applied to a base register while still giving a legitimate address for
+ * can be applied to a base register while still giving a legitimate address for
+ * every mode.  The default value is 0.
+ * every mode.  The default value is 0.
+ *
+ *
+ * On the Zip CPU, this is the minimum operand B offset to a LOD or STO
+ * On the Zip CPU, this is the minimum operand B offset to a LW or SW
+ * operation, which would be a signed 14 bit number.
+ * operation, which would be a signed 14 bit number.
+ */
+ */
+#undef TARGET_MIN_ANCHOR_OFFSET
+#undef TARGET_MIN_ANCHOR_OFFSET
+#define TARGET_MIN_ANCHOR_OFFSET       zip_min_anchor_offset
+#define TARGET_MIN_ANCHOR_OFFSET       zip_min_anchor_offset
+
+
Line 5828... Line 6797...
+ * If ASM_OUTPUT_DEF is available, the hook's default definition uses it to
+ * If ASM_OUTPUT_DEF is available, the hook's default definition uses it to
+ * define the symbol as '. + SYMBOL_REF_BLOCK_OFFSET(RTL)'.  If ASM_OUTPUT_DEF
+ * define the symbol as '. + SYMBOL_REF_BLOCK_OFFSET(RTL)'.  If ASM_OUTPUT_DEF
+ * is not available, the hook's default definition is NULL, which disables the
+ * is not available, the hook's default definition is NULL, which disables the
+ * use of section anchors altogether.
+ * use of section anchors altogether.
+ *
+ *
+ * Section anchors will be very valuable in Zip CPU assembly, therefore we
+ * Section anchors would be very valuable in Zip CPU assembly, therefore we
+ * must define this hook.
+ * must define this hook.  However ... no one else seems to ever define these
 
+ * hooks, so I really dont have much of an example to work with
+ */
+ */
 
+// #warning "Come back to this"
+// #undef      TARGET_ASM_OUTPUT_ANCHOR
+// #undef      TARGET_ASM_OUTPUT_ANCHOR
+// #define     TARGET_ASM_OUTPUT_ANCHOR        zip_asm_output_anchor
+// #define     TARGET_ASM_OUTPUT_ANCHOR        zip_asm_output_anchor
+
+
+/* TARGET_USE_ANCHORS_FOR_SYMBOL_P(RTX) ... Return true if GCC should attempt
+/* TARGET_USE_ANCHORS_FOR_SYMBOL_P(RTX) ... Return true if GCC should attempt
+ * to use anchors to access SYMBOL_REF X.  You can assume SYMBOL_REF_HAS_BLOCK_INFO_P(X) and !SYMBOL_REF_ANCHOR_P(X).
+ * to use anchors to access SYMBOL_REF X.  You can assume
 
+ * SYMBOL_REF_HAS_BLOCK_INFO_P(X) and !SYMBOL_REF_ANCHOR_P(X).
+ *
+ *
+ * The default version is correct for most targets, but you might need to intercept this hook to handle things like target specific attributes or target-specific sections.
+ * The default version is correct for most targets, but you might need to
 
+ * intercept this hook to handle things like target specific attributes or
 
+ * target-specific sections.
+ *
+ *
+ * Not knowing anything more, we'll leave the default as is for the Zip CPU.
+ * Not knowing anything more, we'll leave the default as is for the Zip CPU.
+ */
+ */
+// #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
+// #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
+// #define TARGET_USE_ANCHORS_FOR_SYMBOL_P     zip_use_anchors_for_symbol_p
+// #define TARGET_USE_ANCHORS_FOR_SYMBOL_P     zip_use_anchors_for_symbol_p
Line 6072... Line 7046...
+ *
+ *
+ * On the Zip CPU, constant function addresses--especially relative ones,
+ * On the Zip CPU, constant function addresses--especially relative ones,
+ * can be optimized into a single cycle delay.  Register jumps will always
+ * can be optimized into a single cycle delay.  Register jumps will always
+ * stall the whole (5-stage) pipeline.
+ * stall the whole (5-stage) pipeline.
+ */
+ */
+#define        NO_FUNCTION_CSE
+#define        NO_FUNCTION_CSE true
+
+
+/* TARGET_RTX_COSTS(X,CODE,OUTER,OPNO,TOTAL,SPD) ... This target hook describes
+/* TARGET_RTX_COSTS(X,CODE,OUTER,OPNO,TOTAL,SPD) ... This target hook describes
+ * the relative costs of RTL expressions.
+ * the relative costs of RTL expressions.
+ *
+ *
+ * The cost may depend on the precise form of the expression, which is avaialble
+ * The cost may depend on the precise form of the expression, which is avaialble
Line 6139... Line 7113...
+#define        PIC_OFFSET_TABLE_REG_CALL_CLOBBERED     0
+#define        PIC_OFFSET_TABLE_REG_CALL_CLOBBERED     0
+// #define LEGITIMATE_PIC_OPERAND_P(X) should evaluate to X(GOT) only
+// #define LEGITIMATE_PIC_OPERAND_P(X) should evaluate to X(GOT) only
+
+
+/* 17.20 Defining the Output Assembler Language */
+/* 17.20 Defining the Output Assembler Language */
+
+
+/* 17.20.4 Output of Data */
+/* 17.20.2 Output of Data */
+
+
+#undef TARGET_ASM_ALIGNED_HI_OP
 
+#undef TARGET_ASM_ALIGNED_SI_OP
 
+#define        TARGET_ASM_UNALIGNED_HI_OP      "\t.byte\t"
 
+#define        TARGET_ASM_UNALIGNED_SI_OP      "\t.byte\t"
 
+/* These hooks (above) specify assembly directives for creating certain kinds
+/* These hooks (above) specify assembly directives for creating certain kinds
+ * of integer objects.  The TARGET_ASM_BYTE_OP directive creates a byte-sized
+ * of integer objects.  The TARGET_ASM_BYTE_OP directive creates a byte-sized
+ * object.  The TARGET_ASMALIGNED_HI_OP one creates an aligned two-byte object
+ * object.  The TARGET_ASMALIGNED_HI_OP one creates an aligned two-byte object
+ * and so on.  Any of the hookd may be NULL, indicating that no suitable
+ * and so on.  Any of the hookd may be NULL, indicating that no suitable
+ * directive is available.
+ * directive is available.
Line 6156... Line 7126...
+ * The compiler will print these strings at the start of a new line, followed
+ * The compiler will print these strings at the start of a new line, followed
+ * immediately by the object's initial value.  In most cases, the string should
+ * immediately by the object's initial value.  In most cases, the string should
+ * contain a tab, a pseudo op, and then another tab.
+ * contain a tab, a pseudo op, and then another tab.
+ */
+ */
+
+
 
+#undef TARGET_ASM_ALIGNED_HI_OP
 
+#undef TARGET_ASM_ALIGNED_SI_OP
 
+// #undef      TARGET_ASM_ALIGNED_DI_OP
 
+#define        TARGET_ASM_ALIGNED_HI_OP        ".short"
 
+// The assembler is set up to call a 4-byte integer a long.  This definition of
 
+// a long isn't consistent with the compilers definition.  For this reason,
 
+// the ZipCPU backend for the GNU Assembler defines a long as a 64-bit number,
 
+// and an int as a 32-bit number.
 
+#define        TARGET_ASM_ALIGNED_SI_OP        ".int"
 
+// #define     TARGET_ASM_ALIGNED_DI_OP        ".long"
 
+
 
+
+/* 17.20.4 Output and Generation of Labels */
+/* 17.20.4 Output and Generation of Labels */
+
+
+/* ASM_OUTPUT_LABEL
+/* ASM_OUTPUT_LABEL
+ * ... A default definition of this macro is provided which is correct for
+ * ... A default definition of this macro is provided which is correct for
+ * most systems.
+ * most systems.
Line 6334... Line 7316...
+ */
+ */
+
+
+/* TARGET_ASM_LABEL_ALIGN */
+/* TARGET_ASM_LABEL_ALIGN */
+/* Assembler Commands for Alignment */
+/* Assembler Commands for Alignment */
+#define        ASM_OUTPUT_ALIGN(STREAM,POWER)  \
+#define        ASM_OUTPUT_ALIGN(STREAM,POWER)  \
+       { int pwr = POWER; fprintf(STREAM, "\t.p2align %d\n", (pwr<2)?2:pwr); }
+       do { fprintf(STREAM, "\t.align\t%d\n", POWER); } while (0)
+
 
+
+
+
+
+/* 17.21 Controlling Debugging Information Format */
+/* 17.21 Controlling Debugging Information Format */
+/* 17.22 Cross Compilation and Floating Point */
+/* 17.22 Cross Compilation and Floating Point */
+
+
Line 6397... Line 7378...
+ */
+ */
+#define        HAS_LONG_COND_BRANCH true
+#define        HAS_LONG_COND_BRANCH true
+
+
+/* HAS_LONG_UNCOND_BRANCH ... Define this boolean macro to indicate whether
+/* HAS_LONG_UNCOND_BRANCH ... Define this boolean macro to indicate whether
+ * or not your architecture has unconditional branches that can span all of
+ * or not your architecture has unconditional branches that can span all of
+ * memory.  (ZipCPU does ... via the LOD (PC),PC instruction.)  It is used in
+ * memory.  (ZipCPU does ... via the LW (PC),PC instruction.)  It is used in
+ * conjunction with an optimization that partitions hot and cold basic blocks
+ * conjunction with an optimization that partitions hot and cold basic blocks
+ * into separate sections of the executable.  If this macro is set to false,
+ * into separate sections of the executable.  If this macro is set to false,
+ * gcc will convert any unconditional branches that attempt to cross between
+ * gcc will convert any unconditional branches that attempt to cross between
+ * sections into indirect jumps.
+ * sections into indirect jumps.
+ *
+ *
+ * ZipCPU has the LOD (PC),PC instruction which can be used to implement a long
+ * ZipCPU has the LW (PC),PC instruction which can be used to implement a long
+ * jump.
+ * jump.
+ */
+ */
+#define        HAS_LONG_UNCOND_BRANCH  true
+#define        HAS_LONG_UNCOND_BRANCH  true
+
+
+/* CASE_VECTOR_MODE ... An alias for a machine mode name.  This is the machine
+/* CASE_VECTOR_MODE ... An alias for a machine mode name.  This is the machine
+ * mode that eleemnts of a jump-table should have.
+ * mode that elements of a jump-table should have.
+ *
+ *
+ */
+ */
+#define        CASE_VECTOR_MODE        SImode
+#define        CASE_VECTOR_MODE        SImode
+
+
+/* CASE_VECTOR_SHORTEN_MODE(MIN,MAX,BODY) ... Optional: return the preferred
+/* CASE_VECTOR_SHORTEN_MODE(MIN,MAX,BODY) ... Optional: return the preferred
Line 6445... Line 7426...
+/* WORD_REGISTER_OPERATIONS ... Define this macro to 1 if operations between