| Line 1... |
Line 1... |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/config.sub gcc-5.3.0-zip/config.sub
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/config.sub gcc-6.2.0-zip/config.sub
|
--- gcc-5.3.0-original/config.sub 2015-01-02 04:30:21.000000000 -0500
|
--- gcc-6.2.0/config.sub 2015-12-31 16:13:28.000000000 -0500
|
+++ gcc-5.3.0-zip/config.sub 2016-01-30 12:27:56.023073747 -0500
|
+++ gcc-6.2.0-zip/config.sub 2017-01-11 11:07:21.116065311 -0500
|
@@ -316,7 +316,7 @@
|
@@ -355,6 +355,14 @@
|
| visium \
|
xscaleel)
|
| we32k \
|
basic_machine=armel-unknown
|
| x86 | xc16x | xstormy16 | xtensa \
|
|
- | z8k | z80)
|
|
+ | z8k | z80 | zip)
|
|
basic_machine=$basic_machine-unknown
|
|
;;
|
;;
|
c54x)
|
+ zip-*-linux*)
|
@@ -1547,6 +1547,9 @@
|
+ basic_machine=zip
|
# system, and we'll never get to this point.
|
+ os=-linux
|
|
|
case $basic_machine in
|
|
+ zip-*)
|
|
+ os=-elf
|
|
+ ;;
|
+ ;;
|
score-*)
|
+ zip*)
|
os=-elf
|
+ basic_machine=zip-unknown
|
|
+ os=-none
|
|
+ ;;
|
|
|
|
# We use `pc' rather than `unknown'
|
|
# because (1) that's what they normally are, and
|
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/configure gcc-6.2.0-zip/configure
|
|
--- gcc-6.2.0/configure 2016-03-17 18:54:19.000000000 -0400
|
|
+++ gcc-6.2.0-zip/configure 2017-02-06 21:54:22.244807700 -0500
|
|
@@ -3548,6 +3548,44 @@
|
|
ft32-*-*)
|
|
noconfigdirs="$noconfigdirs ${libgcj}"
|
|
;;
|
|
+ zip*)
|
|
+ noconfigdirs="$noconfigdirs ${libgcj}"
|
|
+ noconfigdirs="$noconfigdirs target-boehm-gc"
|
|
+ noconfigdirs="$noconfigdirs target-libgfortran"
|
|
+ # noconfigdirs="$noconfigdirs target-libsanitizer"
|
|
+ # noconfigdirs="$noconfigdirs target-libada"
|
|
+ # noconfigdirs="$noconfigdirs target-libatomic"
|
|
+ # noconfigdirs="$noconfigdirs target-libcilkrts"
|
|
+ # noconfigdirs="$noconfigdirs target-libitm"
|
|
+ # noconfigdirs="$noconfigdirs target-libquadmath"
|
|
+ # noconfigdirs="$noconfigdirs target-libstdc++-v3"
|
|
+ # noconfigdirs="$noconfigdirs target-libssp"
|
|
+ # noconfigdirs="$noconfigdirs target-libgo"
|
|
+ # noconfigdirs="$noconfigdirs target-libgomp"
|
|
+ # noconfigdirs="$noconfigdirs target-libvtv"
|
|
+ # noconfigdirs="$noconfigdirs target-libobjc"
|
|
+ # target-libgcc
|
|
+ # target-liboffloadmic
|
|
+ # target-libmpx # Only gets enabled by request
|
|
+ # target-libbacktrace
|
|
+ # ${libgcj}
|
|
+ # target-boehm-gc
|
|
+ # target-libada
|
|
+ # target-libatomic
|
|
+ # target-libcilkrts
|
|
+ # target-libgfortran
|
|
+ # target-libgo
|
|
+ # target-libgomp
|
|
+ # target-libitm
|
|
+ # target-libobjc
|
|
+ # target-libquadmath
|
|
+ # target-libsanitizer
|
|
+ # target-libstdc++-v3
|
|
+ # target-libssp
|
|
+ # target-libvtv
|
|
+ # target-libgloss
|
|
+ # target-newlib
|
|
+ ;;
|
|
*-*-lynxos*)
|
|
noconfigdirs="$noconfigdirs ${libgcj}"
|
;;
|
;;
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/configure gcc-5.3.0-zip/configure
|
@@ -3575,6 +3613,9 @@
|
--- gcc-5.3.0-original/configure 2015-05-03 13:29:57.000000000 -0400
|
*-*-aix*)
|
+++ gcc-5.3.0-zip/configure 2016-01-30 16:19:48.264867231 -0500
|
noconfigdirs="$noconfigdirs target-libgo"
|
@@ -3927,6 +3927,8 @@
|
;;
|
|
+ zip*)
|
|
+ noconfigdirs="$noconfigdirs target-libgo"
|
|
+ ;;
|
|
esac
|
|
fi
|
|
|
|
@@ -3971,6 +4012,9 @@
|
vax-*-*)
|
vax-*-*)
|
noconfigdirs="$noconfigdirs target-newlib target-libgloss"
|
noconfigdirs="$noconfigdirs target-newlib target-libgloss"
|
;;
|
;;
|
+ zip*)
|
+ zip*)
|
+ noconfigdirs="$noconfigdirs target-libffi target-boehm-gc gdb gprof"
|
+ noconfigdirs="$noconfigdirs target-libffi target-boehm-gc gdb gprof"
|
|
+ ;;
|
esac
|
esac
|
|
|
# If we aren't building newlib, then don't build libgloss, since libgloss
|
# If we aren't building newlib, then don't build libgloss, since libgloss
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/configure.ac gcc-5.3.0-zip/configure.ac
|
@@ -6785,16 +6829,16 @@
|
--- gcc-5.3.0-original/configure.ac 2015-05-03 13:29:57.000000000 -0400
|
# CFLAGS_FOR_TARGET and CXXFLAGS_FOR_TARGET.
|
+++ gcc-5.3.0-zip/configure.ac 2016-02-12 10:47:23.847194843 -0500
|
if test "x$CFLAGS_FOR_TARGET" = x; then
|
@@ -1274,6 +1274,10 @@
|
if test "x${is_cross_compiler}" = xyes; then
|
|
- CFLAGS_FOR_TARGET="-g -O2"
|
|
+ CFLAGS_FOR_TARGET="-O3"
|
|
else
|
|
CFLAGS_FOR_TARGET=$CFLAGS
|
|
case " $CFLAGS " in
|
|
- *" -O2 "*) ;;
|
|
- *) CFLAGS_FOR_TARGET="-O2 $CFLAGS_FOR_TARGET" ;;
|
|
+ *" -O3 "*) ;;
|
|
+ *) CFLAGS_FOR_TARGET="-O3 $CFLAGS_FOR_TARGET" ;;
|
|
esac
|
|
case " $CFLAGS " in
|
|
*" -g "* | *" -g3 "*) ;;
|
|
- *) CFLAGS_FOR_TARGET="-g $CFLAGS_FOR_TARGET" ;;
|
|
+ *) CFLAGS_FOR_TARGET="$CFLAGS_FOR_TARGET" ;;
|
|
esac
|
|
fi
|
|
fi
|
|
@@ -6802,16 +6846,16 @@
|
|
|
|
if test "x$CXXFLAGS_FOR_TARGET" = x; then
|
|
if test "x${is_cross_compiler}" = xyes; then
|
|
- CXXFLAGS_FOR_TARGET="-g -O2"
|
|
+ CXXFLAGS_FOR_TARGET="-O3"
|
|
else
|
|
CXXFLAGS_FOR_TARGET=$CXXFLAGS
|
|
case " $CXXFLAGS " in
|
|
- *" -O2 "*) ;;
|
|
- *) CXXFLAGS_FOR_TARGET="-O2 $CXXFLAGS_FOR_TARGET" ;;
|
|
+ *" -O3 "*) ;;
|
|
+ *) CXXFLAGS_FOR_TARGET="-O3 $CXXFLAGS_FOR_TARGET" ;;
|
|
esac
|
|
case " $CXXFLAGS " in
|
|
*" -g "* | *" -g3 "*) ;;
|
|
- *) CXXFLAGS_FOR_TARGET="-g $CXXFLAGS_FOR_TARGET" ;;
|
|
+ *) CXXFLAGS_FOR_TARGET="$CXXFLAGS_FOR_TARGET" ;;
|
|
esac
|
|
fi
|
|
fi
|
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/configure.ac gcc-6.2.0-zip/configure.ac
|
|
--- gcc-6.2.0/configure.ac 2016-03-17 18:54:19.000000000 -0400
|
|
+++ gcc-6.2.0-zip/configure.ac 2017-01-10 12:43:23.819301273 -0500
|
|
@@ -884,6 +884,9 @@
|
|
ft32-*-*)
|
|
noconfigdirs="$noconfigdirs ${libgcj}"
|
|
;;
|
|
+ zip*)
|
|
+ noconfigdirs="$noconfigdirs ${libgcj}"
|
|
+ ;;
|
|
*-*-lynxos*)
|
|
noconfigdirs="$noconfigdirs ${libgcj}"
|
|
;;
|
|
@@ -911,6 +914,9 @@
|
|
*-*-aix*)
|
|
noconfigdirs="$noconfigdirs target-libgo"
|
|
;;
|
|
+ zip*)
|
|
+ noconfigdirs="$noconfigdirs target-libgo"
|
|
+ ;;
|
|
esac
|
|
fi
|
|
|
|
@@ -1307,6 +1313,10 @@
|
vax-*-*)
|
vax-*-*)
|
noconfigdirs="$noconfigdirs target-newlib target-libgloss"
|
noconfigdirs="$noconfigdirs target-newlib target-libgloss"
|
;;
|
;;
|
+ zip*)
|
+ zip*)
|
+ noconfigdirs="$noconfigdirs target-libffi target-boehm-gc gdb gprof"
|
+ noconfigdirs="$noconfigdirs target-libffi target-boehm-gc gdb gprof ${libgcj}"
|
+ unsupported_languages="$unsupported_languages fortran java"
|
+ unsupported_languages="$unsupported_languages fortran"
|
+ ;;
|
+ ;;
|
esac
|
esac
|
|
|
# If we aren't building newlib, then don't build libgloss, since libgloss
|
# If we aren't building newlib, then don't build libgloss, since libgloss
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/cfgexpand.c gcc-5.3.0-zip/gcc/cfgexpand.c
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/cfgexpand.c gcc-6.2.0-zip/gcc/cfgexpand.c
|
--- gcc-5.3.0-original/gcc/cfgexpand.c 2015-07-23 06:39:26.000000000 -0400
|
--- gcc-6.2.0/gcc/cfgexpand.c 2016-04-27 08:23:50.000000000 -0400
|
+++ gcc-5.3.0-zip/gcc/cfgexpand.c 2016-04-01 06:40:17.288326711 -0400
|
+++ gcc-6.2.0-zip/gcc/cfgexpand.c 2016-12-31 16:38:36.195534819 -0500
|
@@ -108,6 +108,14 @@
|
@@ -74,6 +74,15 @@
|
#include "tree-chkp.h"
|
#include "tree-chkp.h"
|
#include "rtl-chkp.h"
|
#include "rtl-chkp.h"
|
|
|
|
+
|
+#ifdef DO_ZIP_DEBUGS
|
+#ifdef DO_ZIP_DEBUGS
|
+#include <stdio.h>
|
+#include <stdio.h>
|
+#define ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
|
+#define ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s;%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
|
+extern void zip_debug_rtx(const_rtx);
|
+extern void zip_debug_rtx(const_rtx);
|
+#else
|
+#else
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
+#endif
|
+#endif
|
+
|
+
|
/* Some systems use __main in a way incompatible with its use in gcc, in these
|
/* Some systems use __main in a way incompatible with its use in gcc, in these
|
cases use the macros NAME__MAIN to give a quoted symbol and SYMBOL__MAIN to
|
cases use the macros NAME__MAIN to give a quoted symbol and SYMBOL__MAIN to
|
give the same symbol without quotes for an alternative entry point. You
|
give the same symbol without quotes for an alternative entry point. You
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/cgraphbuild.c gcc-5.3.0-zip/gcc/cgraphbuild.c
|
@@ -1172,7 +1181,7 @@
|
--- gcc-5.3.0-original/gcc/cgraphbuild.c 2015-01-09 15:18:42.000000000 -0500
|
base_align = crtl->max_used_stack_slot_alignment;
|
+++ gcc-5.3.0-zip/gcc/cgraphbuild.c 2016-03-24 22:13:24.815287808 -0400
|
else
|
@@ -62,6 +62,13 @@
|
base_align = MAX (crtl->max_used_stack_slot_alignment,
|
#include "ipa-prop.h"
|
- GET_MODE_ALIGNMENT (SImode)
|
#include "ipa-inline.h"
|
+ GET_MODE_ALIGNMENT (word_mode)
|
|
<< ASAN_SHADOW_SHIFT);
|
|
}
|
|
else
|
|
@@ -2225,7 +2234,7 @@
|
|
data.asan_vec.safe_push (offset);
|
|
/* Leave space for alignment if STRICT_ALIGNMENT. */
|
|
if (STRICT_ALIGNMENT)
|
|
- alloc_stack_frame_space ((GET_MODE_ALIGNMENT (SImode)
|
|
+ alloc_stack_frame_space ((GET_MODE_ALIGNMENT (word_mode)
|
|
<< ASAN_SHADOW_SHIFT)
|
|
/ BITS_PER_UNIT, 1);
|
|
|
|
@@ -5745,7 +5754,7 @@
|
|
&& (last = get_last_insn ())
|
|
&& JUMP_P (last))
|
|
{
|
|
- rtx dummy = gen_reg_rtx (SImode);
|
|
+ rtx dummy = gen_reg_rtx (word_mode);
|
|
emit_insn_after_noloc (gen_move_insn (dummy, dummy), last, NULL);
|
|
}
|
|
|
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/cgraphbuild.c gcc-6.2.0-zip/gcc/cgraphbuild.c
|
|
--- gcc-6.2.0/gcc/cgraphbuild.c 2016-01-04 09:30:50.000000000 -0500
|
|
+++ gcc-6.2.0-zip/gcc/cgraphbuild.c 2016-12-31 16:39:44.963107994 -0500
|
|
@@ -32,6 +32,15 @@
|
|
#include "ipa-utils.h"
|
|
#include "except.h"
|
|
|
|
+
|
+#ifdef DO_ZIP_DEBUGS
|
+#ifdef DO_ZIP_DEBUGS
|
|
+#include <stdio.h>
|
|
+#define ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s;%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
|
+extern void zip_debug_rtx(const_rtx);
|
+extern void zip_debug_rtx(const_rtx);
|
+#define ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
|
|
+#else
|
+#else
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
+#endif
|
+#endif
|
+
|
+
|
/* Context of record_reference. */
|
/* Context of record_reference. */
|
struct record_reference_ctx
|
struct record_reference_ctx
|
{
|
{
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/common/config/zip/zip-common.c gcc-5.3.0-zip/gcc/common/config/zip/zip-common.c
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/combine.c gcc-6.2.0-zip/gcc/combine.c
|
--- gcc-5.3.0-original/gcc/common/config/zip/zip-common.c 1969-12-31 19:00:00.000000000 -0500
|
--- gcc-6.2.0/gcc/combine.c 2016-08-08 06:06:15.000000000 -0400
|
+++ gcc-5.3.0-zip/gcc/common/config/zip/zip-common.c 2016-02-14 00:54:31.821055716 -0500
|
+++ gcc-6.2.0-zip/gcc/combine.c 2017-02-03 09:25:19.676720321 -0500
|
|
@@ -103,6 +103,15 @@
|
|
#include "rtl-iter.h"
|
|
#include "print-rtl.h"
|
|
|
|
+#define DO_ZIP_DEBUGS
|
|
+#ifdef DO_ZIP_DEBUGS
|
|
+#include <stdio.h>
|
|
+#define ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
|
|
+extern void zip_debug_rtx(const_rtx);
|
|
+#else
|
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
|
+#endif
|
|
+
|
|
#ifndef LOAD_EXTEND_OP
|
|
#define LOAD_EXTEND_OP(M) UNKNOWN
|
|
#endif
|
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/common/config/zip/zip-common.c gcc-6.2.0-zip/gcc/common/config/zip/zip-common.c
|
|
--- gcc-6.2.0/gcc/common/config/zip/zip-common.c 1969-12-31 19:00:00.000000000 -0500
|
|
+++ gcc-6.2.0-zip/gcc/common/config/zip/zip-common.c 2017-01-11 09:41:34.483106099 -0500
|
@@ -0,0 +1,52 @@
|
@@ -0,0 +1,52 @@
|
+////////////////////////////////////////////////////////////////////////////////
|
+////////////////////////////////////////////////////////////////////////////////
|
+//
|
+//
|
+// Filename: common/config/zip/zip-common.c
|
+// Filename: common/config/zip/zip-common.c
|
+//
|
+//
|
| Line 96... |
Line 259... |
+// Creator: Dan Gisselquist, Ph.D.
|
+// Creator: Dan Gisselquist, Ph.D.
|
+// Gisselquist Technology, LLC
|
+// Gisselquist Technology, LLC
|
+//
|
+//
|
+////////////////////////////////////////////////////////////////////////////////
|
+////////////////////////////////////////////////////////////////////////////////
|
+//
|
+//
|
+// Copyright (C) 2016, Gisselquist Technology, LLC
|
+// Copyright (C) 2016-2017, Gisselquist Technology, LLC
|
+//
|
+//
|
+// This program is free software (firmware): you can redistribute it and/or
|
+// This program is free software (firmware): you can redistribute it and/or
|
+// modify it under the terms of the GNU General Public License as published
|
+// modify it under the terms of the GNU General Public License as published
|
+// by the Free Software Foundation, either version 3 of the License, or (at
|
+// by the Free Software Foundation, either version 3 of the License, or (at
|
+// your option) any later version.
|
+// your option) any later version.
|
| Line 135... |
Line 298... |
+
|
+
|
+#undef TARGET_OPTION_OPTIMIZATION_TABLE
|
+#undef TARGET_OPTION_OPTIMIZATION_TABLE
|
+#define TARGET_OPTION_OPTIMIZATION_TABLE zip_option_optimization_table
|
+#define TARGET_OPTION_OPTIMIZATION_TABLE zip_option_optimization_table
|
+
|
+
|
+struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
|
+struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h gcc-5.3.0-zip/gcc/config/aarch64/aarch64-linux.h
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/genzipops.c gcc-6.2.0-zip/gcc/config/zip/genzipops.c
|
--- gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h 2016-11-28 18:14:19.382586425 -0500
|
--- gcc-6.2.0/gcc/config/zip/genzipops.c 1969-12-31 19:00:00.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/config/aarch64/aarch64-linux.h 2015-07-24 12:00:26.000000000 -0400
|
+++ gcc-6.2.0-zip/gcc/config/zip/genzipops.c 2017-03-07 12:03:59.062584503 -0500
|
@@ -21,7 +21,7 @@
|
@@ -0,0 +1,444 @@
|
#ifndef GCC_AARCH64_LINUX_H
|
|
#define GCC_AARCH64_LINUX_H
|
|
|
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
|
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
|
|
|
|
#undef ASAN_CC1_SPEC
|
|
#define ASAN_CC1_SPEC "%{%:sanitize(address):-funwind-tables}"
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/alpha/linux-elf.h gcc-5.3.0-zip/gcc/config/alpha/linux-elf.h
|
|
--- gcc-5.3.0-original/gcc/config/alpha/linux-elf.h 2016-11-28 18:14:19.382586425 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/alpha/linux-elf.h 2015-01-05 07:33:28.000000000 -0500
|
|
@@ -23,8 +23,8 @@
|
|
#define EXTRA_SPECS \
|
|
{ "elf_dynamic_linker", ELF_DYNAMIC_LINKER },
|
|
|
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2"
|
|
-#define UCLIBC_DYNAMIC_LINKER "/tools/lib/ld-uClibc.so.0"
|
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
|
|
+#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
|
|
#if DEFAULT_LIBC == LIBC_UCLIBC
|
|
#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
|
|
#elif DEFAULT_LIBC == LIBC_GLIBC
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/arm/linux-eabi.h gcc-5.3.0-zip/gcc/config/arm/linux-eabi.h
|
|
--- gcc-5.3.0-original/gcc/config/arm/linux-eabi.h 2016-11-28 18:14:19.382586425 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/arm/linux-eabi.h 2015-01-05 07:33:28.000000000 -0500
|
|
@@ -68,8 +68,8 @@
|
|
GLIBC_DYNAMIC_LINKER_DEFAULT and TARGET_DEFAULT_FLOAT_ABI. */
|
|
|
|
#undef GLIBC_DYNAMIC_LINKER
|
|
-#define GLIBC_DYNAMIC_LINKER_SOFT_FLOAT "/tools/lib/ld-linux.so.3"
|
|
-#define GLIBC_DYNAMIC_LINKER_HARD_FLOAT "/tools/lib/ld-linux-armhf.so.3"
|
|
+#define GLIBC_DYNAMIC_LINKER_SOFT_FLOAT "/lib/ld-linux.so.3"
|
|
+#define GLIBC_DYNAMIC_LINKER_HARD_FLOAT "/lib/ld-linux-armhf.so.3"
|
|
#define GLIBC_DYNAMIC_LINKER_DEFAULT GLIBC_DYNAMIC_LINKER_SOFT_FLOAT
|
|
|
|
#define GLIBC_DYNAMIC_LINKER \
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/arm/linux-elf.h gcc-5.3.0-zip/gcc/config/arm/linux-elf.h
|
|
--- gcc-5.3.0-original/gcc/config/arm/linux-elf.h 2016-11-28 18:14:19.382586425 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/arm/linux-elf.h 2015-06-23 05:26:54.000000000 -0400
|
|
@@ -62,7 +62,7 @@
|
|
|
|
#define LIBGCC_SPEC "%{mfloat-abi=soft*:-lfloat} -lgcc"
|
|
|
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2"
|
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
|
|
|
|
#define LINUX_TARGET_LINK_SPEC "%{h*} \
|
|
%{static:-Bstatic} \
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/bfin/linux.h gcc-5.3.0-zip/gcc/config/bfin/linux.h
|
|
--- gcc-5.3.0-original/gcc/config/bfin/linux.h 2016-11-28 18:14:19.382586425 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/bfin/linux.h 2015-01-05 07:33:28.000000000 -0500
|
|
@@ -45,7 +45,7 @@
|
|
%{shared:-G -Bdynamic} \
|
|
%{!shared: %{!static: \
|
|
%{rdynamic:-export-dynamic} \
|
|
- -dynamic-linker /tools/lib/ld-uClibc.so.0} \
|
|
+ -dynamic-linker /lib/ld-uClibc.so.0} \
|
|
%{static}} -init __init -fini __fini"
|
|
|
|
#undef TARGET_SUPPORTS_SYNC_CALLS
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/cris/linux.h gcc-5.3.0-zip/gcc/config/cris/linux.h
|
|
--- gcc-5.3.0-original/gcc/config/cris/linux.h 2016-11-28 18:14:19.382586425 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/cris/linux.h 2015-01-05 07:33:28.000000000 -0500
|
|
@@ -102,7 +102,7 @@
|
|
#undef CRIS_DEFAULT_CPU_VERSION
|
|
#define CRIS_DEFAULT_CPU_VERSION CRIS_CPU_NG
|
|
|
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
|
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
|
|
|
|
#undef CRIS_LINK_SUBTARGET_SPEC
|
|
#define CRIS_LINK_SUBTARGET_SPEC \
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/freebsd-spec.h gcc-5.3.0-zip/gcc/config/freebsd-spec.h
|
|
--- gcc-5.3.0-original/gcc/config/freebsd-spec.h 2016-11-28 18:14:19.382586425 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/freebsd-spec.h 2015-06-25 13:53:14.000000000 -0400
|
|
@@ -129,9 +129,9 @@
|
|
#endif
|
|
|
|
#if FBSD_MAJOR < 6
|
|
-#define FBSD_DYNAMIC_LINKER "/tools/libexec/ld-elf.so.1"
|
|
+#define FBSD_DYNAMIC_LINKER "/usr/libexec/ld-elf.so.1"
|
|
#else
|
|
-#define FBSD_DYNAMIC_LINKER "/tools/libexec/ld-elf.so.1"
|
|
+#define FBSD_DYNAMIC_LINKER "/libexec/ld-elf.so.1"
|
|
#endif
|
|
|
|
/* NOTE: The freebsd-spec.h header is included also for various
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/frv/linux.h gcc-5.3.0-zip/gcc/config/frv/linux.h
|
|
--- gcc-5.3.0-original/gcc/config/frv/linux.h 2016-11-28 18:14:19.382586425 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/frv/linux.h 2015-01-05 07:33:28.000000000 -0500
|
|
@@ -34,7 +34,7 @@
|
|
#define ENDFILE_SPEC \
|
|
"%{shared|pie:crtendS.o%s;:crtend.o%s} crtn.o%s"
|
|
|
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
|
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
|
|
|
|
#undef LINK_SPEC
|
|
#define LINK_SPEC "\
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/gnu.h gcc-5.3.0-zip/gcc/config/i386/gnu.h
|
|
--- gcc-5.3.0-original/gcc/config/i386/gnu.h 2016-11-28 18:14:19.382586425 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/i386/gnu.h 2015-01-05 07:33:28.000000000 -0500
|
|
@@ -22,7 +22,7 @@
|
|
#define GNU_USER_LINK_EMULATION "elf_i386"
|
|
|
|
#undef GNU_USER_DYNAMIC_LINKER
|
|
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so"
|
|
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so"
|
|
|
|
#undef STARTFILE_SPEC
|
|
#if defined HAVE_LD_PIE
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu64.h
|
|
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h 2016-11-28 18:14:19.386586394 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu64.h 2015-01-05 07:33:28.000000000 -0500
|
|
@@ -22,6 +22,6 @@
|
|
#define GNU_USER_LINK_EMULATION64 "elf_x86_64_fbsd"
|
|
#define GNU_USER_LINK_EMULATIONX32 "elf32_x86_64_fbsd"
|
|
|
|
-#define GLIBC_DYNAMIC_LINKER32 "/tools/lib/ld.so.1"
|
|
-#define GLIBC_DYNAMIC_LINKER64 "/tools/lib/ld-kfreebsd-x86-64.so.1"
|
|
-#define GLIBC_DYNAMIC_LINKERX32 "/tools/lib/ld-kfreebsd-x32.so.1"
|
|
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1"
|
|
+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld-kfreebsd-x86-64.so.1"
|
|
+#define GLIBC_DYNAMIC_LINKERX32 "/lib/ld-kfreebsd-x32.so.1"
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu.h
|
|
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h 2016-11-28 18:14:19.386586394 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu.h 2015-01-05 07:33:28.000000000 -0500
|
|
@@ -19,4 +19,4 @@
|
|
<http://www.gnu.org/licenses/>. */
|
|
|
|
#define GNU_USER_LINK_EMULATION "elf_i386_fbsd"
|
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
|
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/linux64.h gcc-5.3.0-zip/gcc/config/i386/linux64.h
|
|
--- gcc-5.3.0-original/gcc/config/i386/linux64.h 2016-11-28 18:14:19.386586394 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/i386/linux64.h 2015-01-05 07:33:28.000000000 -0500
|
|
@@ -27,6 +27,6 @@
|
|
#define GNU_USER_LINK_EMULATION64 "elf_x86_64"
|
|
#define GNU_USER_LINK_EMULATIONX32 "elf32_x86_64"
|
|
|
|
-#define GLIBC_DYNAMIC_LINKER32 "/tools/lib/ld-linux.so.2"
|
|
-#define GLIBC_DYNAMIC_LINKER64 "/tools/lib64/ld-linux-x86-64.so.2"
|
|
-#define GLIBC_DYNAMIC_LINKERX32 "/tools/libx32/ld-linux-x32.so.2"
|
|
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2"
|
|
+#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux-x86-64.so.2"
|
|
+#define GLIBC_DYNAMIC_LINKERX32 "/libx32/ld-linux-x32.so.2"
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/linux.h gcc-5.3.0-zip/gcc/config/i386/linux.h
|
|
--- gcc-5.3.0-original/gcc/config/i386/linux.h 2016-11-28 18:14:19.386586394 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/i386/linux.h 2015-01-05 07:33:28.000000000 -0500
|
|
@@ -20,4 +20,4 @@
|
|
<http://www.gnu.org/licenses/>. */
|
|
|
|
#define GNU_USER_LINK_EMULATION "elf_i386"
|
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2"
|
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/ia64/linux.h gcc-5.3.0-zip/gcc/config/ia64/linux.h
|
|
--- gcc-5.3.0-original/gcc/config/ia64/linux.h 2016-11-28 18:14:19.386586394 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/ia64/linux.h 2015-01-05 07:33:28.000000000 -0500
|
|
@@ -55,7 +55,7 @@
|
|
/* Define this for shared library support because it isn't in the main
|
|
linux.h file. */
|
|
|
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux-ia64.so.2"
|
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-ia64.so.2"
|
|
|
|
#undef LINK_SPEC
|
|
#define LINK_SPEC "\
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/knetbsd-gnu.h gcc-5.3.0-zip/gcc/config/knetbsd-gnu.h
|
|
--- gcc-5.3.0-original/gcc/config/knetbsd-gnu.h 2016-11-28 18:14:19.386586394 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/knetbsd-gnu.h 2015-01-05 07:33:28.000000000 -0500
|
|
@@ -32,4 +32,4 @@
|
|
|
|
|
|
#undef GNU_USER_DYNAMIC_LINKER
|
|
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so.1"
|
|
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1"
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h gcc-5.3.0-zip/gcc/config/kopensolaris-gnu.h
|
|
--- gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h 2016-11-28 18:14:19.386586394 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/kopensolaris-gnu.h 2015-01-05 07:33:28.000000000 -0500
|
|
@@ -31,5 +31,4 @@
|
|
while (0)
|
|
|
|
#undef GNU_USER_DYNAMIC_LINKER
|
|
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so.1"
|
|
-
|
|
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1"
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/linux.h gcc-5.3.0-zip/gcc/config/linux.h
|
|
--- gcc-5.3.0-original/gcc/config/linux.h 2016-11-28 18:14:19.386586394 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/linux.h 2015-01-05 07:33:28.000000000 -0500
|
|
@@ -73,10 +73,10 @@
|
|
GLIBC_DYNAMIC_LINKER must be defined for each target using them, or
|
|
GLIBC_DYNAMIC_LINKER32 and GLIBC_DYNAMIC_LINKER64 for targets
|
|
supporting both 32-bit and 64-bit compilation. */
|
|
-#define UCLIBC_DYNAMIC_LINKER "/tools/lib/ld-uClibc.so.0"
|
|
-#define UCLIBC_DYNAMIC_LINKER32 "/tools/lib/ld-uClibc.so.0"
|
|
-#define UCLIBC_DYNAMIC_LINKER64 "/tools/lib/ld64-uClibc.so.0"
|
|
-#define UCLIBC_DYNAMIC_LINKERX32 "/tools/lib/ldx32-uClibc.so.0"
|
|
+#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
|
|
+#define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0"
|
|
+#define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0"
|
|
+#define UCLIBC_DYNAMIC_LINKERX32 "/lib/ldx32-uClibc.so.0"
|
|
#define BIONIC_DYNAMIC_LINKER "/system/bin/linker"
|
|
#define BIONIC_DYNAMIC_LINKER32 "/system/bin/linker"
|
|
#define BIONIC_DYNAMIC_LINKER64 "/system/bin/linker64"
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h gcc-5.3.0-zip/gcc/config/lm32/uclinux-elf.h
|
|
--- gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h 2016-11-28 18:14:19.386586394 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/lm32/uclinux-elf.h 2015-01-05 07:33:28.000000000 -0500
|
|
@@ -67,7 +67,7 @@
|
|
%{shared:-shared} \
|
|
%{symbolic:-Bsymbolic} \
|
|
%{rdynamic:-export-dynamic} \
|
|
- -dynamic-linker /tools/lib/ld-linux.so.2"
|
|
+ -dynamic-linker /lib/ld-linux.so.2"
|
|
|
|
#define TARGET_OS_CPP_BUILTINS() GNU_USER_TARGET_OS_CPP_BUILTINS()
|
|
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/m68k/linux.h gcc-5.3.0-zip/gcc/config/m68k/linux.h
|
|
--- gcc-5.3.0-original/gcc/config/m68k/linux.h 2016-11-28 18:14:19.386586394 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/m68k/linux.h 2015-01-05 07:33:28.000000000 -0500
|
|
@@ -71,7 +71,7 @@
|
|
When the -shared link option is used a final link is not being
|
|
done. */
|
|
|
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
|
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
|
|
|
|
#undef LINK_SPEC
|
|
#define LINK_SPEC "-m m68kelf %{shared} \
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/microblaze/linux.h gcc-5.3.0-zip/gcc/config/microblaze/linux.h
|
|
--- gcc-5.3.0-original/gcc/config/microblaze/linux.h 2016-11-28 18:14:19.386586394 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/microblaze/linux.h 2015-05-28 10:08:19.000000000 -0400
|
|
@@ -28,7 +28,7 @@
|
|
#undef TLS_NEEDS_GOT
|
|
#define TLS_NEEDS_GOT 1
|
|
|
|
-#define DYNAMIC_LINKER "/tools/lib/ld.so.1"
|
|
+#define DYNAMIC_LINKER "/lib/ld.so.1"
|
|
#undef SUBTARGET_EXTRA_SPECS
|
|
#define SUBTARGET_EXTRA_SPECS \
|
|
{ "dynamic_linker", DYNAMIC_LINKER }
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/mips/linux.h gcc-5.3.0-zip/gcc/config/mips/linux.h
|
|
--- gcc-5.3.0-original/gcc/config/mips/linux.h 2016-11-28 18:14:19.386586394 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/mips/linux.h 2015-01-05 07:33:28.000000000 -0500
|
|
@@ -22,20 +22,20 @@
|
|
#define GNU_USER_LINK_EMULATIONN32 "elf32%{EB:b}%{EL:l}tsmipn32"
|
|
|
|
#define GLIBC_DYNAMIC_LINKER32 \
|
|
- "%{mnan=2008:/tools/lib/ld-linux-mipsn8.so.1;:/tools/lib/ld.so.1}"
|
|
+ "%{mnan=2008:/lib/ld-linux-mipsn8.so.1;:/lib/ld.so.1}"
|
|
#define GLIBC_DYNAMIC_LINKER64 \
|
|
- "%{mnan=2008:/tools/lib64/ld-linux-mipsn8.so.1;:/tools/lib64/ld.so.1}"
|
|
+ "%{mnan=2008:/lib64/ld-linux-mipsn8.so.1;:/lib64/ld.so.1}"
|
|
#define GLIBC_DYNAMIC_LINKERN32 \
|
|
- "%{mnan=2008:/tools/lib32/ld-linux-mipsn8.so.1;:/tools/lib32/ld.so.1}"
|
|
+ "%{mnan=2008:/lib32/ld-linux-mipsn8.so.1;:/lib32/ld.so.1}"
|
|
|
|
#undef UCLIBC_DYNAMIC_LINKER32
|
|
#define UCLIBC_DYNAMIC_LINKER32 \
|
|
- "%{mnan=2008:/tools/lib/ld-uClibc-mipsn8.so.0;:/tools/lib/ld-uClibc.so.0}"
|
|
+ "%{mnan=2008:/lib/ld-uClibc-mipsn8.so.0;:/lib/ld-uClibc.so.0}"
|
|
#undef UCLIBC_DYNAMIC_LINKER64
|
|
#define UCLIBC_DYNAMIC_LINKER64 \
|
|
- "%{mnan=2008:/tools/lib/ld64-uClibc-mipsn8.so.0;:/tools/lib/ld64-uClibc.so.0}"
|
|
+ "%{mnan=2008:/lib/ld64-uClibc-mipsn8.so.0;:/lib/ld64-uClibc.so.0}"
|
|
#define UCLIBC_DYNAMIC_LINKERN32 \
|
|
- "%{mnan=2008:/tools/lib32/ld-uClibc-mipsn8.so.0;:/tools/lib32/ld-uClibc.so.0}"
|
|
+ "%{mnan=2008:/lib32/ld-uClibc-mipsn8.so.0;:/lib32/ld-uClibc.so.0}"
|
|
|
|
#define BIONIC_DYNAMIC_LINKERN32 "/system/bin/linker32"
|
|
#define GNU_USER_DYNAMIC_LINKERN32 \
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/mn10300/linux.h gcc-5.3.0-zip/gcc/config/mn10300/linux.h
|
|
--- gcc-5.3.0-original/gcc/config/mn10300/linux.h 2016-11-28 18:14:19.386586394 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/mn10300/linux.h 2015-01-05 07:33:28.000000000 -0500
|
|
@@ -32,7 +32,7 @@
|
|
#undef ASM_SPEC
|
|
#define ASM_SPEC ""
|
|
|
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
|
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
|
|
|
|
#undef LINK_SPEC
|
|
#define LINK_SPEC "%{mrelax:--relax} %{shared:-shared} \
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/pa/pa-linux.h gcc-5.3.0-zip/gcc/config/pa/pa-linux.h
|
|
--- gcc-5.3.0-original/gcc/config/pa/pa-linux.h 2016-11-28 18:14:19.386586394 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/pa/pa-linux.h 2015-09-24 20:04:26.000000000 -0400
|
|
@@ -37,7 +37,7 @@
|
|
/* Define this for shared library support because it isn't in the main
|
|
linux.h file. */
|
|
|
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
|
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
|
|
|
|
#undef LINK_SPEC
|
|
#define LINK_SPEC "\
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/rs6000/linux64.h gcc-5.3.0-zip/gcc/config/rs6000/linux64.h
|
|
--- gcc-5.3.0-original/gcc/config/rs6000/linux64.h 2016-11-28 18:14:19.386586394 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/rs6000/linux64.h 2015-03-09 19:18:57.000000000 -0400
|
|
@@ -357,14 +357,14 @@
|
|
#undef LINK_OS_DEFAULT_SPEC
|
|
#define LINK_OS_DEFAULT_SPEC "%(link_os_linux)"
|
|
|
|
-#define GLIBC_DYNAMIC_LINKER32 "/tools/lib/ld.so.1"
|
|
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1"
|
|
#ifdef LINUX64_DEFAULT_ABI_ELFv2
|
|
-#define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv1:/tools/lib64/ld64.so.1;:/tools/lib64/ld64.so.2}"
|
|
+#define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv1:/lib64/ld64.so.1;:/lib64/ld64.so.2}"
|
|
#else
|
|
-#define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv2:/tools/lib64/ld64.so.2;:/tools/lib64/ld64.so.1}"
|
|
+#define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv2:/lib64/ld64.so.2;:/lib64/ld64.so.1}"
|
|
#endif
|
|
-#define UCLIBC_DYNAMIC_LINKER32 "/tools/lib/ld-uClibc.so.0"
|
|
-#define UCLIBC_DYNAMIC_LINKER64 "/tools/lib/ld64-uClibc.so.0"
|
|
+#define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0"
|
|
+#define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0"
|
|
#if DEFAULT_LIBC == LIBC_UCLIBC
|
|
#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
|
|
#elif DEFAULT_LIBC == LIBC_GLIBC
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/rs6000/sysv4.h gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h
|
|
--- gcc-5.3.0-original/gcc/config/rs6000/sysv4.h 2016-11-28 18:14:19.386586394 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h 2015-09-24 09:46:45.000000000 -0400
|
|
@@ -757,8 +757,8 @@
|
|
|
|
#define LINK_START_LINUX_SPEC ""
|
|
|
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
|
|
-#define UCLIBC_DYNAMIC_LINKER "/tools/lib/ld-uClibc.so.0"
|
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
|
|
+#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
|
|
#if DEFAULT_LIBC == LIBC_UCLIBC
|
|
#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
|
|
#elif !defined (DEFAULT_LIBC) || DEFAULT_LIBC == LIBC_GLIBC
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/s390/linux.h gcc-5.3.0-zip/gcc/config/s390/linux.h
|
|
--- gcc-5.3.0-original/gcc/config/s390/linux.h 2016-11-28 18:14:19.386586394 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/s390/linux.h 2015-05-11 03:14:10.000000000 -0400
|
|
@@ -60,8 +60,8 @@
|
|
#define MULTILIB_DEFAULTS { "m31" }
|
|
#endif
|
|
|
|
-#define GLIBC_DYNAMIC_LINKER32 "/tools/lib/ld.so.1"
|
|
-#define GLIBC_DYNAMIC_LINKER64 "/tools/lib/ld64.so.1"
|
|
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1"
|
|
+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld64.so.1"
|
|
|
|
#undef LINK_SPEC
|
|
#define LINK_SPEC \
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sh/linux.h gcc-5.3.0-zip/gcc/config/sh/linux.h
|
|
--- gcc-5.3.0-original/gcc/config/sh/linux.h 2016-11-28 18:14:19.386586394 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/sh/linux.h 2015-01-05 07:33:28.000000000 -0500
|
|
@@ -43,7 +43,7 @@
|
|
|
|
#define TARGET_ASM_FILE_END file_end_indicate_exec_stack
|
|
|
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2"
|
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
|
|
|
|
#undef SUBTARGET_LINK_EMUL_SUFFIX
|
|
#define SUBTARGET_LINK_EMUL_SUFFIX "_linux"
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sparc/linux64.h gcc-5.3.0-zip/gcc/config/sparc/linux64.h
|
|
--- gcc-5.3.0-original/gcc/config/sparc/linux64.h 2016-11-28 18:14:19.386586394 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/sparc/linux64.h 2015-01-05 07:33:28.000000000 -0500
|
|
@@ -84,8 +84,8 @@
|
|
When the -shared link option is used a final link is not being
|
|
done. */
|
|
|
|
-#define GLIBC_DYNAMIC_LINKER32 "/tools/lib/ld-linux.so.2"
|
|
-#define GLIBC_DYNAMIC_LINKER64 "/tools/lib64/ld-linux.so.2"
|
|
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2"
|
|
+#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux.so.2"
|
|
|
|
#ifdef SPARC_BI_ARCH
|
|
|
|
@@ -193,7 +193,7 @@
|
|
#else /* !SPARC_BI_ARCH */
|
|
|
|
#undef LINK_SPEC
|
|
-#define LINK_SPEC "-m elf64_sparc -Y P,%R/tools/lib64 %{shared:-shared} \
|
|
+#define LINK_SPEC "-m elf64_sparc -Y P,%R/usr/lib64 %{shared:-shared} \
|
|
%{!shared: \
|
|
%{!static: \
|
|
%{rdynamic:-export-dynamic} \
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sparc/linux.h gcc-5.3.0-zip/gcc/config/sparc/linux.h
|
|
--- gcc-5.3.0-original/gcc/config/sparc/linux.h 2016-11-28 18:14:19.386586394 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/sparc/linux.h 2015-01-05 07:33:28.000000000 -0500
|
|
@@ -83,7 +83,7 @@
|
|
When the -shared link option is used a final link is not being
|
|
done. */
|
|
|
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2"
|
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
|
|
|
|
#undef LINK_SPEC
|
|
#define LINK_SPEC "-m elf32_sparc %{shared:-shared} \
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/vax/linux.h gcc-5.3.0-zip/gcc/config/vax/linux.h
|
|
--- gcc-5.3.0-original/gcc/config/vax/linux.h 2016-11-28 18:14:19.386586394 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/vax/linux.h 2015-01-05 07:33:28.000000000 -0500
|
|
@@ -41,7 +41,7 @@
|
|
%{!shared: \
|
|
%{!static: \
|
|
%{rdynamic:-export-dynamic} \
|
|
- -dynamic-linker /tools/lib/ld.so.1} \
|
|
+ -dynamic-linker /lib/ld.so.1} \
|
|
%{static:-static}}"
|
|
|
|
#undef WCHAR_TYPE
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/xtensa/linux.h gcc-5.3.0-zip/gcc/config/xtensa/linux.h
|
|
--- gcc-5.3.0-original/gcc/config/xtensa/linux.h 2016-11-28 18:14:19.386586394 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/xtensa/linux.h 2015-01-05 07:33:28.000000000 -0500
|
|
@@ -44,7 +44,7 @@
|
|
%{mlongcalls:--longcalls} \
|
|
%{mno-longcalls:--no-longcalls}"
|
|
|
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
|
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
|
|
|
|
#undef LINK_SPEC
|
|
#define LINK_SPEC \
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/netbsd.h gcc-5.3.0-zip/gcc/config/zip/netbsd.h
|
|
--- gcc-5.3.0-original/gcc/config/zip/netbsd.h 1969-12-31 19:00:00.000000000 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/zip/netbsd.h 2016-01-30 15:04:14.796899050 -0500
|
|
@@ -0,0 +1,82 @@
|
|
+////////////////////////////////////////////////////////////////////////////////
|
+////////////////////////////////////////////////////////////////////////////////
|
+//
|
+//
|
+// Filename: netbsd.h
|
+// Filename: genzipops.c
|
+//
|
+//
|
+// Project: Zip CPU backend for the GNU Compiler Collection
|
+// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
|
|
+//
|
|
+// Purpose: This program generates the zip-ops.md machine description file.
|
|
+//
|
|
+// While I understand that this is not GCC's preferred method of generating
|
|
+// machine description files, there were just so many instructions to
|
|
+// generate, and so many forms of them, and the GCC infrastructure didn't
|
|
+// support the conditional execution model of the ZipCPU that ... I built
|
|
+// it this way.
|
|
+//
|
|
+// As of this writing, building zip-ops.md is not an automatic part of
|
|
+// making GCC. To build genzipops, just type:
|
|
+//
|
|
+// g++ genzipops.c -o genzipops
|
|
+//
|
|
+// And to run it, type:
|
|
+//
|
|
+// genzipops > zip-ops.md
|
|
+//
|
|
+// genzipops takes no arguments, and does nothing but write the machine
|
|
+// descriptions to the standard output.
|
+//
|
+//
|
+// Purpose:
|
|
+//
|
+//
|
+// Creator: Dan Gisselquist, Ph.D.
|
+// Creator: Dan Gisselquist, Ph.D.
|
+// Gisselquist Technology, LLC
|
+// Gisselquist Technology, LLC
|
+//
|
+//
|
+////////////////////////////////////////////////////////////////////////////////
|
+////////////////////////////////////////////////////////////////////////////////
|
+//
|
+//
|
+// Copyright (C) 2016, Gisselquist Technology, LLC
|
+// Copyright (C) 2017, Gisselquist Technology, LLC
|
+//
|
+//
|
+// This program is free software (firmware): you can redistribute it and/or
|
+// This program is free software (firmware): you can redistribute it and/or
|
+// modify it under the terms of the GNU General Public License as published
|
+// modify it under the terms of the GNU General Public License as published
|
+// by the Free Software Foundation, either version 3 of the License, or (at
|
+// by the Free Software Foundation, either version 3 of the License, or (at
|
+// your option) any later version.
|
+// your option) any later version.
|
| Line 585... |
Line 347... |
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
+// for more details.
|
+// for more details.
|
+//
|
+//
|
+// You should have received a copy of the GNU General Public License along
|
+// You should have received a copy of the GNU General Public License along
|
+// with this program. (It's in the $(ROOT)/doc directory, run make with no
|
+// with this program. (It's in the $(ROOT)/doc directory. Run make with no
|
+// target there if the PDF file isn't present.) If not, see
|
+// target there if the PDF file isn't present.) If not, see
|
+// <http://www.gnu.org/licenses/> for a copy.
|
+// <http://www.gnu.org/licenses/> for a copy.
|
+//
|
+//
|
+// License: GPL, v3, as defined and found on www.gnu.org,
|
+// License: GPL, v3, as defined and found on www.gnu.org,
|
+// http://www.gnu.org/licenses/gpl.html
|
+// http://www.gnu.org/licenses/gpl.html
|
+//
|
+//
|
+//
|
+//
|
+////////////////////////////////////////////////////////////////////////////////
|
+////////////////////////////////////////////////////////////////////////////////
|
+#ifndef ZIP_NETBSD_H
|
+//
|
+#define ZIP_NETBSD_H
|
+//
|
+
|
+#include <unistd.h>
|
+/* Define default target values. */
|
+#include <stdlib.h>
|
+
|
+#include <stdio.h>
|
+#undef MACHINE_TYPE
|
+#include <string.h>
|
+#define MACHINE_TYPE "NetBSD/Zip ELF"
|
|
+
|
|
+#undef TARGET_OS_CPP_BUILTINS
|
|
+#define TARGET_OS_CPP_BUILTINS() \
|
|
+ do { NETBSD_OS_CPP_BUILTINS_ELF(); \
|
|
+ builtin_define("__ZIPCPU__"); \
|
|
+ builtin_assert("cpu=zip"); \
|
|
+ builtin_assert("machine=zip"); \
|
|
+ } while(0);
|
|
+
|
|
+#undef CPP_SPEC
|
|
+#define CPP_SPEC NETBSD_CPP_SPEC
|
|
+
|
|
+#undef STARTFILE_SPEC
|
|
+#define STARTFILE_SPEC NETBSD_STARTFILE_SPEC
|
|
+
|
|
+#undef ENDFILE_SPEC
|
|
+#define ENDFILE_SPEC NETBSD_ENDFILE_SPEC
|
|
+
|
|
+#undef LIB_SPEC
|
|
+#define LIB_SPEC NETBSD_LIB_SPEC
|
|
+
|
+
|
+#undef TARGET_VERSION
|
+void legal(FILE *fp) {
|
+#define TARGET_VERSION fprintf(stderr, " (%s)", MACHINE_TYPE);
|
+ fprintf(fp, ""
|
+
|
+";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n"
|
+/* Make gcc agree with <machine/ansi.h> */
|
+";;\n"
|
+
|
+";; Filename: zip-ops.md\n"
|
+#undef WCHAR_TYPE
|
+";;\n"
|
+#define WCHAR_TYPE "int"
|
+";; Project: Zip CPU -- a small, lightweight, RISC CPU soft core\n"
|
+
|
+";;\n"
|
+#undef WCHAR_TYPE_SIZE
|
+";; Purpose: This is a computer generated machine description of the\n"
|
+#define WCHAR_TYPE_SIZE 32
|
+";; ZipCPU\'s operations. It is computer generated simply for\n"
|
+
|
+";; two reasons. First, I can\'t seem to find a way to generate this\n"
|
+#undef WINT_TYPE
|
+";; information within GCC\'s current constructs. Specifically, the\n"
|
+#define WINT_TYPE "int"
|
+";; CPU\'s instructions normally set the condition codes, unless they\n"
|
+
|
+";; are conditional instructions when they don\'t. Second, the ZipCPU is\n"
|
+/* Clean up after the generic Zip/ELF configuration. */
|
+";; actually quite regular. Almost all of the instructions have the same\n"
|
+#undef MD_EXEC_PREFIX
|
+";; form. This form turns into many, many RTL instructions. Because the\n"
|
+#undef MD_STARTFILE_PREFIX
|
+";; CPU doesn\'t match any of the others within GCC, that means either\n"
|
+
|
+";; I have a *lot* of cut, copy, paste, and edit to do to create the file\n"
|
+#endif /* ZIP_NETBSD_H */
|
+";; and upon any and every edit, or I need to build a program to generate\n"
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/notes.txt gcc-5.3.0-zip/gcc/config/zip/notes.txt
|
+";; the remaining .md constructs. Hence, I chose the latter to minimize\n"
|
--- gcc-5.3.0-original/gcc/config/zip/notes.txt 1969-12-31 19:00:00.000000000 -0500
|
+";; the amount of work I needed to do.\n"
|
+++ gcc-5.3.0-zip/gcc/config/zip/notes.txt 2016-08-17 23:00:25.714139174 -0400
|
+";;\n"
|
@@ -0,0 +1,6 @@
|
+";;\n"
|
+signum:
|
+";; Creator: Dan Gisselquist, Ph.D.\n"
|
+ CMP 0,%1
|
+";; Gisselquist Technology, LLC\n"
|
+ LDILO.GT 1,%1
|
+";;\n"
|
+ LDILO.LT -1,%1
|
+";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n"
|
+
|
+";;\n"
|
+
|
+";; Copyright (C) 2017, Gisselquist Technology, LLC\n"
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/t-zip gcc-5.3.0-zip/gcc/config/zip/t-zip
|
+";;\n"
|
--- gcc-5.3.0-original/gcc/config/zip/t-zip 1969-12-31 19:00:00.000000000 -0500
|
+";; This program is free software (firmware): you can redistribute it and/or\n"
|
+++ gcc-5.3.0-zip/gcc/config/zip/t-zip 2016-02-04 19:00:59.939652587 -0500
|
+";; modify it under the terms of the GNU General Public License as published\n"
|
@@ -0,0 +1,47 @@
|
+";; by the Free Software Foundation, either version 3 of the License, or (at\n"
|
+################################################################################
|
+";; your option) any later version.\n"
|
+##
|
+";;\n"
|
+## Filename: t-zip
|
+";; This program is distributed in the hope that it will be useful, but WITHOUT\n"
|
+##
|
+";; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or\n"
|
+## Project: Zip CPU backend for the GNU Compiler Collection
|
+";; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\n"
|
+##
|
+";; for more details.\n"
|
+## Purpose:
|
+";;\n"
|
+##
|
+";; License: GPL, v3, as defined and found on www.gnu.org,\n"
|
+## Creator: Dan Gisselquist, Ph.D.
|
+";; http://www.gnu.org/licenses/gpl.html\n"
|
+## Gisselquist Technology, LLC
|
+";;\n"
|
+##
|
+";;\n"
|
+################################################################################
|
+";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n"
|
+##
|
+";;\n"
|
+## Copyright (C) 2016, Gisselquist Technology, LLC
|
+";;\n");
|
+##
|
+}
|
+## This program is free software (firmware): you can redistribute it and/or
|
+
|
+## modify it under the terms of the GNU General Public License as published
|
+void gen_heading(FILE *fp, const char *heading) {
|
+## by the Free Software Foundation, either version 3 of the License, or (at
|
+ fprintf(fp, ";\n;\n; %s\n;\n;\n", heading);
|
+## your option) any later version.
|
+}
|
+##
|
+
|
+## This program is distributed in the hope that it will be useful, but WITHOUT
|
+void genzip_condop(FILE *fp, const char *md_opname,
|
+## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
+ const char *rtxstr, const char *insn_cond,
|
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
+ const char *zip_op,
|
+## for more details.
|
+ const char *rtx_cond, const char *zip_cond) {
|
+##
|
+
|
+## You should have received a copy of the GNU General Public License along
|
+ fprintf(fp, "(define_insn \"%s_%s\"\n"
|
+## with this program. (It's in the $(ROOT)/doc directory, run make with no
|
+ "\t[(cond_exec (%s (reg:CC CC_REG) (const_int 0))\n"
|
+## target there if the PDF file isn't present.) If not, see
|
+ "\t\t\t%s)]\n"
|
+## <http://www.gnu.org/licenses/> for a copy.
|
+ "\t\"%s\"\t; Condition\n"
|
+##
|
+ "\t\"%s.%s\\t%%1,%%0\t; genzip, conditional operator\"\t; Template\n"
|
+## License: GPL, v3, as defined and found on www.gnu.org,
|
+ "\t[(set_attr \"predicable\" \"no\") "
|
+## http://www.gnu.org/licenses/gpl.html
|
+ "(set_attr \"ccresult\" \"unchanged\")])\n;\n;\n",
|
+##
|
+ md_opname, rtx_cond, rtx_cond, rtxstr, insn_cond, zip_op, zip_cond);
|
+##
|
+
|
+################################################################################
|
+}
|
+
|
+
|
+FPBIT = fp-bit.c
|
+void genzipop_long(FILE *fp, const char *md_opname, const char *uncond_rtx, const char *insn_cond, const char *split_rtx, const char *dup_rtx, const char *zip_op) {
|
+DPBIT = dp-bit.c
|
+ char heading[128];
|
+
|
+ sprintf(heading, "%s (genzipop_long)", zip_op);
|
+# dp-bit.c: $(srcdir)/config/fp-bit.c
|
+ fprintf(fp, ";\n;\n;\n; %s (genzipop_long)\n;\n;\n;\n", zip_op);
|
+ # cat $(srcdir)/config/fp-bit.c > dp-bit.c
|
+
|
+#
|
+ fprintf(fp, "(define_insn \"%s\"\n"
|
+# fp-bit.c: $(srcdir)/config/fp-bit.c
|
+"\t[%s\n"
|
+ # echo '#define FLOAT" > fp-bit.c
|
+"\t(clobber (reg:CC CC_REG))]\n"
|
+ # cat $(srcdir)/config/fp-bit.c >> fp-bit.c
|
+"\t\"%s\"\n"
|
+
|
+"\t\"%s\\t%%2,%%0\t; %s\"\n"
|
+
|
+"\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"set\")])\n;\n;\n",
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.c gcc-5.3.0-zip/gcc/config/zip/zip.c
|
+ md_opname, uncond_rtx, insn_cond, zip_op, md_opname);
|
--- gcc-5.3.0-original/gcc/config/zip/zip.c 1969-12-31 19:00:00.000000000 -0500
|
+
|
+++ gcc-5.3.0-zip/gcc/config/zip/zip.c 2016-11-19 08:28:56.703678695 -0500
|
+
|
@@ -0,0 +1,2293 @@
|
+ fprintf(fp, "(define_insn \"%s_raw\"\n"
|
|
+"\t[%s\n"
|
|
+"\t(set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]\n"
|
|
+"\t\"%s\"\n"
|
|
+"\t\"%s\\t%%1,%%0\t; %s_raw\"\n"
|
|
+"\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"set\")])\n;\n;\n",
|
|
+ md_opname, dup_rtx, insn_cond, zip_op, md_opname);
|
|
+
|
|
+ genzip_condop(fp, md_opname, dup_rtx, insn_cond, zip_op, "eq", "Z");
|
|
+ genzip_condop(fp, md_opname, dup_rtx, insn_cond, zip_op, "ne", "NZ");
|
|
+ genzip_condop(fp, md_opname, dup_rtx, insn_cond, zip_op, "lt", "LT");
|
|
+ genzip_condop(fp, md_opname, dup_rtx, insn_cond, zip_op, "ge", "GE");
|
|
+ genzip_condop(fp, md_opname, dup_rtx, insn_cond, zip_op, "ltu", "C");
|
|
+ genzip_condop(fp, md_opname, dup_rtx, insn_cond, zip_op, "geu", "NC");
|
|
+}
|
|
+
|
|
+void genzipop(FILE *fp, const char *md_opname, const char *rtx_name, const char *insn_cond, const char *zip_op) {
|
|
+ char rtxstr[512], splitstr[512], dupstr[512], altname[64];
|
|
+
|
|
+ sprintf(rtxstr,
|
|
+"(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
|
|
+"\t\t(%s (match_operand:SI 1 \"register_operand\" \"0\")\n"
|
|
+"\t\t\t(match_operand:SI 2 \"zip_opb_single_operand_p\" \"rO\")))", rtx_name);
|
|
+ sprintf(splitstr,
|
|
+ "(set (match_dup 0) (%s (match_dup 0) (match_dup 2)))", rtx_name);
|
|
+
|
|
+ sprintf(dupstr,
|
|
+"(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
|
|
+"\t\t(%s (match_dup 0)\n"
|
|
+"\t\t\t(match_operand:SI 1 \"zip_opb_single_operand_p\" \"rO\")))", rtx_name);
|
|
+
|
|
+ genzipop_long(fp, md_opname, rtxstr, insn_cond, splitstr, dupstr, zip_op);
|
|
+
|
|
+ sprintf(rtxstr,
|
|
+"(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
|
|
+"\t\t(%s (match_operand:SI 1 \"register_operand\" \"0\")\n"
|
|
+"\t\t\t(plus:SI (match_operand:SI 2 \"register_operand\" \"r\")\n"
|
|
+"\t\t\t\t(match_operand:SI 3 \"const_int_operand\" \"N\"))))", rtx_name);
|
|
+ sprintf(splitstr,
|
|
+ "(set (match_dup 0) (%s (match_dup 0)\n"
|
|
+"\t\t\t(plus:SI (match_dup 2) (match_dup 3))))", rtx_name);
|
|
+
|
|
+ sprintf(dupstr,
|
|
+"(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
|
|
+"\t\t(%s (match_dup 0)\n"
|
|
+"\t\t\t(plus:SI (match_operand:SI 1 \"register_operand\" \"r\")\n"
|
|
+"\t\t\t\t(match_operand:SI 2 \"const_int_operand\" \"N\"))))", rtx_name);
|
|
+
|
|
+ sprintf(altname, "%s_off", md_opname);
|
|
+
|
|
+ genzipop_long(fp, altname, rtxstr, insn_cond, splitstr, dupstr, zip_op);
|
|
+}
|
|
+
|
|
+void gencmov(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
|
|
+ fprintf(fp, ";\n;\n"
|
|
+"(define_insn \"%s_%s\"\n"
|
|
+ "\t[(set (match_operand:SI 0 \"register_operand\" \"=r,r,r,Q\")\n"
|
|
+ "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
|
|
+ "\t\t\t(match_operand:SI 1 \"general_operand\" \"r,Q,i,r\")\n"
|
|
+ "\t\t\t(match_dup 0)))]\n"
|
|
+ "\t\"\"\n"
|
|
+ "\t\"@\n"
|
|
+ "\tMOV.%s\t%%1,%%0\t; cmov\n"
|
|
+ "\tLW.%s\t%%1,%%0\t; cmov\n"
|
|
+ "\tLDI.%s\t%%1,%%0\t; cmov\n"
|
|
+ "\tSW.%s\t%%1,%%0\t; cmov\"\n"
|
|
+ "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
|
|
+ md_opname, md_cond, md_cond, zip_cond, zip_cond, zip_cond, zip_cond);
|
|
+
|
|
+}
|
|
+
|
|
+void gencadd(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
|
|
+ fprintf(fp, ";\n;\n"
|
|
+"(define_insn \"%s_%s\"\n"
|
|
+ "\t[(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
|
|
+ "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
|
|
+ "\t\t\t(plus:SI (match_dup 0)\n"
|
|
+ "\t\t\t\t(match_operand:SI 1 \"zip_opb_single_operand_p\" \"rO\"))\n"
|
|
+ "\t\t\t(match_dup 0)))]\n"
|
|
+ "\t\"\"\n"
|
|
+ "\t\"ADD.%s\t%%1,%%0\t; cadd\"\n"
|
|
+ "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
|
|
+ md_opname, md_cond, md_cond, zip_cond);
|
|
+}
|
|
+
|
|
+void gencnot(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
|
|
+ fprintf(fp, ";\n;\n"
|
|
+"(define_insn \"%s_%s\"\n"
|
|
+ "\t[(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
|
|
+ "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
|
|
+ "\t\t\t(xor:SI (match_dup 0)\n"
|
|
+ "\t\t\t\t(const_int -1))\n"
|
|
+ "\t\t\t(match_dup 0)))]\n"
|
|
+ "\t\"\"\n"
|
|
+ "\t\"NOT.%s\t%%0\t; cnot\"\n"
|
|
+ "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
|
|
+ md_opname, md_cond, md_cond, zip_cond);
|
|
+}
|
|
+
|
|
+void gencneg(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
|
|
+ fprintf(fp, ";\n;\n"
|
|
+"(define_insn \"%s_%s\"\n"
|
|
+ "\t[(set (match_operand:SI 0 \"register_operand\" \"+r\")\n"
|
|
+ "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
|
|
+ "\t\t\t(neg:SI (match_dup 0))\n"
|
|
+ "\t\t\t(match_dup 0)))]\n"
|
|
+ "\t\"\"\n"
|
|
+ "\t\"NEG.%s\t%%0\t; cneg\"\n"
|
|
+ "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
|
|
+ md_opname, md_cond, md_cond, zip_cond);
|
|
+}
|
|
+
|
|
+
|
|
+void gencand(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
|
|
+ fprintf(fp, ";\n;\n"
|
|
+"(define_insn \"%s_%s\"\n"
|
|
+ "\t[(set (match_operand:SI 0 \"register_operand\" \"+r\")\n"
|
|
+ "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
|
|
+ "\t\t\t(and:SI (match_dup 0) (match_operand:SI 1 \"zip_opb_single_operand_p\" \"rO\"))\n"
|
|
+ "\t\t\t(match_dup 0)))]\n"
|
|
+ "\t\"\"\n"
|
|
+ "\t\"AND.%s\t%%1,%%0\t; cand\"\n"
|
|
+ "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
|
|
+ md_opname, md_cond, md_cond, zip_cond);
|
|
+}
|
|
+
|
|
+
|
|
+void gencior(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
|
|
+ fprintf(fp, ";\n;\n"
|
|
+"(define_insn \"%s_%s\"\n"
|
|
+ "\t[(set (match_operand:SI 0 \"register_operand\" \"+r\")\n"
|
|
+ "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
|
|
+ "\t\t\t(ior:SI (match_dup 0) (match_operand:SI 1 \"zip_opb_single_operand_p\" \"rO\"))\n"
|
|
+ "\t\t\t(match_dup 0)))]\n"
|
|
+ "\t\"\"\n"
|
|
+ "\t\"OR.%s\t%%1,%%0\t; cior\"\n"
|
|
+ "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
|
|
+ md_opname, md_cond, md_cond, zip_cond);
|
|
+}
|
|
+
|
|
+void gencxor(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
|
|
+ fprintf(fp, ";\n;\n"
|
|
+"(define_insn \"%s_%s\"\n"
|
|
+ "\t[(set (match_operand:SI 0 \"register_operand\" \"+r\")\n"
|
|
+ "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
|
|
+ "\t\t\t(xor:SI (match_dup 0) (match_operand:SI 1 \"zip_opb_single_operand_p\" \"rO\"))\n"
|
|
+ "\t\t\t(match_dup 0)))]\n"
|
|
+ "\t\"\"\n"
|
|
+ "\t\"XOR.%s\t%%1,%%0\t; cxor\"\n"
|
|
+ "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
|
|
+ md_opname, md_cond, md_cond, zip_cond);
|
|
+}
|
|
+
|
|
+void usage(void) {
|
|
+ printf("USAGE: genzipops <new-zip-ops.md filename>\n");
|
|
+}
|
|
+
|
|
+const char *TMPPATH = ".zip-ops.md";
|
|
+const char *TAILPATH = "zip-ops.md";
|
|
+
|
|
+int main(int argc, char **argv) {
|
|
+ FILE *fp = fopen(TMPPATH, "w");
|
|
+ const char *newname = TAILPATH;
|
|
+
|
|
+ if ((argc>1)&&(argv[1][0] == '-')) {
|
|
+ usage();
|
|
+ exit(EXIT_FAILURE);
|
|
+ }
|
|
+
|
|
+ if (argc>1) {
|
|
+ if ((strlen(argv[1])>=strlen(TAILPATH))
|
|
+ &&(strcmp(&argv[1][strlen(argv[1])-strlen(TAILPATH)],
|
|
+ TAILPATH)==0)
|
|
+ &&(access(argv[1], F_OK)==0))
|
|
+ unlink(argv[1]);
|
|
+ newname = argv[1];
|
|
+ }
|
|
+
|
|
+ legal(fp);
|
|
+ genzipop(fp, "addsi3", "plus:SI", "", "ADD");
|
|
+ genzipop(fp, "subsi3", "minus:SI", "", "SUB");
|
|
+ genzipop(fp, "mulsi3", "mult:SI", "", "MPY");
|
|
+ genzipop(fp, "divsi3", "div:SI", "(ZIP_DIVIDE)", "DIVS");
|
|
+ genzipop(fp, "udivsi3", "udiv:SI", "(ZIP_DIVIDE)", "DIVU");
|
|
+ genzipop(fp, "andsi3", "and:SI", "", "AND");
|
|
+ genzipop(fp, "iorsi3", "ior:SI", "", "OR");
|
|
+ genzipop(fp, "xorsi3", "xor:SI", "", "XOR");
|
|
+ genzipop(fp, "ashrsi3", "ashiftrt:SI","", "ASR");
|
|
+ genzipop(fp, "ashlsi3", "ashift:SI", "", "LSL");
|
|
+ genzipop(fp, "lshrsi3", "lshiftrt:SI","", "LSR");
|
|
+
|
|
+ genzipop_long(fp, "smulsi_highpart",
|
|
+ "(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
|
|
+ "\t\t(truncate:SI (ashiftrt:DI (mult:DI\n"
|
|
+ "\t\t\t(sign_extend:DI (match_operand:SI 1 \"register_operand\" \"0\"))\n"
|
|
+ "\t\t\t(sign_extend:DI (match_operand:SI 2 \"zip_opb_operand_p\" \"rO\")))\n"
|
|
+ "\t\t\t(const_int 32))))",
|
|
+ "(ZIP_HAS_DI)",
|
|
+ "(set (match_dup 0)\n"
|
|
+ "\t\t(truncate:SI (ashiftrt:DI (mult:DI\n"
|
|
+ "\t\t\t(sign_extend:DI (match_dup 1))\n"
|
|
+ "\t\t\t(sign_extend:DI (match_dup 2)))\n"
|
|
+ "\t\t\t(const_int 32))))",
|
|
+ //
|
|
+ "(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
|
|
+ "\t\t(truncate:SI (ashiftrt:DI (mult:DI\n"
|
|
+ "\t\t\t(sign_extend:DI (match_dup 0))\n"
|
|
+ "\t\t\t(sign_extend:DI (match_operand:SI 1 \"zip_opb_operand_p\" \"rO\")))\n"
|
|
+ "\t\t\t(const_int 32))))",
|
|
+ "MPYSHI");
|
|
+ genzipop_long(fp, "umulsi_highpart",
|
|
+ "(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
|
|
+ "\t\t(truncate:SI (ashiftrt:DI (mult:DI\n"
|
|
+ "\t\t\t(zero_extend:DI (match_operand:SI 1 \"register_operand\" \"0\"))\n"
|
|
+ "\t\t\t(zero_extend:DI (match_operand:SI 2 \"zip_opb_operand_p\" \"rO\")))\n"
|
|
+ "\t\t\t(const_int 32))))",
|
|
+ "(ZIP_HAS_DI)",
|
|
+ "(set (match_dup 0)\n"
|
|
+ "\t\t(truncate:SI (ashiftrt:DI (mult:DI\n"
|
|
+ "\t\t\t(zero_extend:DI (match_dup 1))\n"
|
|
+ "\t\t\t(zero_extend:DI (match_dup 2)))\n"
|
|
+ "\t\t\t(const_int 32))))",
|
|
+ //
|
|
+ "(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
|
|
+ "\t\t(truncate:SI (ashiftrt:DI (mult:DI\n"
|
|
+ "\t\t\t(zero_extend:DI (match_dup 0))\n"
|
|
+ "\t\t\t(zero_extend:DI (match_operand:SI 1 \"zip_opb_operand_p\" \"rO\")))\n"
|
|
+ "\t\t\t(const_int 32))))",
|
|
+ "MPYUHI");
|
|
+
|
|
+ gen_heading(fp, "Conditional move instructions");
|
|
+
|
|
+ gencmov(fp, "cmov", "eq", "Z");
|
|
+ gencmov(fp, "cmov", "ne", "NZ");
|
|
+ gencmov(fp, "cmov", "lt", "LT");
|
|
+ gencmov(fp, "cmov", "ge", "GE");
|
|
+ gencmov(fp, "cmov", "ltu", "C");
|
|
+ gencmov(fp, "cmov", "geu", "NC");
|
|
+
|
|
+ gen_heading(fp, "Conditional add instructions");
|
|
+
|
|
+ gencadd(fp, "cadd", "eq", "Z");
|
|
+ gencadd(fp, "cadd", "ne", "NZ");
|
|
+ gencadd(fp, "cadd", "lt", "LT");
|
|
+ gencadd(fp, "cadd", "ge", "GE");
|
|
+ gencadd(fp, "cadd", "ltu", "C");
|
|
+ gencadd(fp, "cadd", "geu", "NC");
|
|
+
|
|
+ gen_heading(fp, "Conditional negate instructions");
|
|
+
|
|
+ gencneg(fp, "cneg", "eq", "Z");
|
|
+ gencneg(fp, "cneg", "ne", "NZ");
|
|
+ gencneg(fp, "cneg", "lt", "LT");
|
|
+ gencneg(fp, "cneg", "ge", "GE");
|
|
+ gencneg(fp, "cneg", "ltu", "C");
|
|
+ gencneg(fp, "cneg", "geu", "NC");
|
|
+
|
|
+ gen_heading(fp, "Conditional not instructions");
|
|
+
|
|
+ gencnot(fp, "cnot", "eq", "Z");
|
|
+ gencnot(fp, "cnot", "ne", "NZ");
|
|
+ gencnot(fp, "cnot", "lt", "LT");
|
|
+ gencnot(fp, "cnot", "ge", "GE");
|
|
+ gencnot(fp, "cnot", "ltu", "C");
|
|
+ gencnot(fp, "cnot", "geu", "NC");
|
|
+
|
|
+ gen_heading(fp, "Conditional and instructions");
|
|
+
|
|
+ gencand(fp, "cand", "eq", "Z");
|
|
+ gencand(fp, "cand", "ne", "NZ");
|
|
+ gencand(fp, "cand", "lt", "LT");
|
|
+ gencand(fp, "cand", "ge", "GE");
|
|
+ gencand(fp, "cand", "ltu", "C");
|
|
+ gencand(fp, "cand", "geu", "NC");
|
|
+
|
|
+ gen_heading(fp, "Conditional ior instructions");
|
|
+
|
|
+ gencior(fp, "cior", "eq", "Z");
|
|
+ gencior(fp, "cior", "ne", "NZ");
|
|
+ gencior(fp, "cior", "lt", "LT");
|
|
+ gencior(fp, "cior", "ge", "GE");
|
|
+ gencior(fp, "cior", "ltu", "C");
|
|
+ gencior(fp, "cior", "geu", "NC");
|
|
+
|
|
+ gen_heading(fp, "Conditional xor instructions");
|
|
+
|
|
+ gencxor(fp, "cxor", "eq", "Z");
|
|
+ gencxor(fp, "cxor", "ne", "NZ");
|
|
+ gencxor(fp, "cxor", "lt", "LT");
|
|
+ gencxor(fp, "cxor", "ge", "GE");
|
|
+ gencxor(fp, "cxor", "ltu", "C");
|
|
+ gencxor(fp, "cxor", "geu", "NC");
|
|
+
|
|
+ fclose(fp);
|
|
+
|
|
+ if (rename(TMPPATH, newname) != 0) {
|
|
+ fprintf(stderr, "ERR: Could not create %s, leaving results in %s\n", newname, TMPPATH);
|
|
+ exit(EXIT_FAILURE);
|
|
+ } exit(EXIT_SUCCESS);
|
|
+}
|
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip.c gcc-6.2.0-zip/gcc/config/zip/zip.c
|
|
--- gcc-6.2.0/gcc/config/zip/zip.c 1969-12-31 19:00:00.000000000 -0500
|
|
+++ gcc-6.2.0-zip/gcc/config/zip/zip.c 2017-03-07 12:03:18.566583672 -0500
|
|
@@ -0,0 +1,2679 @@
|
+////////////////////////////////////////////////////////////////////////////////
|
+////////////////////////////////////////////////////////////////////////////////
|
+//
|
+//
|
+// Filename: zip.c
|
+// Filename: zip.c
|
+//
|
+//
|
+// Project: Zip CPU backend for the GNU Compiler Collection
|
+// Project: Zip CPU backend for the GNU Compiler Collection
|
| Line 719... |
Line 763... |
+// Creator: Dan Gisselquist, Ph.D.
|
+// Creator: Dan Gisselquist, Ph.D.
|
+// Gisselquist Technology, LLC
|
+// Gisselquist Technology, LLC
|
+//
|
+//
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+////////////////////////////////////////////////////////////////////////////////
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+////////////////////////////////////////////////////////////////////////////////
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+//
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+//
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+// Copyright (C) 2016, Gisselquist Technology, LLC
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+// Copyright (C) 2016-2017, Gisselquist Technology, LLC
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+//
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+//
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+// This program is free software (firmware): you can redistribute it and/or
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+// This program is free software (firmware): you can redistribute it and/or
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+// modify it under the terms of the GNU General Public License as published
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+// modify it under the terms of the GNU General Public License as published
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+// by the Free Software Foundation, either version 3 of the License, or (at
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+// by the Free Software Foundation, either version 3 of the License, or (at
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+// your option) any later version.
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+// your option) any later version.
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| Line 755... |
Line 799... |
+#include "lcm.h"
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+#include "lcm.h"
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+#include "cfgbuild.h"
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+#include "cfgbuild.h"
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+#include "cfgcleanup.h"
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+#include "cfgcleanup.h"
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+#include "predict.h"
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+#include "predict.h"
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+#include "basic-block.h"
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+#include "basic-block.h"
|
|
+#include "bitmap.h"
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+#include "df.h"
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+#include "df.h"
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+#include "hashtab.h"
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+#include "hashtab.h"
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+#include "hash-set.h"
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+#include "hash-set.h"
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+#include "machmode.h"
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+#include "machmode.h"
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+#include "symtab.h"
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+#include "symtab.h"
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| Line 782... |
Line 827... |
+#include "langhooks.h"
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+#include "langhooks.h"
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+#include "optabs.h"
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+#include "optabs.h"
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+#include "explow.h"
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+#include "explow.h"
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+#include "emit-rtl.h"
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+#include "emit-rtl.h"
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+#include "ifcvt.h"
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+#include "ifcvt.h"
|
|
+#include "genrtl.h"
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+
|
+
|
+// #include "tmp_p.h"
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+// #include "tmp_p.h"
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+#include "target.h"
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+#include "target.h"
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+#include "target-def.h"
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+#include "target-def.h"
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+// #include "tm-constrs.h"
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+// #include "tm-constrs.h"
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| Line 794... |
Line 840... |
+#include "diagnostic.h"
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+#include "diagnostic.h"
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+// #include "integrate.h"
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+// #include "integrate.h"
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+
|
+
|
+#include "zip-protos.h"
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+#include "zip-protos.h"
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+
|
+
|
+// static int zip_arg_partial_bytes(CUMULATIVE_ARGS *, enum machine_mode, tree, bool);
|
|
+// static bool zip_pass_by_reference(CUMULATIVE_ARGS *, enum machine_mode, const_tree, bool);
|
|
+static bool zip_return_in_memory(const_tree, const_tree);
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+static bool zip_return_in_memory(const_tree, const_tree);
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+static bool zip_frame_pointer_required(void);
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+static bool zip_frame_pointer_required(void);
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+
|
+
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+static void zip_function_arg_advance(cumulative_args_t ca, enum machine_mode mode,
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+static void zip_function_arg_advance(cumulative_args_t ca, enum machine_mode mode,
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+ const_tree type, bool named);
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+ const_tree type, bool named);
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| Line 832... |
Line 876... |
+static void zip_override_options(void);
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+static void zip_override_options(void);
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+static bool zip_can_eliminate(int from ATTRIBUTE_UNUSED, int to);
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+static bool zip_can_eliminate(int from ATTRIBUTE_UNUSED, int to);
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+static int zip_memory_move_cost(machine_mode, reg_class_t, bool);
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+static int zip_memory_move_cost(machine_mode, reg_class_t, bool);
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+static rtx zip_legitimize_address(rtx x, rtx oldx, machine_mode mode);
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+static rtx zip_legitimize_address(rtx x, rtx oldx, machine_mode mode);
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+static bool zip_cannot_modify_jumps_p(void);
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+static bool zip_cannot_modify_jumps_p(void);
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+#ifdef HAVE_cc0
|
|
+ void zip_update_cc_notice(rtx exp, rtx_insn *insn);
|
|
+#error "We're not supposed to have CC0 anymore"
|
|
+#else
|
|
+static bool zip_fixed_condition_code_regs(unsigned int *a, unsigned int *b);
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+static bool zip_fixed_condition_code_regs(unsigned int *a, unsigned int *b);
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+#endif
|
|
+
|
+
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+
|
+
|
+#define ALL_DEBUG_OFF false
|
+#define ZIP_ALL_DEBUG_OFF false
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+#define ALL_DEBUG_ON false
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+#define ZIP_ALL_DEBUG_ON false
|
|
+#define ZIPDEBUGFLAG(A,B) const bool A = \
|
|
+ ((ZIP_ALL_DEBUG_ON)||(B))&&(!ZIP_ALL_DEBUG_OFF)
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+
|
+
|
+enum ZIP_BUILTIN_ID_CODE {
|
+enum ZIP_BUILTIN_ID_CODE {
|
+ ZIP_BUILTIN_RTU,
|
+ ZIP_BUILTIN_RTU,
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+ ZIP_BUILTIN_HALT,
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+ ZIP_BUILTIN_HALT,
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+ ZIP_BUILTIN_IDLE,
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+ ZIP_BUILTIN_IDLE,
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| Line 860... |
Line 901... |
+};
|
+};
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+
|
+
|
+static GTY (()) tree zip_builtins[(int)ZIP_BUILTIN_MAX];
|
+static GTY (()) tree zip_builtins[(int)ZIP_BUILTIN_MAX];
|
+static enum insn_code zip_builtins_icode[(int)ZIP_BUILTIN_MAX];
|
+static enum insn_code zip_builtins_icode[(int)ZIP_BUILTIN_MAX];
|
+
|
+
|
|
+#undef TARGET_ASM_ALIGNED_HI_OP
|
|
+#undef TARGET_ASM_ALIGNED_SI_OP
|
|
+#undef TARGET_ASM_ALIGNED_DI_OP
|
|
+#define TARGET_ASM_ALIGNED_HI_OP "\t.short\t"
|
|
+#define TARGET_ASM_ALIGNED_SI_OP "\t.int\t"
|
|
+#define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
|
|
+
|
|
+#undef TARGET_ASM_UNALIGNED_HI_OP
|
|
+#undef TARGET_ASM_UNALIGNED_SI_OP
|
|
+#undef TARGET_ASM_UNALIGNED_DI_OP
|
|
+#define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
|
|
+#define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
|
|
+#define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
|
+
|
+
|
+#include "gt-zip.h"
|
+#include "gt-zip.h"
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+
|
+
|
+/* The Global 'targetm' Variable. */
|
+/* The Global 'targetm' Variable. */
|
+struct gcc_target targetm = TARGET_INITIALIZER;
|
+struct gcc_target targetm = TARGET_INITIALIZER;
|
| Line 920... |
Line 974... |
+
|
+
|
+/* Worker function for TARGET_RETURN_IN_MEMORY. */
|
+/* Worker function for TARGET_RETURN_IN_MEMORY. */
|
+static bool
|
+static bool
|
+zip_return_in_memory(const_tree type, const_tree fntype ATTRIBUTE_UNUSED) {
|
+zip_return_in_memory(const_tree type, const_tree fntype ATTRIBUTE_UNUSED) {
|
+ const HOST_WIDE_INT size = int_size_in_bytes(type);
|
+ const HOST_WIDE_INT size = int_size_in_bytes(type);
|
+ return (size == -1)||(size > UNITS_PER_WORD);
|
+ return (size == -1)||(size > 2*UNITS_PER_WORD);
|
+}
|
+}
|
+
|
+
|
+/* Emit an error emssage when we're in an asm, and a fatal error for "normal"
|
+/* Emit an error emssage when we're in an asm, and a fatal error for "normal"
|
+ * insn. Formatted output isn't easily implemented, since we use output operand
|
+ * insn. Formatted output isn't easily implemented, since we use output operand
|
+ * lossage to output the actual message and handle the categorization of the
|
+ * lossage to output the actual message and handle the categorization of the
|
+ * error. */
|
+ * error. */
|
+
|
+
|
+static void
|
+static void
|
+zip_operand_lossage(const char *msgid, rtx op) {
|
+zip_operand_lossage(const char *msgid, rtx op) {
|
+ fprintf(stderr, "Operand lossage??\n");
|
|
+ debug_rtx(op);
|
+ debug_rtx(op);
|
+ zip_debug_rtx(op);
|
+ zip_debug_rtx(op);
|
+ output_operand_lossage("%s", msgid);
|
+ output_operand_lossage("%s", msgid);
|
+}
|
+}
|
+
|
+
|
+/* The PRINT_OPERAND_ADDRESS worker. */
|
+/* The PRINT_OPERAND_ADDRESS worker. */
|
+void
|
+void
|
+zip_print_operand_address(FILE *file, rtx x) {
|
+zip_print_operand_address(FILE *file, rtx x) {
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
+ ZIPDEBUGFLAG(dbg, false);
|
+
|
+
|
+ if (dbg) zip_debug_rtx(x);
|
+ if (dbg) zip_debug_rtx(x);
|
+ switch(GET_CODE(x)) {
|
+ switch(GET_CODE(x)) {
|
+ case REG:
|
+ case REG:
|
+ gcc_assert(is_ZIP_REG(REGNO(x)));
|
+ gcc_assert(is_ZIP_REG(REGNO(x)));
|
| Line 1090... |
Line 1143... |
+ if (CONSTANT_P(operand)) {
|
+ if (CONSTANT_P(operand)) {
|
+ output_addr_const(file, operand);
|
+ output_addr_const(file, operand);
|
+ return;
|
+ return;
|
+ }
|
+ }
|
+
|
+
|
|
+ zip_debug_rtx(x);
|
+ LOSE_AND_RETURN("unexpected operand", x);
|
+ LOSE_AND_RETURN("unexpected operand", x);
|
+ }
|
+ }
|
+}
|
+}
|
+
|
+
|
+static bool
|
+static bool
|
| Line 1105... |
Line 1159... |
+ // it.
|
+ // it.
|
+ //
|
+ //
|
+ // Use a GCC global to determine our answer
|
+ // Use a GCC global to determine our answer
|
+ if (cfun->calls_alloca)
|
+ if (cfun->calls_alloca)
|
+ return true;
|
+ return true;
|
|
+
|
|
+ // If the stack frame is too large to access saved registers with
|
|
+ // immediate offsets, then we *must* use a frame pointer
|
|
+ unsigned stack_size = 36;
|
|
+ stack_size += (ACCUMULATE_OUTGOING_ARGS ? crtl->outgoing_args_size : 0);
|
|
+
|
|
+ //
|
|
+ // if cfun->machine->size_for_adjusting_sp might ever be larger than
|
|
+ // zip_max_anchor_offset, then we MUST have a frame pointer.
|
|
+ //
|
|
+ // cfun->machine->size_for_adjusting_sp =
|
|
+ // get_frame_size
|
|
+ // + saved_reg_size (will always be <= 36)
|
|
+ // + outgoing_args_size;
|
|
+ // + pretend_args_size;
|
|
+
|
|
+ if(crtl->args.pretend_args_size > 0)
|
|
+ stack_size += crtl->args.pretend_args_size;
|
|
+ stack_size += get_frame_size();
|
|
+ // Align our attempted stack size
|
|
+ stack_size = ((stack_size+3)&-4);
|
|
+
|
|
+ // Now here's our test
|
|
+ if (stack_size >= zip_max_anchor_offset)
|
|
+ return true;
|
+ return (frame_pointer_needed);
|
+ return (frame_pointer_needed);
|
+/*
|
+/*
|
+*/
|
+*/
|
+}
|
+}
|
+
|
+
|
| Line 1154... |
Line 1233... |
+ */
|
+ */
|
+static void
|
+static void
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+zip_compute_frame(void) {
|
+zip_compute_frame(void) {
|
+ int regno;
|
+ int regno;
|
+ int args_size;
|
+ int args_size;
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
+ ZIPDEBUGFLAG(dbg, false);
|
+
|
+
|
+ if (dbg) fprintf(stderr, "ZIP-COMPUTE-FRAME: %s\n", current_function_name());
|
+ if (dbg) fprintf(stderr, "ZIP-COMPUTE-FRAME: %s\n", current_function_name());
|
+ // gcc_assert(crtl);
|
+ // gcc_assert(crtl);
|
+ gcc_assert(cfun);
|
+ gcc_assert(cfun);
|
+ gcc_assert(cfun->machine);
|
+ gcc_assert(cfun->machine);
|
| Line 1172... |
Line 1251... |
+ cfun->machine->pretend_size = crtl->args.pretend_args_size;
|
+ cfun->machine->pretend_size = crtl->args.pretend_args_size;
|
+ }
|
+ }
|
+
|
+
|
+ cfun->machine->local_vars_size = get_frame_size();
|
+ cfun->machine->local_vars_size = get_frame_size();
|
+
|
+
|
|
+ // Force frame alignment of the local variable section
|
|
+ cfun->machine->local_vars_size += 3;
|
|
+ cfun->machine->local_vars_size &= -4;
|
|
+
|
+ // Save callee-saved registers.
|
+ // Save callee-saved registers.
|
+ cfun->machine->saved_reg_size = 0;
|
+ cfun->machine->saved_reg_size = 0;
|
+ for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) {
|
+ for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) {
|
+ if (zip_save_reg(regno))
|
+ if (zip_save_reg(regno))
|
+ cfun->machine->saved_reg_size ++;
|
+ cfun->machine->saved_reg_size += 4;
|
+ }
|
+ }
|
+
|
+
|
+ cfun->machine->fp_needed = (zip_frame_pointer_required());
|
+ cfun->machine->fp_needed = (zip_frame_pointer_required());
|
+
|
+
|
+ if ((cfun->machine->fp_needed)&&
|
+ if ((cfun->machine->fp_needed)&&
|
+ (!df_regs_ever_live_p(zip_FP))) {
|
+ (!df_regs_ever_live_p(zip_FP))) {
|
+ cfun->machine->saved_reg_size ++;
|
+ cfun->machine->saved_reg_size += 4;
|
+ }
|
+ }
|
+
|
+
|
+ cfun->machine->sp_fp_offset = crtl->outgoing_args_size
|
+ cfun->machine->sp_fp_offset = crtl->outgoing_args_size
|
+ + cfun->machine->local_vars_size;
|
+ + cfun->machine->local_vars_size;
|
+ cfun->machine->size_for_adjusting_sp = cfun->machine->local_vars_size
|
+ cfun->machine->size_for_adjusting_sp = cfun->machine->local_vars_size
|
| Line 1214... |
Line 1297... |
+ cfun->machine->size_for_adjusting_sp);
|
+ cfun->machine->size_for_adjusting_sp);
|
+ }
|
+ }
|
+}
|
+}
|
+
|
+
|
+void
|
+void
|
+zip_expand_prologue(void) {
|
+zip_save_registers(rtx basereg_rtx, int sp_offset_to_first_register) {
|
+ rtx insn;
|
+ rtx insn;
|
|
+ ZIPDEBUGFLAG(dbg, false);
|
+
|
+
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
+ // Compute Frame has already been calculated before coming into here
|
+ zip_compute_frame();
|
+ //
|
+
|
+ // zip_compute_frame();
|
+ if (dbg) fprintf(stderr, "PROLOGUE: Computing Prologue instructions\n");
|
+ if (dbg) fprintf(stderr, "PROLOGUE::SAVE-REGISTER\n");
|
+ if (dbg) fprintf(stderr, "PROLOGUE: SP-FP offset is %d\n",
|
|
+ cfun->machine->sp_fp_offset);
|
|
+ if (cfun->machine->size_for_adjusting_sp != 0) {
|
|
+ insn = emit_insn(gen_subsi3_reg_clobber(stack_pointer_rtx,
|
|
+ stack_pointer_rtx,
|
|
+ gen_int_mode(cfun->machine->size_for_adjusting_sp,
|
|
+ SImode)));
|
|
+ // cfun->machine->sp_fp_offset
|
|
+
|
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
|
+ }
|
|
+
|
+
|
+ {
|
|
+ int offset = 0, regno;
|
+ int offset = 0, regno;
|
+ for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) {
|
+ for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) {
|
+ if (zip_save_reg(regno)) {
|
+ if (zip_save_reg(regno)) {
|
+ if (dbg) fprintf(stderr,
|
+ if (dbg) fprintf(stderr,
|
+ "PROLOGUE: Saving R%d in %d+%d(SP)\n",
|
+ "PROLOGUE::SAVE-REGISTER Saving R%d in %d+%d(SP)\n",
|
+ regno, cfun->machine->sp_fp_offset,
|
+ regno, sp_offset_to_first_register, offset);
|
+ offset);
|
|
+ insn=emit_insn(gen_movsi_sto_off(
|
+ insn=emit_insn(gen_movsi_sto_off(
|
+ stack_pointer_rtx,
|
+ basereg_rtx,
|
+ GEN_INT(cfun->machine->sp_fp_offset
|
+ GEN_INT(sp_offset_to_first_register +offset),
|
+ +offset++),
|
|
+ gen_rtx_REG(SImode, regno)));
|
+ gen_rtx_REG(SImode, regno)));
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
|
+ offset += 4;
|
+ }
|
+ }
|
+ }
|
+ } if (dbg) fprintf(stderr, "%d registers saved%s\n", offset,
|
+ if (dbg) fprintf(stderr, "%d registers saved%s\n", offset,
|
|
+ (crtl->saves_all_registers)?", should be all of them":", less than all");
|
+ (crtl->saves_all_registers)?", should be all of them":", less than all");
|
|
+
|
+ }
|
+ }
|
+
|
+
|
|
+/*
|
|
+ * zip_expand_small_prologue()
|
|
+ *
|
|
+ * To be used when the sp_fp_offset is less then zip_max_opb_offset.
|
|
+ *
|
|
+ *
|
|
+ * Approach:
|
|
+ * SUB size_for_adjusting_sp,SP
|
|
+ * SW REG,0(SP)
|
|
+ * SW REG,4(SP)
|
|
+ * SW REG,8(SP)
|
|
+ * ....
|
|
+ * SW REG,#(SP)
|
|
+ *
|
|
+ * and if we need a frame register, we'll either do ...
|
|
+ * MOV sp_fp_offset+SP,FP
|
|
+ * or if the offset is too large, we'll do ...
|
|
+ * MOV SP,FP
|
|
+ * ADD sp_fp_offset,FP
|
|
+ *
|
|
+ */
|
|
+void
|
|
+zip_expand_small_prologue(void) {
|
|
+ ZIPDEBUGFLAG(dbg, false);
|
|
+ rtx insn;
|
|
+
|
|
+ zip_compute_frame();
|
|
+
|
|
+ if (dbg) fprintf(stderr, "PROLOGUE:::EXPAND-SMALL-PROLOGUE(SP-FP offset is %d)\n",
|
|
+ cfun->machine->sp_fp_offset);
|
|
+
|
|
+ insn = emit_insn(gen_subsi3(stack_pointer_rtx, stack_pointer_rtx,
|
|
+ gen_int_mode(cfun->machine->size_for_adjusting_sp,
|
|
+ SImode)));
|
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
|
+
|
|
+ zip_save_registers(stack_pointer_rtx, cfun->machine->sp_fp_offset);
|
|
+
|
+ if (cfun->machine->fp_needed) {
|
+ if (cfun->machine->fp_needed) {
|
|
+ if (dbg) fprintf(stderr, "PROLOGUE:::EXPAND-SMALL-PROLOGUE(FP-NEEDED)\n");
|
+ if (dbg) zip_debug_rtx(stack_pointer_rtx);
|
+ if (dbg) zip_debug_rtx(stack_pointer_rtx);
|
+ if (dbg) zip_debug_rtx(frame_pointer_rtx);
|
+ if (dbg) zip_debug_rtx(frame_pointer_rtx);
|
|
+ if (cfun->machine->sp_fp_offset < zip_max_mov_offset) {
|
|
+ if (dbg) fprintf(stderr,
|
|
+ "PROLOGUE:::EXPAND-SMALL-PROLOGUE() "
|
|
+ "gen_movsi_reg_off(FP, SP, %d), %d < %ld\n",
|
|
+ cfun->machine->sp_fp_offset,
|
|
+ cfun->machine->sp_fp_offset,
|
|
+ zip_max_mov_offset);
|
+ insn = emit_insn(gen_movsi_reg_off(frame_pointer_rtx,
|
+ insn = emit_insn(gen_movsi_reg_off(frame_pointer_rtx,
|
+ stack_pointer_rtx,
|
+ stack_pointer_rtx,
|
+ GEN_INT(cfun->machine->sp_fp_offset)));
|
+ GEN_INT(cfun->machine->sp_fp_offset)));
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
+ if (dbg) fprintf(stderr, "sp_fp_offset is %d\n", cfun->machine->sp_fp_offset);
|
+ } else {
|
|
+ rtx fp_rtx;
|
|
+
|
|
+ fp_rtx = gen_rtx_REG(SImode, zip_FP);
|
|
+
|
|
+ insn = emit_insn(gen_movsi(fp_rtx, stack_pointer_rtx));
|
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
|
+
|
|
+ insn = emit_insn(gen_addsi3(fp_rtx, fp_rtx,
|
|
+ GEN_INT(cfun->machine->sp_fp_offset)));
|
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
|
+ }
|
|
+ }
|
|
+}
|
|
+
|
|
+/*
|
|
+ * zip_expand_large_prologue()
|
|
+ *
|
|
+ * The prologue function will be called when the size_for_adjusting_sp is too
|
|
+ * large to fit into a single OPB-immediate as part of a subtract.
|
|
+ *
|
|
+ * Approach:
|
|
+ * SUB (size_for_adjusting_sp-sp_fp_offset),SP
|
|
+ * SW R0,(SP)
|
|
+ * SW R5,4(SP)
|
|
+ * SW R6,8SP)
|
|
+ * SW R7,(SP)
|
|
+ * ...
|
|
+ * SW FP,(SP)
|
|
+ *
|
|
+ * LDI sp_fp_offset,FP
|
|
+ * SUB FP,SP
|
|
+ * ADD SP,FP
|
|
+ */
|
|
+void
|
|
+zip_expand_large_prologue(void) {
|
|
+ ZIPDEBUGFLAG(dbg, false);
|
|
+ rtx insn, fp_rtx;
|
|
+
|
|
+ gcc_assert(cfun->machine->fp_needed);
|
|
+
|
|
+ if (dbg) fprintf(stderr, "PROLOGUE::expand-large(%d-%d)\n",
|
|
+ cfun->machine->size_for_adjusting_sp,
|
|
+ cfun->machine->sp_fp_offset);
|
|
+ insn = emit_insn(gen_subsi3(stack_pointer_rtx, stack_pointer_rtx,
|
|
+ gen_int_mode(cfun->machine->size_for_adjusting_sp
|
|
+ -cfun->machine->sp_fp_offset, SImode)));
|
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
|
+
|
|
+ zip_save_registers(stack_pointer_rtx, 0);
|
|
+
|
|
+ fp_rtx = gen_rtx_REG(SImode, zip_FP);
|
|
+
|
|
+ insn = emit_insn(gen_movsi(fp_rtx,
|
|
+ gen_int_mode(cfun->machine->sp_fp_offset, SImode)));
|
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
|
+
|
|
+ insn = emit_insn(gen_subsi3(stack_pointer_rtx, stack_pointer_rtx,
|
|
+ fp_rtx));
|
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
|
+
|
|
+ insn = emit_insn(gen_addsi3(fp_rtx, fp_rtx, stack_pointer_rtx));
|
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
|
+}
|
|
+
|
|
+void
|
|
+zip_expand_prologue(void) {
|
|
+ ZIPDEBUGFLAG(dbg, false);
|
|
+
|
|
+ zip_compute_frame();
|
|
+
|
|
+ if (dbg) fprintf(stderr, "PROLOGUE: Computing Prologue instructions\n");
|
|
+ if (dbg) fprintf(stderr, "PROLOGUE: SP-FP offset is %d\n",
|
|
+ cfun->machine->sp_fp_offset);
|
|
+ if (cfun->machine->size_for_adjusting_sp != 0) {
|
|
+ if (cfun->machine->size_for_adjusting_sp <= zip_max_anchor_offset) {
|
|
+ if (dbg) fprintf(stderr, "PROLOGUE: "
|
|
+ "%d <= %ld, so going small\n",
|
|
+ cfun->machine->size_for_adjusting_sp,
|
|
+ zip_max_opb_imm);
|
|
+ zip_expand_small_prologue();
|
|
+ } else {
|
|
+ zip_expand_large_prologue();
|
|
+ }
|
+ }
|
+ }
|
+}
|
+}
|
+
|
+
|
+int
|
+int
|
+zip_use_return_insn(void)
|
+zip_use_return_insn(void)
|
| Line 1282... |
Line 1482... |
+ zip_compute_frame();
|
+ zip_compute_frame();
|
+ return (cfun->machine->size_for_adjusting_sp == 0)?1:0;
|
+ return (cfun->machine->size_for_adjusting_sp == 0)?1:0;
|
+}
|
+}
|
+
|
+
|
+/* As per the notes in M68k.c, quote the function epilogue should not depend
|
+/* As per the notes in M68k.c, quote the function epilogue should not depend
|
+ * upon the current stack pointer. It should use the frame poitner only,
|
+ * upon the current stack pointer. It should use the frame pointer only,
|
+ * if there is a frame pointer. This is mandatory because of alloca; we also
|
+ * if there is a frame pointer. This is mandatory because of alloca; we also
|
+ * take advantage of it to omit stack adjustments before returning ...
|
+ * take advantage of it to omit stack adjustments before returning ...
|
+ *
|
+ *
|
+ * Let's see if we can use their approach here.
|
+ * Let's see if we can use their approach here.
|
+ *
|
+ *
|
+ * We can't. Consider our choices:
|
+ * We can't. Consider our choices:
|
+ * LOD (FP),R0
|
+ * LW (FP),R0
|
+ * LOD 1(FP),R4
|
+ * LW 4(FP),R4
|
+ * LOD 2(FP),R5
|
+ * LW 8(FP),R5
|
+ * LOD 3(FP),R6
|
+ * LW 12(FP),R6
|
+ * LOD 4(FP),FP
|
+ * LW 16(FP),FP
|
+ * ... Then what is the stack pointer?
|
+ * ... Then what is the stack pointer?
|
+ * or
|
+ * or
|
+ * LOD (FP),R0
|
+ * LW (FP),R0
|
+ * LOD 1(FP),R4
|
+ * LW 4(FP),R4
|
+ * LOD 2(FP),R5
|
+ * LW 8(FP),R5
|
+ * LOD 3(FP),R6
|
+ * LW 12(FP),R6
|
+ * MOV FP,SP
|
+ * MOV FP,SP
|
+ * LOD 4(SP),FP
|
+ * LW 16(SP),FP
|
+ * ... Which suffers unnecessary pipeline stalls, and certainly doesn't
|
+ * ... Which suffers unnecessary pipeline stalls, and certainly doesn't
|
+ * exploit our pipeline memory function
|
+ * exploit our pipeline memory function
|
+ * or
|
+ * or
|
+ * MOV FP,SP
|
+ * MOV FP,SP
|
+ * LOD (SP),R0
|
+ * LW (SP),R0
|
+ * LOD 1(SP),R4
|
+ * LW 4(SP),R4
|
+ * LOD 2(SP),R5
|
+ * LW 8(SP),R5
|
+ * LOD 3(SP),R6
|
+ * LW 12(SP),R6
|
+ * LOD 4(SP),FP
|
+ * LW 16(SP),FP
|
+ * Which will be our choice. Note that we do use the stack pointer, eventually.
|
+ * Which will be our choice. Note that we do use the stack pointer, eventually.
|
+ *
|
+ *
|
+ */
|
+ */
|
+void
|
+void
|
+zip_expand_epilogue(void) {
|
+zip_expand_epilogue(void) {
|
+ int regno, offset;
|
+ int regno, offset;
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
+ ZIPDEBUGFLAG(dbg, false);
|
+ rtx insn;
|
+ rtx insn;
|
+
|
+
|
+ zip_compute_frame();
|
+ zip_compute_frame();
|
+
|
+
|
+ if (dbg) fprintf(stderr, "EPILOG::\n");
|
+ if (dbg) fprintf(stderr, "EPILOG::\n");
|
| Line 1330... |
Line 1530... |
+ // enough so that you must have a frame pointer, then you can't
|
+ // enough so that you must have a frame pointer, then you can't
|
+ // trust its offset enough to restore from it. Hence, we start
|
+ // trust its offset enough to restore from it. Hence, we start
|
+ // by moving the frame pointer to the stack pointer to recover
|
+ // by moving the frame pointer to the stack pointer to recover
|
+ // the stack pointer back to a usable value.
|
+ // the stack pointer back to a usable value.
|
+ if (dbg) fprintf(stderr, "EPILOG::Moving frame pointer to stack register\n");
|
+ if (dbg) fprintf(stderr, "EPILOG::Moving frame pointer to stack register\n");
|
+ insn = emit_insn(gen_movsi_reg(stack_pointer_rtx, frame_pointer_rtx));
|
+ insn = emit_insn(gen_movsi_raw(stack_pointer_rtx, frame_pointer_rtx));
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
+ }
|
+ }
|
+
|
+
|
+ if (cfun->machine->saved_reg_size != 0) {
|
+ if (cfun->machine->saved_reg_size != 0) {
|
+ if (cfun->machine->fp_needed)
|
+ if (cfun->machine->fp_needed)
|
| Line 1342... |
Line 1542... |
+ else
|
+ else
|
+ offset = cfun->machine->sp_fp_offset;
|
+ offset = cfun->machine->sp_fp_offset;
|
+ if (dbg) fprintf(stderr, "EPILOG::Saved_REG_Size = %d\n", cfun->machine->saved_reg_size);
|
+ if (dbg) fprintf(stderr, "EPILOG::Saved_REG_Size = %d\n", cfun->machine->saved_reg_size);
|
+ for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) {
|
+ for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) {
|
+ if (zip_save_reg(regno)) {
|
+ if (zip_save_reg(regno)) {
|
+ if (dbg) fprintf(stderr, "EPILOG::RESTORING R%d\n", regno);
|
+ if (dbg) fprintf(stderr, "EPILOG::RESTORING R%d from SP+%d\n", regno, offset);
|
+ rtx reg = gen_rtx_REG(SImode, regno);
|
+ rtx reg = gen_rtx_REG(SImode, regno);
|
+ insn = emit_insn(gen_movsi_lod_off(
|
+ insn = emit_insn(gen_movsi_lod_off(
|
+ reg,
|
+ reg,
|
+ stack_pointer_rtx,
|
+ stack_pointer_rtx,
|
+ GEN_INT(offset++)));
|
+ GEN_INT(offset)));
|
+ add_reg_note(insn, REG_CFA_RESTORE, reg);
|
+ add_reg_note(insn, REG_CFA_RESTORE, reg);
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
|
+ offset += 4;
|
+ }
|
+ }
|
+ }
|
+ }
|
+ }
|
+ }
|
+
|
+
|
+ if (cfun->machine->fp_needed) {
|
+ if (cfun->machine->fp_needed) {
|
+ // Restore the stack pointer back to the original, the
|
+ // Restore the stack pointer back to the original, the
|
+ // difference being the difference from the frame pointer
|
+ // difference being the difference from the frame pointer
|
+ // to the original stack
|
+ // to the original stack
|
+ insn = emit_insn(gen_addsi3_reg_clobber(stack_pointer_rtx,
|
+ insn = emit_insn(gen_addsi3(stack_pointer_rtx,
|
+ stack_pointer_rtx,
|
+ stack_pointer_rtx,
|
+ GEN_INT(cfun->machine->size_for_adjusting_sp
|
+ GEN_INT(cfun->machine->size_for_adjusting_sp
|
+ -cfun->machine->sp_fp_offset)));
|
+ -cfun->machine->sp_fp_offset)));
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
+ } else {
|
+ } else {
|
+ // else now the difference is between the stack pointer and
|
+ // else now the difference is between the stack pointer and
|
+ // the original stack pointer.
|
+ // the original stack pointer.
|
+ if (dbg) fprintf(stderr, "EPILOG::ADDSI3(StackPtr, %d)\n",
|
+ if (dbg) fprintf(stderr, "EPILOG::ADDSI3(StackPtr, %d)\n",
|
+ cfun->machine->size_for_adjusting_sp);
|
+ cfun->machine->size_for_adjusting_sp);
|
+ insn = emit_insn(gen_addsi3_reg_clobber(stack_pointer_rtx,
|
+ insn = emit_insn(gen_addsi3(stack_pointer_rtx, stack_pointer_rtx,
|
+ stack_pointer_rtx,
|
|
+ GEN_INT(cfun->machine->size_for_adjusting_sp)));
|
+ GEN_INT(cfun->machine->size_for_adjusting_sp)));
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
+ }
|
+ }
|
+ if (dbg) fprintf(stderr, "EPILOG::EMITTING-RETURN\n");
|
+ if (dbg) fprintf(stderr, "EPILOG::EMITTING-RETURN\n");
|
+
|
+
|
| Line 1383... |
Line 1583... |
+}
|
+}
|
+
|
+
|
+void
|
+void
|
+zip_sibcall_epilogue(void) {
|
+zip_sibcall_epilogue(void) {
|
+ int regno, offset;
|
+ int regno, offset;
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
+ ZIPDEBUGFLAG(dbg, false);
|
+ rtx insn;
|
+ rtx insn;
|
+
|
+
|
+ zip_compute_frame();
|
+ zip_compute_frame();
|
+
|
+
|
+ if (dbg) fprintf(stderr, "EPILOG::\n");
|
+ if (dbg) fprintf(stderr, "EPILOG::\n");
|
| Line 1396... |
Line 1596... |
+ // enough so that you must have a frame pointer, then you can't
|
+ // enough so that you must have a frame pointer, then you can't
|
+ // trust its offset enough to restore from it. Hence, we start
|
+ // trust its offset enough to restore from it. Hence, we start
|
+ // by moving the frame pointer to the stack pointer to recover
|
+ // by moving the frame pointer to the stack pointer to recover
|
+ // the stack pointer back to a usable value.
|
+ // the stack pointer back to a usable value.
|
+ if (dbg) fprintf(stderr, "SIBCALL-EPILOG::Moving frame pointer to stack register\n");
|
+ if (dbg) fprintf(stderr, "SIBCALL-EPILOG::Moving frame pointer to stack register\n");
|
+ insn = emit_insn(gen_movsi_reg(stack_pointer_rtx, frame_pointer_rtx));
|
+ insn = emit_insn(gen_movsi_raw(stack_pointer_rtx, frame_pointer_rtx));
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
+ }
|
+ }
|
+
|
+
|
+ if (cfun->machine->saved_reg_size != 0) {
|
+ if (cfun->machine->saved_reg_size != 0) {
|
+ if (cfun->machine->fp_needed)
|
+ if (cfun->machine->fp_needed)
|
| Line 1413... |
Line 1613... |
+ if (dbg) fprintf(stderr, "SIBCALL-EPILOG::RESTORING R%d\n", regno);
|
+ if (dbg) fprintf(stderr, "SIBCALL-EPILOG::RESTORING R%d\n", regno);
|
+ rtx reg = gen_rtx_REG(SImode, regno);
|
+ rtx reg = gen_rtx_REG(SImode, regno);
|
+ insn = emit_insn(gen_movsi_lod_off(
|
+ insn = emit_insn(gen_movsi_lod_off(
|
+ reg,
|
+ reg,
|
+ stack_pointer_rtx,
|
+ stack_pointer_rtx,
|
+ GEN_INT(offset++)));
|
+ GEN_INT(offset)));
|
+ add_reg_note(insn, REG_CFA_RESTORE, reg);
|
+ add_reg_note(insn, REG_CFA_RESTORE, reg);
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
|
+ offset += 4;
|
+ }
|
+ }
|
+ }
|
+ }
|
+ }
|
+ }
|
+
|
+
|
+ if (cfun->machine->fp_needed) {
|
+ if (cfun->machine->fp_needed) {
|
+ // Restore the stack pointer back to the original, the
|
+ // Restore the stack pointer back to the original, the
|
+ // difference being the difference from the frame pointer
|
+ // difference being the difference from the frame pointer
|
+ // to the original stack
|
+ // to the original stack
|
+ insn = emit_insn(gen_addsi3_reg_clobber(stack_pointer_rtx,
|
+ insn = emit_insn(gen_addsi3(stack_pointer_rtx, stack_pointer_rtx,
|
+ stack_pointer_rtx,
|
|
+ GEN_INT(cfun->machine->size_for_adjusting_sp
|
+ GEN_INT(cfun->machine->size_for_adjusting_sp
|
+ -cfun->machine->sp_fp_offset)));
|
+ -cfun->machine->sp_fp_offset)));
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
+ } else {
|
+ } else {
|
+ // else now the difference is between the stack pointer and
|
+ // else now the difference is between the stack pointer and
|
+ // the original stack pointer.
|
+ // the original stack pointer.
|
+ if (dbg) fprintf(stderr, "SIBCALL-EPILOG::ADDSI3(StackPtr, %d)\n",
|
+ if (dbg) fprintf(stderr, "SIBCALL-EPILOG::ADDSI3(StackPtr, %d)\n",
|
+ cfun->machine->size_for_adjusting_sp);
|
+ cfun->machine->size_for_adjusting_sp);
|
+ insn = emit_insn(gen_addsi3_reg_clobber(stack_pointer_rtx,
|
+ insn = emit_insn(gen_addsi3(stack_pointer_rtx,stack_pointer_rtx,
|
+ stack_pointer_rtx,
|
|
+ GEN_INT(cfun->machine->size_for_adjusting_sp)));
|
+ GEN_INT(cfun->machine->size_for_adjusting_sp)));
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
+ }
|
+ }
|
+}
|
+}
|
+
|
+
|
|
+rtx
|
|
+zip_return_addr_rtx(int count, rtx frame ATTRIBUTE_UNUSED)
|
|
+{
|
|
+ //
|
|
+ // Don't try to compute anything other than frame zero.
|
|
+ //
|
|
+ if (count != 0)
|
|
+ return NULL_RTX;
|
|
+
|
|
+ // Make sure we've computed our frame, do we need to save registers?
|
|
+ zip_compute_frame();
|
|
+
|
|
+ if (zip_save_reg(zip_LR)) {
|
|
+ if (cfun->machine->fp_needed)
|
|
+ return gen_rtx_MEM(SImode, frame_pointer_rtx);
|
|
+ else
|
|
+ return gen_rtx_MEM(SImode, gen_rtx_PLUS(Pmode,
|
|
+ stack_pointer_rtx,
|
|
+ GEN_INT(cfun->machine->sp_fp_offset)));
|
|
+ } else {
|
|
+ return gen_rtx_REG(Pmode, zip_LR);
|
|
+
|
|
+ }
|
|
+}
|
|
+
|
+/* Implement RETURN_ADDR_RTX(COUNT, FRAMEADDR).
|
+/* Implement RETURN_ADDR_RTX(COUNT, FRAMEADDR).
|
+ *
|
+ *
|
+ * We currently only support calculating the return address for the current
|
+ * We currently only support calculating the return address for the current
|
+ * frame.
|
+ * frame.
|
+ */
|
+ */
|
| Line 1521... |
Line 1745... |
+ if ((from == zip_FP)&&(to == zip_SP))
|
+ if ((from == zip_FP)&&(to == zip_SP))
|
+ return !cfun->machine->fp_needed;
|
+ return !cfun->machine->fp_needed;
|
+ return true;
|
+ return true;
|
+}
|
+}
|
+
|
+
|
+/*
|
|
+static void
|
|
+zip_basic_check(void)
|
|
+{
|
|
+ gcc_assert(mode_base_align[SImode]==4);
|
|
+ if ((BITS_PER_UNIT != 32)
|
|
+ ||(GET_MODE_SIZE(SImode)!=1)
|
|
+ ||(GET_MODE_SIZE(DImode)!=1)
|
|
+ ||(HARD_REGNO_NREGS(0,SImode)!=1)) {
|
|
+ printf("SIZEOF(SIMode) == %d\n", GET_MODE_SIZE(SImode));
|
|
+ printf("BITS_PER_UNIT == %d\n", BITS_PER_UNIT);
|
|
+ gcc_assert(BITS_PER_UNIT==32);
|
|
+ gcc_assert(GET_MODE_SIZE(SImode)==1);
|
|
+ gcc_assert(HARD_REGNO_NREGS(0,SImode)==1);
|
|
+ }
|
|
+}
|
|
+*/
|
|
+
|
|
+#define zip_basic_check()
|
|
+
|
|
+/* Compute the number of word sized registers needed to hold a function
|
+/* Compute the number of word sized registers needed to hold a function
|
+ * argument of mode INT_MODE and tree type TYPE.
|
+ * argument of mode INT_MODE and tree type TYPE.
|
+ */
|
+ */
|
+int
|
+int
|
+zip_num_arg_regs(enum machine_mode mode, const_tree type) {
|
+zip_num_arg_regs(enum machine_mode mode, const_tree type) {
|
+ int size;
|
+ int size;
|
+
|
+
|
+ zip_basic_check();
|
|
+
|
|
+ if (targetm.calls.must_pass_in_stack(mode, type))
|
+ if (targetm.calls.must_pass_in_stack(mode, type))
|
+ return 0;
|
+ return 0;
|
+
|
+
|
+ if ((type)&&(mode == BLKmode))
|
+ if ((type)&&(mode == BLKmode))
|
+ size = int_size_in_bytes(type);
|
+ size = int_size_in_bytes(type);
|
| Line 1567... |
Line 1769... |
+zip_function_arg_advance(cumulative_args_t ca, machine_mode mode,
|
+zip_function_arg_advance(cumulative_args_t ca, machine_mode mode,
|
+ const_tree type, bool named ATTRIBUTE_UNUSED) {
|
+ const_tree type, bool named ATTRIBUTE_UNUSED) {
|
+ CUMULATIVE_ARGS *cum;
|
+ CUMULATIVE_ARGS *cum;
|
+ int nreg;
|
+ int nreg;
|
+
|
+
|
+ zip_basic_check();
|
|
+
|
|
+ cum = get_cumulative_args(ca);
|
+ cum = get_cumulative_args(ca);
|
+ nreg = zip_num_arg_regs(mode, type);
|
+ nreg = zip_num_arg_regs(mode, type);
|
+ if (((*cum)+nreg) > NUM_ARG_REGS)
|
+ if (((*cum)+nreg) > NUM_ARG_REGS)
|
+ (*cum) = NUM_ARG_REGS;
|
+ (*cum) = NUM_ARG_REGS;
|
+ else
|
+ else
|
| Line 1582... |
Line 1782... |
+static rtx
|
+static rtx
|
+zip_function_arg(cumulative_args_t ca, machine_mode mode,
|
+zip_function_arg(cumulative_args_t ca, machine_mode mode,
|
+ const_tree type ATTRIBUTE_UNUSED, bool named) {
|
+ const_tree type ATTRIBUTE_UNUSED, bool named) {
|
+ CUMULATIVE_ARGS *cum;
|
+ CUMULATIVE_ARGS *cum;
|
+
|
+
|
+ zip_basic_check();
|
|
+
|
|
+
|
|
+ if (!named)
|
+ if (!named)
|
+ return NULL_RTX;
|
+ return NULL_RTX;
|
+ //if (targetm.calls.must_pass_in_stack(mode, type))
|
|
+ //return NULL_RTX;
|
|
+ cum = get_cumulative_args(ca);
|
+ cum = get_cumulative_args(ca);
|
+
|
+
|
+ if ((*cum) >= NUM_ARG_REGS)
|
+ if ((*cum) >= NUM_ARG_REGS)
|
+ return NULL_RTX;
|
+ return NULL_RTX;
|
+ return
|
+ return
|
| Line 1679... |
Line 1874... |
+}
|
+}
|
+
|
+
|
+void zip_canonicalize_comparison(int *code, rtx *op0, rtx *op1,
|
+void zip_canonicalize_comparison(int *code, rtx *op0, rtx *op1,
|
+ bool preserve_op0)
|
+ bool preserve_op0)
|
+{
|
+{
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
+ ZIPDEBUGFLAG(dbg, false);
|
|
+ bool reverse = false;
|
+
|
+
|
+ if (dbg) fprintf(stderr, "CANONICALIZE ...%s\n", (preserve_op0)?"(Preserve Op0)":"");
|
+ if (dbg) fprintf(stderr, "CANONICALIZE ...%s\n", (preserve_op0)?"(Preserve Op0)":"");
|
+ if (dbg) zip_debug_rtx_pfx("CODE", gen_rtx_fmt_ee((rtx_code)*code, VOIDmode, gen_rtx_REG(CCmode,zip_CC), const0_rtx));
|
+ if (dbg) zip_debug_rtx_pfx("CODE", gen_rtx_fmt_ee((rtx_code)*code, VOIDmode, gen_rtx_REG(CCmode,zip_CC), const0_rtx));
|
+ if (dbg) zip_debug_rtx_pfx("OP0 ", *op0);
|
+ if (dbg) zip_debug_rtx_pfx("OP0 ", *op0);
|
+ if (dbg) zip_debug_rtx_pfx("OP1 ", *op1);
|
+ if (dbg) zip_debug_rtx_pfx("OP1 ", *op1);
|
+
|
+
|
+ if ((!preserve_op0)&&((*code == LE)||(*code == GTU)||(*code == GEU))) {
|
+ // Z -> Z
|
+ rtx tem = *op0;
|
+ // NZ -> !Z
|
|
+ // LT -> N
|
|
+ // GE -> !N
|
|
+ // LTU -> C
|
|
+ // GEU -> !C
|
|
+ //
|
|
+ // LTE -> GTE w/ swapped operands
|
|
+ // GT -> LT w/ swapped operands
|
|
+ // GTU -> LTU w/ swapped operands
|
|
+ // LEU -> GEU w/ swapped operands
|
|
+ //
|
|
+
|
|
+ if ((CONST_INT_P(*op0))||(GET_CODE(*op0) == PLUS)) {
|
|
+ rtx tmp = *op0;
|
+ *op0 = *op1;
|
+ *op0 = *op1;
|
+ *op1 = tem;
|
+ *op1 = tmp;
|
+ *code = (int)swap_condition((enum rtx_code)*code);
|
+ *code = (int)swap_condition((enum rtx_code)*code);
|
+ }
|
+ }
|
+
|
+
|
+ if ((*code == LE)||(*code == LEU)||(*code == GTU)) {
|
+ if (*code == GTU) {
|
+ int offset = 1; // (*code == GTU) ? 1 : -1;
|
+ if (REG_P(*op1)) {
|
+ bool swap = false;
|
+ //; Reverse the comparison
|
+
|
+ reverse = true;
|
+ if (CONST_INT_P(*op1)) {
|
+ } else if (CONST_INT_P(*op1)) {
|
+ *op1 = GEN_INT(INTVAL(*op1)+offset);
|
+ //; A > B
|
+ swap = true;
|
+ //; A >= B+1
|
+ } else if (REG_P(*op1)) {
|
+ //; Add one to the integer constant,
|
+ *op1 = plus_constant(GET_MODE(*op1), *op1, offset, true);
|
+ //; And use a GEU comparison
|
+ swap = true;
|
+ *code = GEU;
|
+ } else if ((GET_CODE(*op1)==PLUS)&&(CONST_INT_P(XEXP(*op1,1)))){
|
+ *op1 = GEN_INT(INTVAL(*op1)+1);
|
+ *op1 = plus_constant(GET_MODE(*op1),XEXP(*op1,0),
|
+ } else {
|
+ INTVAL(XEXP(*op1,1))+offset);
|
+ //; Reverse the comparison
|
+ swap = true;
|
+ reverse = true;
|
+ } if (swap) {
|
+ }
|
+ if (*code == LE)
|
+ } else if (*code == LEU) {
|
+ (*code)= LT;
|
+ if (REG_P(*op1)) {
|
+ else if (*code == LEU)
|
+ reverse = true;
|
+ (*code)= LTU;
|
+ } else if (CONST_INT_P(*op1)) {
|
+ else // (*code == GTU)
|
+ //; A <= B
|
+ (*code) = GEU;
|
+ //; A < B+1
|
|
+ //; Add one to the integer constant,
|
|
+ //; And use a GTU comparison
|
|
+ *op1 = GEN_INT(INTVAL(*op1)+1);
|
|
+ *code = LTU;
|
|
+ } else {
|
|
+ reverse = true;
|
|
+ }
|
|
+ } else if (*code == LE) {
|
|
+ if (REG_P(*op1)) {
|
|
+ reverse = true;
|
|
+ } else if (CONST_INT_P(*op1)) {
|
|
+ //; A < B
|
|
+ //; A <= B-1
|
|
+ //; Add one to the integer constant,
|
|
+ //; And use a GTU comparison
|
|
+ *op1 = GEN_INT(INTVAL(*op1)-1);
|
|
+ *code = LT;
|
|
+ } else {
|
|
+ reverse = true;
|
+ }
|
+ }
|
|
+ } else if (*code == GT) {
|
|
+ if (REG_P(*op1)) {
|
|
+ //; Reverse the comparison
|
|
+ reverse = true;
|
|
+ } else if (CONST_INT_P(*op1)) {
|
|
+ //; A > B
|
|
+ //; A >= B+1
|
|
+ //; Add one to the integer constant,
|
|
+ //; And use a GTU comparison
|
|
+ *op1 = GEN_INT(INTVAL(*op1)+1);
|
|
+ *code = GE;
|
|
+ } else {
|
|
+ reverse = true;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ if (reverse) {
|
|
+ rtx tem = *op0;
|
|
+ *op0 = *op1;
|
|
+ *op1 = tem;
|
|
+ *code = (int)swap_condition((enum rtx_code)*code);
|
+ }
|
+ }
|
+}
|
+}
|
+
|
+
|
+static bool
|
+static bool
|
+zip_fixed_condition_code_regs(unsigned int *a, unsigned int *b) {
|
+zip_fixed_condition_code_regs(unsigned int *a, unsigned int *b) {
|
| Line 1728... |
Line 1977... |
+}
|
+}
|
+
|
+
|
+
|
+
|
+/* totally buggy - we can't return pointers to nested functions */
|
+/* totally buggy - we can't return pointers to nested functions */
|
+static void
|
+static void
|
+zip_asm_trampoline_template(FILE *f) {
|
+zip_asm_trampoline_template(FILE *f)
|
+ // Whereas at one time I thought I wouldn't need it, now I know I
|
+{
|
+ // need this trampoline function, although it is for a completely
|
|
+ // different purpose than the one I was familiar with.
|
|
+ fprintf(f, "\tbrev\t0,r1\n");
|
+ fprintf(f, "\tbrev\t0,r1\n");
|
+ fprintf(f, "\tldilo\t0,r1\n");
|
+ fprintf(f, "\tldilo\t0,r1\n");
|
+ fprintf(f, "\tjmp r1\n");
|
+ fprintf(f, "\tjmp r1\n");
|
+}
|
+}
|
+
|
+
|
| Line 1751... |
Line 1998... |
+static tree
|
+static tree
|
+def_builtin(const char *name, enum insn_code icode, enum ZIP_BUILTIN_ID_CODE code,
|
+def_builtin(const char *name, enum insn_code icode, enum ZIP_BUILTIN_ID_CODE code,
|
+ tree type)
|
+ tree type)
|
+{
|
+{
|
+ tree t = add_builtin_function(name,type,code,BUILT_IN_MD, NULL, NULL_TREE);
|
+ tree t = add_builtin_function(name,type,code,BUILT_IN_MD, NULL, NULL_TREE);
|
+ zip_basic_check();
|
|
+
|
+
|
+ if(t) {
|
+ if(t) {
|
+ zip_builtins[code] = t;
|
+ zip_builtins[code] = t;
|
+ zip_builtins_icode[code] = icode;
|
+ zip_builtins_icode[code] = icode;
|
+ }
|
+ }
|
| Line 1763... |
Line 2009... |
+ return t;
|
+ return t;
|
+
|
+
|
+}
|
+}
|
+
|
+
|
+void zip_init_builtins(void) {
|
+void zip_init_builtins(void) {
|
+ zip_basic_check();
|
|
+
|
+
|
+ tree void_ftype_void = build_function_type_list(void_type_node, NULL_TREE);
|
+ tree void_ftype_void = build_function_type_list(void_type_node, NULL_TREE);
|
+#ifdef HAVE_zip_rtu
|
+#ifdef HAVE_zip_rtu
|
+ def_builtin("zip_rtu", CODE_FOR_zip_rtu, ZIP_BUILTIN_RTU, void_ftype_void);
|
+ def_builtin("zip_rtu", CODE_FOR_zip_rtu, ZIP_BUILTIN_RTU, void_ftype_void);
|
+#endif
|
+#endif
|
| Line 1826... |
Line 2071... |
+
|
+
|
+static rtx
|
+static rtx
|
+zip_expand_builtin(tree exp, rtx target,
|
+zip_expand_builtin(tree exp, rtx target,
|
+ rtx subtarget ATTRIBUTE_UNUSED,
|
+ rtx subtarget ATTRIBUTE_UNUSED,
|
+ machine_mode tmode ATTRIBUTE_UNUSED,
|
+ machine_mode tmode ATTRIBUTE_UNUSED,
|
+ int ignore ATTRIBUTE_UNUSED) {
|
+ int ignore ATTRIBUTE_UNUSED)
|
+
|
+{
|
+ tree fndecl = TREE_OPERAND(CALL_EXPR_FN(exp), 0);
|
+ tree fndecl = TREE_OPERAND(CALL_EXPR_FN(exp), 0);
|
+ bool nonvoid = (TREE_TYPE(TREE_TYPE(fndecl)) != void_type_node);
|
+ bool nonvoid = (TREE_TYPE(TREE_TYPE(fndecl)) != void_type_node);
|
+ enum ZIP_BUILTIN_ID_CODE code=(enum ZIP_BUILTIN_ID_CODE)DECL_FUNCTION_CODE(fndecl);
|
+ enum ZIP_BUILTIN_ID_CODE code=(enum ZIP_BUILTIN_ID_CODE)DECL_FUNCTION_CODE(fndecl);
|
+ enum insn_code icode = zip_builtins_icode[code];
|
+ enum insn_code icode = zip_builtins_icode[code];
|
+ rtx pat, op[5];
|
+ rtx pat, op[5];
|
| Line 1867... |
Line 2112... |
+ emit_insn(pat);
|
+ emit_insn(pat);
|
+ return (nonvoid ? target : const0_rtx);
|
+ return (nonvoid ? target : const0_rtx);
|
+}
|
+}
|
+
|
+
|
+static bool
|
+static bool
|
+zip_scalar_mode_supported_p(enum machine_mode mode) {
|
+zip_scalar_mode_supported_p(enum machine_mode mode)
|
+ zip_basic_check();
|
+{
|
+
|
+ if ((ZIP_HAS_DI)&&(mode == DImode))
|
+ return ((mode)==SImode)||((mode)==DImode); // ||((mode)==SFmode);
|
+ return true;
|
|
+ if ((mode==SImode)||(mode==HImode)||(mode==QImode))
|
|
+ return true;
|
|
+ if (mode==SFmode) // &&(ZIP_FPU)
|
|
+ return true; // If (!ZIP_CPU), will need to be emulated
|
|
+ if (mode==DFmode) // Must always be emulated
|
|
+ return true;
|
|
+ return false;
|
+}
|
+}
|
+
|
+
|
+static bool
|
+static bool
|
+zip_libgcc_floating_mode_supported_p(enum machine_mode mode) {
|
+zip_libgcc_floating_mode_supported_p(enum machine_mode mode)
|
|
+{
|
+ return ((mode)==SFmode)||((mode)==DFmode);
|
+ return ((mode)==SFmode)||((mode)==DFmode);
|
+}
|
+}
|
+
|
+
|
+static int
|
+static int
|
+zip_address_cost(rtx addr ATTRIBUTE_UNUSED,
|
+zip_address_cost(rtx addr ATTRIBUTE_UNUSED,
|
| Line 1891... |
Line 2144... |
+zip_mode_dependent_address_p(const_rtx addr ATTRIBUTE_UNUSED,
|
+zip_mode_dependent_address_p(const_rtx addr ATTRIBUTE_UNUSED,
|
+ addr_space_t as ATTRIBUTE_UNUSED) {
|
+ addr_space_t as ATTRIBUTE_UNUSED) {
|
+ return false;
|
+ return false;
|
+}
|
+}
|
+
|
+
|
+/*
|
|
+static void
|
|
+zip_asm_output_anchor(rtx x) {
|
|
+ printf("ANCHOR: OP(%d)\n", GET_CODE(x));
|
|
+}
|
|
+*/
|
|
+
|
|
+static void
|
+static void
|
+zip_debug_print(const char *pfx, int lvl, const char *str) {
|
+zip_debug_print(const char *pfx, int lvl, const char *str) {
|
+ int i;
|
+ int i;
|
+ i = lvl;
|
+ i = lvl;
|
+ if ((true)||(lvl == 0))
|
+ if ((true)||(lvl == 0))
|
| Line 1932... |
Line 2178... |
+ fprintf(stderr, "%s:BLK\n", str);
|
+ fprintf(stderr, "%s:BLK\n", str);
|
+ break;
|
+ break;
|
+ case BImode:
|
+ case BImode:
|
+ fprintf(stderr, "%s:BI\n", str);
|
+ fprintf(stderr, "%s:BI\n", str);
|
+ break;
|
+ break;
|
+#ifdef HAVE_QImode
|
|
+ case QImode:
|
+ case QImode:
|
+ fprintf(stderr, "%s:QI\n", str);
|
+ fprintf(stderr, "%s:QI\n", str);
|
+ break;
|
+ break;
|
+#endif
|
|
+#ifdef HAVE_HImode
|
|
+ case HImode:
|
+ case HImode:
|
+ fprintf(stderr, "%s:HI\n", str);
|
+ fprintf(stderr, "%s:HI\n", str);
|
+ break;
|
+ break;
|
+#endif
|
+#ifdef HAVE_SImode
|
+ case SImode:
|
+ case SImode:
|
+ fprintf(stderr, "%s:SI\n", str);
|
+ fprintf(stderr, "%s:SI\n", str);
|
+ break;
|
+ break;
|
+ case CCmode:
|
+#endif
|
+ fprintf(stderr, "%s:CC\n", str);
|
+#ifdef HAVE_DImode
|
+ break;
|
|
+ case DImode:
|
+ case DImode:
|
+ fprintf(stderr, "%s:DI\n", str);
|
+ fprintf(stderr, "%s:DI\n", str);
|
+ break;
|
+ break;
|
|
+#endif
|
|
+ case CCmode:
|
|
+ fprintf(stderr, "%s:CC\n", str);
|
|
+ break;
|
+ default:
|
+ default:
|
+ fprintf(stderr, "%s:?\n", str);
|
+ fprintf(stderr, "%s:?\n", str);
|
+ }
|
+ }
|
+}
|
+}
|
+
|
+
|
| Line 1970... |
Line 2216... |
+ gcc_assert(0 && "Bad RTX Code");
|
+ gcc_assert(0 && "Bad RTX Code");
|
+ return;
|
+ return;
|
+ } switch(GET_CODE(x)) { // rtl.def
|
+ } switch(GET_CODE(x)) { // rtl.def
|
+ case PARALLEL:
|
+ case PARALLEL:
|
+ zip_debug_print(pfx, lvl, "(PARALLEL");
|
+ zip_debug_print(pfx, lvl, "(PARALLEL");
|
|
+ if (XVEC(x,0) != NULL)
|
+ for(int j=0; j<XVECLEN(x,0);j++)
|
+ for(int j=0; j<XVECLEN(x,0);j++)
|
+ zip_debug_rtx_1(pfx, XVECEXP(x,0,j), lvl+1);
|
+ zip_debug_rtx_1(pfx, XVECEXP(x,0,j), lvl+1);
|
+ zip_debug_print(pfx, lvl, ")");
|
+ zip_debug_print(pfx, lvl, ")");
|
+ debug_rtx(x);
|
+ debug_rtx(x);
|
+ break;
|
+ break;
|
| Line 2056... |
Line 2303... |
+ debug_rtx(x);
|
+ debug_rtx(x);
|
+ break;
|
+ break;
|
+ case REG: {
|
+ case REG: {
|
+ char buf[25], mstr[4];
|
+ char buf[25], mstr[4];
|
+ mstr[0] = '\0';
|
+ mstr[0] = '\0';
|
+ if (GET_MODE(x) == SImode)
|
+ if (GET_MODE(x) == QImode)
|
+ strcpy(mstr, ":SI");
|
+ strcpy(mstr, ":QI");
|
+ else if (GET_MODE(x) == DImode)
|
+ else if (GET_MODE(x) == HImode)
|
+ strcpy(mstr, ":DI");
|
+ strcpy(mstr, ":HI");
|
+ else if (GET_MODE(x) == VOIDmode)
|
+ else if (GET_MODE(x) == VOIDmode)
|
+ strcpy(mstr, ":V");
|
+ strcpy(mstr, ":V");
|
+ if (REGNO(x) == zip_PC)
|
+ if (REGNO(x) == zip_PC)
|
+ sprintf(buf, "(PC%s)", mstr);
|
+ sprintf(buf, "(PC%s)", mstr);
|
+ else if (REGNO(x) == zip_CC)
|
+ else if (REGNO(x) == zip_CC)
|
| Line 2109... |
Line 2356... |
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
+ zip_debug_print(pfx, lvl, ")");
|
+ zip_debug_print(pfx, lvl, ")");
|
+ break;
|
+ break;
|
+ case CONST_INT:
|
+ case CONST_INT:
|
+ { char buf[128];
|
+ { char buf[128];
|
+ if (GET_MODE(x)==SImode)
|
+ if (GET_MODE(x)==QImode)
|
+ sprintf(buf, "(CONST_INT:SI %ld)", (long)INTVAL(x));
|
+ sprintf(buf, "(CONST_INT:QI %ld)", (long)INTVAL(x));
|
+ else if (GET_MODE(x)==VOIDmode)
|
+ else if (GET_MODE(x)==VOIDmode)
|
+ sprintf(buf, "(CONST_INT:V %ld)", (long)INTVAL(x));
|
+ sprintf(buf, "(CONST_INT:V %ld, %016lx)", (long)INTVAL(x),
|
|
+ (unsigned long)INTVAL(x));
|
+ else
|
+ else
|
+ sprintf(buf, "(CONST_INT:? %ld)", (long)INTVAL(x));
|
+ sprintf(buf, "(CONST_INT:? %ld)", (long)INTVAL(x));
|
+ zip_debug_print(pfx, lvl, buf);
|
+ zip_debug_print(pfx, lvl, buf);
|
+ } break;
|
+ } break;
|
+ case LABEL_REF:
|
+ case LABEL_REF:
|
| Line 2125... |
Line 2373... |
+ zip_debug_print(pfx, lvl, buf);
|
+ zip_debug_print(pfx, lvl, buf);
|
+ }
|
+ }
|
+ break;
|
+ break;
|
+ case SYMBOL_REF:
|
+ case SYMBOL_REF:
|
+ {
|
+ {
|
+ char buf[128];
|
+ char buf[1024];
|
+ sprintf(buf, "(SYMBOL: %s)", XSTR(x,0));
|
+ sprintf(buf, "(SYMBOL: %s)", XSTR(x,0));
|
+ // fprintf(file, "%s", XSTR(x,0));
|
+ // fprintf(file, "%s", XSTR(x,0));
|
+ zip_debug_print(pfx, lvl, buf);
|
+ zip_debug_print(pfx, lvl, buf);
|
+ }
|
+ }
|
+ break;
|
+ break;
|
| Line 2245... |
Line 2493... |
+ break;
|
+ break;
|
+ case SCRATCH: //
|
+ case SCRATCH: //
|
+ zip_debug_print_m(pfx, lvl, "(SCRATCH)", GET_MODE(x));
|
+ zip_debug_print_m(pfx, lvl, "(SCRATCH)", GET_MODE(x));
|
+ break;
|
+ break;
|
+ case SUBREG:
|
+ case SUBREG:
|
+ { char buf[25];
|
+ { char buf[64], mstr[8];
|
|
+ if (GET_MODE(x) == QImode)
|
|
+ strcpy(mstr, ":QI");
|
|
+ else if (GET_MODE(x) == HImode)
|
|
+ strcpy(mstr, ":HI");
|
|
+ else if (GET_MODE(x) == SImode)
|
|
+ strcpy(mstr, ":SI");
|
|
+ else if (GET_MODE(x) == VOIDmode)
|
|
+ strcpy(mstr, ":V");
|
|
+ else
|
|
+ strcpy(mstr, ":?");
|
+ if (REG_P(XEXP(x,0))) {
|
+ if (REG_P(XEXP(x,0))) {
|
+ sprintf(buf, "(SUBREG %d/%d)", REGNO(XEXP(x,0)),
|
+ int hreg = REGNO(XEXP(x,0)), mod = GET_MODE(XEXP(x,0)),
|
+ SUBREG_BYTE(x));
|
+ sb = SUBREG_BYTE(x);
|
|
+ if (mod==QImode)
|
|
+ sprintf(buf,"(SUBREG%s (REG:QI %d)/%d)",mstr,hreg, sb);
|
|
+ else if (mod==HImode)
|
|
+ sprintf(buf,"(SUBREG%s (REG:HI %d)/%d)",mstr,hreg, sb);
|
|
+ else if (mod==QImode)
|
|
+ sprintf(buf,"(SUBREG%s (REG:QI %d)/%d)",mstr,hreg, sb);
|
|
+ else if (mod==VOIDmode)
|
|
+ sprintf(buf,"(SUBREG%s (REG:V %d)/%d)",mstr,hreg, sb);
|
|
+ else
|
|
+ sprintf(buf,"(SUBREG%s %d:?/%d)",mstr,hreg, sb);
|
+ zip_debug_print(pfx, lvl, buf);
|
+ zip_debug_print(pfx, lvl, buf);
|
+ } else if (MEM_P(XEXP(x,0))) {
|
+ } else if (MEM_P(XEXP(x,0))) {
|
+ sprintf(buf, "(SUBREG /%d", SUBREG_BYTE(x));
|
+ sprintf(buf, "(SUBREG%s /%d", mstr,SUBREG_BYTE(x));
|
+ zip_debug_print(pfx, lvl, buf);
|
+ zip_debug_print(pfx, lvl, buf);
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
+ zip_debug_print(pfx, lvl, ")");
|
+ zip_debug_print(pfx, lvl, ")");
|
+ } else {
|
+ } else {
|
+ sprintf(buf, "(SUBREG UNK /%d", SUBREG_BYTE(x));
|
+ sprintf(buf, "(SUBREG%s UNK /%d", mstr,SUBREG_BYTE(x));
|
+ zip_debug_print(pfx, lvl, buf);
|
+ zip_debug_print(pfx, lvl, buf);
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
+ zip_debug_print(pfx, lvl, ")");
|
+ zip_debug_print(pfx, lvl, ")");
|
+ }}
|
+ }}
|
+ break;
|
+ break;
|
| Line 2280... |
Line 2548... |
+ zip_debug_print_m(pfx, lvl, "(LSHIFTRT", GET_MODE(x));
|
+ zip_debug_print_m(pfx, lvl, "(LSHIFTRT", GET_MODE(x));
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
+ zip_debug_print(pfx, lvl, ")");
|
+ zip_debug_print(pfx, lvl, ")");
|
+ break;
|
+ break;
|
|
+ case ZERO_EXTRACT:
|
|
+ zip_debug_print_m(pfx, lvl, "(ZERO_EXTRACT", GET_MODE(x));
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
|
+ zip_debug_print(pfx, lvl, ")");
|
|
+ break;
|
|
+ case ZERO_EXTEND:
|
|
+ zip_debug_print_m(pfx, lvl, "(ZERO_EXTEND", GET_MODE(x));
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
|
+ zip_debug_print(pfx, lvl, ")");
|
|
+ break;
|
+ default:
|
+ default:
|
+ { char buf[128];
|
+ { char buf[128];
|
+ sprintf(buf, "(? = %d) -- calling DEBUG-RTX", GET_CODE(x));
|
+ sprintf(buf, "(? = %d) -- calling DEBUG-RTX", GET_CODE(x));
|
+ zip_debug_print(pfx, lvl, buf);
|
+ zip_debug_print(pfx, lvl, buf);
|
+ debug_rtx(x);
|
+ debug_rtx(x);
|
| Line 2304... |
Line 2582... |
+void
|
+void
|
+zip_debug_ccode(int ccode) {
|
+zip_debug_ccode(int ccode) {
|
+ switch(ccode) {
|
+ switch(ccode) {
|
+ case EQ: fprintf(stderr, "EQ"); break;
|
+ case EQ: fprintf(stderr, "EQ"); break;
|
+ case NE: fprintf(stderr, "NE"); break;
|
+ case NE: fprintf(stderr, "NE"); break;
|
+ case GT: fprintf(stderr, "GT"); break;
|
|
+ case GE: fprintf(stderr, "GE"); break;
|
+ case GE: fprintf(stderr, "GE"); break;
|
+ case LT: fprintf(stderr, "LT"); break;
|
+ case LT: fprintf(stderr, "LT"); break;
|
+ case LE: fprintf(stderr, "LE"); break;
|
|
+ case GTU: fprintf(stderr, "GTU"); break;
|
|
+ case GEU: fprintf(stderr, "GEU"); break;
|
|
+ case LTU: fprintf(stderr, "LTU"); break;
|
+ case LTU: fprintf(stderr, "LTU"); break;
|
+ case LEU: fprintf(stderr, "LEU"); break;
|
+ case GEU: fprintf(stderr, "GEU"); break;
|
|
+ case GT: fprintf(stderr, "GT[!]"); break;
|
|
+ case LE: fprintf(stderr, "LE[!]"); break;
|
|
+ case GTU: fprintf(stderr, "GTU[!]"); break;
|
|
+ case LEU: fprintf(stderr, "LEU[!]"); break;
|
+ default:
|
+ default:
|
+ fprintf(stderr, "%d", ccode); break;
|
+ fprintf(stderr, "%d", ccode); break;
|
+ }
|
+ }
|
+}
|
+}
|
+
|
+
|
| Line 2336... |
Line 2614... |
+
|
+
|
+
|
+
|
+static bool
|
+static bool
|
+zip_legitimate_opb(rtx x, bool strict)
|
+zip_legitimate_opb(rtx x, bool strict)
|
+{
|
+{
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
+ ZIPDEBUGFLAG(dbg, false);
|
+
|
+
|
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB\n");
|
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB\n");
|
+ if (dbg) zip_debug_rtx_pfx("Test: ", x);
|
+ if (dbg) zip_debug_rtx_pfx("Test: ", x);
|
+
|
+
|
+ if (NULL_RTX == x)
|
+ if (NULL_RTX == x)
|
+ return false;
|
+ return false;
|
+ else if ((GET_MODE(x) != SImode)&&(GET_MODE(x) != VOIDmode)) {
|
+ else if ((GET_MODE(x) != QImode)
|
|
+ &&(GET_MODE(x) != HImode)
|
|
+ &&(GET_MODE(x) != SImode)
|
|
+ &&(GET_MODE(x) != VOIDmode)) {
|
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> Mode failure\n");
|
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> Mode failure\n");
|
+ return false;
|
+ return false;
|
+ } else if ((strict)&&(REG_P(x))) {
|
+ } else if ((strict)&&(REG_P(x))) {
|
+ if (REGNO(x)<zip_CC) {
|
+ if (REGNO(x)<zip_CC) {
|
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> (Reg)\n");
|
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> (Reg)\n");
|
| Line 2364... |
Line 2645... |
+ return true;
|
+ return true;
|
+ // } else if ((GET_CODE(x) == LABEL_REF)||(GET_CODE(x)==CODE_LABEL)) {
|
+ // } else if ((GET_CODE(x) == LABEL_REF)||(GET_CODE(x)==CODE_LABEL)) {
|
+ // return true;
|
+ // return true;
|
+ } else if (GET_CODE(x) == PLUS) {
|
+ } else if (GET_CODE(x) == PLUS) {
|
+ // Is it a valid register?
|
+ // Is it a valid register?
|
+ if ((!strict)&&(!register_operand((rtx)XEXP((rtx)x,0), GET_MODE(x)))) {
|
+ rtx regrtx = XEXP(x, 0);
|
|
+ if ((!strict)&&(!REG_P(regrtx))) {
|
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No (No reg in +%s)\n",
|
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No (No reg in +%s)\n",
|
+ (GET_CODE(XEXP(x,1))==REG)?", reg in op[1]":"");
|
+ (GET_CODE(XEXP(x,1))==REG)?", reg in op[1]":"");
|
+ return false;
|
+ return false;
|
+ } else if ((strict)&&((!REG_P(XEXP(x,0)))||(REGNO(XEXP(x,0))>=zip_CC))) {
|
+ } else if ((strict)&&((!REG_P(XEXP(x,0)))||(REGNO(XEXP(x,0))>=zip_CC))) {
|
+ return false;
|
+ return false;
|
| Line 2396... |
Line 2678... |
+ return false;
|
+ return false;
|
+}
|
+}
|
+
|
+
|
+static bool
|
+static bool
|
+zip_legitimate_move_operand_p(machine_mode mode ATTRIBUTE_UNUSED, rtx x, bool strict) {
|
+zip_legitimate_move_operand_p(machine_mode mode ATTRIBUTE_UNUSED, rtx x, bool strict) {
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
+ const bool dbg = ((ZIP_ALL_DEBUG_ON)||(false))&&(!ZIP_ALL_DEBUG_OFF);
|
+
|
+
|
+ if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND\n");
|
+ if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND\n");
|
+ if (dbg) zip_debug_rtx_pfx("VMov?: ", x);
|
+ if (dbg) zip_debug_rtx_pfx("VMov?: ", x);
|
+
|
+
|
+ if (!zip_legitimate_opb(x, strict))
|
+ if (!zip_legitimate_opb(x, strict))
|
| Line 2419... |
Line 2701... |
+}
|
+}
|
+
|
+
|
+int
|
+int
|
+zip_pd_mov_operand(rtx op)
|
+zip_pd_mov_operand(rtx op)
|
+{
|
+{
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
+ const bool dbg = ((ZIP_ALL_DEBUG_ON)||(false))&&(!ZIP_ALL_DEBUG_OFF);
|
+
|
+
|
+ if (dbg) fprintf(stderr, "ZIP-VALID-MOV(predicate) for OPERAND\n");
|
+ if (dbg) fprintf(stderr, "ZIP-VALID-MOV(predicate) for OPERAND\n");
|
+ return zip_legitimate_move_operand_p(VOIDmode, op, !can_create_pseudo_p());
|
+ return zip_legitimate_move_operand_p(VOIDmode, op, !can_create_pseudo_p());
|
+}
|
+}
|
+
|
+
|
+int
|
+int
|
+zip_pd_mvimm_operand(rtx op)
|
+zip_pd_mvimm_operand(rtx op)
|
+{
|
+{
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
+ const bool dbg = ((ZIP_ALL_DEBUG_ON)||(false))&&(!ZIP_ALL_DEBUG_OFF);
|
+
|
+
|
+ if (dbg) fprintf(stderr, "ZIP-VALID-MVIMM(predicate) for OPERAND\n");
|
+ if (dbg) fprintf(stderr, "ZIP-VALID-MVIMM(predicate) for OPERAND\n");
|
+ if (!CONST_INT_P(op))
|
+ if (!CONST_INT_P(op))
|
+ return false;
|
+ return false;
|
+ if (INTVAL(op) > zip_max_mov_offset)
|
+ if (INTVAL(op) > zip_max_mov_offset)
|
| Line 2443... |
Line 2725... |
+}
|
+}
|
+
|
+
|
+int
|
+int
|
+zip_pd_imm_operand(rtx op)
|
+zip_pd_imm_operand(rtx op)
|
+{
|
+{
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
+ const bool dbg = ((ZIP_ALL_DEBUG_ON)||(false))&&(!ZIP_ALL_DEBUG_OFF);
|
+
|
+
|
+ if (dbg) fprintf(stderr, "ZIP-VALID-IMM(predicate) for OPERAND\n");
|
+ if (dbg) fprintf(stderr, "ZIP-VALID-IMM(predicate) for OPERAND\n");
|
+ if (!CONST_INT_P(op))
|
+ if (!CONST_INT_P(op))
|
+ return false;
|
+ return false;
|
+ if (INTVAL(op) > zip_max_anchor_offset)
|
+ if (INTVAL(op) > zip_max_anchor_offset)
|
| Line 2458... |
Line 2740... |
+}
|
+}
|
+
|
+
|
+int
|
+int
|
+zip_address_operand(rtx op)
|
+zip_address_operand(rtx op)
|
+{
|
+{
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
+ const bool dbg = ((ZIP_ALL_DEBUG_ON)||(false))&&(!ZIP_ALL_DEBUG_OFF);
|
+
|
+
|
+ if (dbg) fprintf(stderr, "ZIP-ADDRESS for OPERAND\n");
|
+ if (dbg) fprintf(stderr, "ZIP-ADDRESS for OPERAND\n");
|
+ if ((REG_P(op))&&(REGNO(op)==zip_CC))
|
+ if ((REG_P(op))&&(REGNO(op)==zip_CC))
|
+ return false;
|
+ return false;
|
+ else if ((GET_CODE(op) == PLUS)&&(REG_P(XEXP(op,0)))
|
+ else if ((GET_CODE(op) == PLUS)&&(REG_P(XEXP(op,0)))
|
| Line 2473... |
Line 2755... |
+}
|
+}
|
+
|
+
|
+int
|
+int
|
+zip_pd_opb_operand(rtx op)
|
+zip_pd_opb_operand(rtx op)
|
+{
|
+{
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
+ ZIPDEBUGFLAG(dbg, false);
|
+
|
+
|
+ if (dbg) fprintf(stderr, "ZIP-OPB(predicate) for OPERAND\n");
|
+ if (dbg) fprintf(stderr, "ZIP-OPB(predicate) for OPERAND\n");
|
+ return zip_legitimate_opb(op, false); //, !can_create_pseudo_p());
|
+ return zip_legitimate_opb(op, false); //, !can_create_pseudo_p());
|
+}
|
+}
|
+
|
+
|
+int
|
+int
|
+zip_ct_address_operand(rtx op)
|
+zip_ct_address_operand(rtx op)
|
+{
|
+{
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
+ ZIPDEBUGFLAG(dbg, false);
|
+
|
+
|
+ if (dbg) fprintf(stderr, "ZIP-ADDRESS(constraint) for OPERAND\n");
|
+ if (dbg) fprintf(stderr, "ZIP-ADDRESS(constraint) for OPERAND\n");
|
+ return zip_legitimate_opb(op, !can_create_pseudo_p());
|
+ return zip_legitimate_opb(op, !can_create_pseudo_p());
|
+}
|
+}
|
+
|
+
|
+int
|
+int
|
+zip_const_address_operand(rtx x) {
|
+zip_const_address_operand(rtx x) {
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
+ ZIPDEBUGFLAG(dbg, false);
|
+
|
+
|
+ if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS?\n");
|
+ if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS?\n");
|
+ if (dbg) zip_debug_rtx(x);
|
+ if (dbg) zip_debug_rtx(x);
|
+ if ((GET_MODE(x) != SImode)&&(GET_MODE(x) != VOIDmode)) {
|
+ if ((GET_MODE(x) != SImode)&&(GET_MODE(x) != VOIDmode)) {
|
+ fprintf(stderr, "is ZIP-CONST-ADDRESS? -> NO, BAD MODE\n");
|
+ fprintf(stderr, "is ZIP-CONST-ADDRESS? -> NO, BAD MODE\n");
|
| Line 2523... |
Line 2805... |
+ return false;
|
+ return false;
|
+}
|
+}
|
+
|
+
|
+int
|
+int
|
+zip_ct_const_address_operand(rtx x) {
|
+zip_ct_const_address_operand(rtx x) {
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
+ ZIPDEBUGFLAG(dbg, false);
|
+
|
+
|
+ if (dbg) fprintf(stderr, "ZIP-CONST-ADDRESS(constraint)\n");
|
+ if (dbg) fprintf(stderr, "ZIP-CONST-ADDRESS(constraint)\n");
|
+ return zip_const_address_operand(x);
|
+ return zip_const_address_operand(x);
|
+}
|
+}
|
+
|
+
|
+int
|
+int
|
+zip_pd_const_address_operand(rtx x) {
|
+zip_pd_const_address_operand(rtx x) {
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
+ ZIPDEBUGFLAG(dbg, false);
|
+
|
+
|
+ if (dbg) fprintf(stderr, "ZIP-CONST-ADDRESS(predicate)\n");
|
+ if (dbg) fprintf(stderr, "ZIP-CONST-ADDRESS(predicate)\n");
|
+ return zip_const_address_operand(x);
|
+ return zip_const_address_operand(x);
|
+}
|
+}
|
+
|
+
|
+
|
+
|
+static bool
|
+static bool
|
+zip_legitimate_address_p(machine_mode mode ATTRIBUTE_UNUSED, rtx x, bool strict)
|
+zip_legitimate_address_p(machine_mode mode ATTRIBUTE_UNUSED, rtx x, bool strict)
|
+{
|
+{
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
+ ZIPDEBUGFLAG(dbg, false);
|
+
|
+
|
+ if (dbg) fprintf(stderr, "Zip-LEGITIMATE-ADDRESS-P\n");
|
+ if (dbg) fprintf(stderr, "Zip-LEGITIMATE-ADDRESS-P\n");
|
+ if (dbg) zip_debug_rtx(x);
|
+ if (dbg) zip_debug_rtx(x);
|
+
|
+
|
+ // Only insist the register be a valid register if strict is true
|
+ // Only insist the register be a valid register if strict is true
|
| Line 2557... |
Line 2839... |
+ return false;
|
+ return false;
|
+}
|
+}
|
+
|
+
|
+static rtx
|
+static rtx
|
+zip_legitimize_address(rtx x, rtx oldx ATTRIBUTE_UNUSED, machine_mode mode ATTRIBUTE_UNUSED) {
|
+zip_legitimize_address(rtx x, rtx oldx ATTRIBUTE_UNUSED, machine_mode mode ATTRIBUTE_UNUSED) {
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
+ ZIPDEBUGFLAG(dbg, false);
|
|
+
|
+
|
+
|
+ if (dbg) zip_debug_rtx_pfx("LEGITIMIZE: ", x);
|
+ if (dbg) zip_debug_rtx_pfx("LEGITIMIZE: ", x);
|
+ if (zip_legitimate_address_p(mode, x, !can_create_pseudo_p()))
|
+ if (zip_legitimate_address_p(mode, x, !can_create_pseudo_p()))
|
+ return x;
|
+ return x;
|
+
|
+
|
|
+ if (dbg) zip_debug_rtx_pfx("ILLEGITIMATE: ", x);
|
+ if (GET_CODE(x)==PLUS) {
|
+ if (GET_CODE(x)==PLUS) {
|
|
+ // if ((zip_legitimate_address_p(mode, XEXP(x,0),
|
|
+ // !can_create_pseudo_p()))
|
|
+ // &&(GETMODE(XEXP(x,1))==CONST_INT)) {
|
|
+ //}
|
+ if (!REG_P(XEXP(x,0)))
|
+ if (!REG_P(XEXP(x,0)))
|
+ XEXP(x,0) = force_reg(GET_MODE(x),XEXP(x,0));
|
+ XEXP(x,0) = force_reg(Pmode,XEXP(x,0));
|
+ if ((!zip_legitimate_address_p(mode, x, !can_create_pseudo_p()))
|
+ if ((!zip_legitimate_address_p(mode, x, !can_create_pseudo_p()))
|
+ &&(!CONST_INT_P(XEXP(x,1))))
|
+ &&(!CONST_INT_P(XEXP(x,1))))
|
+ x = force_reg(GET_MODE(x),x);
|
+ x = force_reg(GET_MODE(x),x);
|
+ } else if (MEM_P(x))
|
+ } else if (MEM_P(x))
|
+ x = force_reg(GET_MODE(x),x);
|
+ x = force_reg(GET_MODE(x),x);
|
| Line 2579... |
Line 2867... |
+}
|
+}
|
+
|
+
|
+void
|
+void
|
+zip_asm_output_def(FILE *stream, const char *name, const char *value)
|
+zip_asm_output_def(FILE *stream, const char *name, const char *value)
|
+{
|
+{
|
+ assemble_name(stream, name);
|
+ fprintf(stream, "\t.equ %s, %s\n", name, value);
|
+ fprintf(stream, "\t.equ ");
|
|
+ assemble_name(stream, value);
|
|
+ fputc('\n', stream);
|
|
+}
|
+}
|
+
|
+
|
+#define USE_SUBREG
|
|
+#ifdef USE_SUBREG
|
|
+#define SREG_P(RTX) ((SUBREG_P(RTX))&&(REG_P(XEXP(RTX,0))))
|
|
+#define SMEM_P(RTX) ((SUBREG_P(RTX))&&(MEM_P(XEXP(RTX,0))))
|
|
+#else
|
|
+#define SREG_P(RTX) false
|
|
+#define SMEM_P(RTX) false
|
|
+#endif
|
|
+
|
|
+const char *zip_set_zero_or_one(rtx condition, rtx dst) {
|
+const char *zip_set_zero_or_one(rtx condition, rtx dst) {
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
+ ZIPDEBUGFLAG(dbg, false);
|
|
+
|
+ if (dbg) fprintf(stderr, "ZIP::SET-ZERO-OR-ONE\n");
|
+ if (dbg) fprintf(stderr, "ZIP::SET-ZERO-OR-ONE\n");
|
+ if (dbg) zip_debug_rtx_pfx("CND", condition);
|
+ if (dbg) zip_debug_rtx_pfx("CND", condition);
|
+ if (dbg) zip_debug_rtx_pfx("REG", dst);
|
+ if (dbg) zip_debug_rtx_pfx("REG", dst);
|
+ switch(GET_CODE(condition)) {
|
+ switch(GET_CODE(condition)) {
|
+ case EQ: return "LDI\t0,%0\n\tLDILO.Z\t1,%0";
|
+ case EQ: return "LDI\t0,%0\n\tLDILO.Z\t1,%0\t; set01_eq";
|
+ case NE: return "LDI\t0,%0\n\tLDILO.NZ\t1,%0";
|
+ case NE: return "LDI\t0,%0\n\tLDILO.NZ\t1,%0\t; set01_ne";
|
+ case LT: return "LDI\t0,%0\n\tLDILO.LT\t1,%0";
|
+ case LT: return "LDI\t0,%0\n\tLDILO.LT\t1,%0\t; set01_lt";
|
+ case GT: return "LDI\t0,%0\n\tLDILO.GT\t1,%0";
|
+ case GT: return "LDI\t1,%0\n\tLDILO.LT\t1,%0\n\tLDILO.Z\t1,%0\t; set01_gt";
|
+ case LE: return "LDI\t1,%0\n\tLDILO.GT\t0,%0";
|
+ case LE: return "LDI\t0,%0\n\tLDILO.LT\t1,%0\n\tLDILO.Z\t1,%0\t; set01_le";
|
+ case GE: return "LDI\t0,%0\n\tLDILO.GE\t1,%0";
|
+ case GE: return "LDI\t0,%0\n\tLDILO.GE\t1,%0\t; set01_ge";
|
+ case LTU: return "LDI\t0,%0\n\tLDILO.C\t1,%0";
|
+ case LTU: return "LDI\t0,%0\n\tLDILO.C\t1,%0\t; set01_ltu";
|
+ case GTU: return "LDI\t1,%0\n\tLDILO.C\t0,%0\n\tLDILO.Z\t0,%0";
|
+ case GEU: return "LDI\t0,%0\n\tLDILO.NC\t1,%0\t; set01_geu";
|
+ case LEU: return "LDI\t0,%0\n\tLDILO.C\t1,%0\n\tLDILO.Z\t1,%0";
|
+ case GTU: return "LDI\t1,%0\n\tLDILO.C\t0,%0\n\tLDILO.Z\t0,%0\t; set01_gtu";
|
+ case GEU: return "LDI\t1,%0\n\tLDILO.C\t0,%0";
|
+ case LEU: return "LDI\t0,%0\n\tLDILO.C\t1,%0\n\tLDILO.Z\t1,%0\t; set01_leu";
|
+ default:
|
+ default:
|
+ zip_debug_rtx(condition);
|
+ zip_debug_rtx(condition);
|
+ internal_error("CSTORE Unsupported condition");
|
+ internal_error("CSTORE Unsupported condition");
|
+ return NULL;
|
+ return NULL;
|
+ }
|
+ }
|
+}
|
+}
|
+
|
+
|
+/*
|
|
+const char *zip_binary_movsicc(rtx_code condition, const char *op, const int opno) {
|
|
+ static char result[64] = "";
|
|
+ switch(condition) {
|
|
+ //
|
|
+ // Result already exists in the iffalse register
|
|
+ // Can't change it. Therefore, on the
|
|
+ // condition ... move true register to the
|
|
+ // destination
|
|
+ //
|
|
+ case EQ: sprintf(result, "%s.Z\t%%%d,%%0", op, opno); break;
|
|
+ case NE: sprintf(result, "%s.NZ\t%%%d,%%0", op, opno); break;
|
|
+ case LT: sprintf(result, "%s.LT\t%%%d,%%0", op, opno); break;
|
|
+ case GT: sprintf(result, "%s.GT\t%%%d,%%0", op, opno); break;
|
|
+ // .LE doesn't exist on Zip CPU--turn this into two instructions
|
|
+ case LE: sprintf(result, "%s.LT\t%%%d,%%0\n\t%s.Z\t%%%d,%%0", op, opno, op, opno); break;
|
|
+ case GE: sprintf(result, "%s.GE\t%%%d,%%0", op, opno); break;
|
|
+ case LTU: sprintf(result, "%s.C\t%%%d,%%0", op, opno); break;
|
|
+ //
|
|
+ // .GTU doesn't exist on the Zip CPU either. We also note that
|
|
+ // .C will never be set on an equal condition. Therefore, we
|
|
+ // turn this into a XOR.NZ 2,CC, which will set the .C condition
|
|
+ // as long as .Z wasn't true. We then undo this when we're
|
|
+ // done. This is possible since none of these instructions
|
|
+ // (LDI/MOV/Lod conditional, nor Xor conditional) will ever set
|
|
+ // the condition codes.
|
|
+ //
|
|
+ // This is obviously not very optimal. Avoid this by all means
|
|
+ // if you can
|
|
+ case GTU: sprintf(result, "XOR.NZ\t2,CC\n%s.C\t%%%d,%%0\n\tXOR.NZ\t2,CC", op, opno); break;
|
|
+ // .LEU doesn't exist on Zip CPU either--turn this into another
|
|
+ // two instructions
|
|
+ case LEU: sprintf(result, "%s.C\t%%%d,%%0\n\t%s.Z\t%%%d,%%0", op, opno, op, opno); break;
|
|
+ //
|
|
+ // .GEU doesn't exist on Zip CPU. Implementing it her is
|
|
+ // painful. We can change the condition codes to make it so,
|
|
+ // but the instruction requires the condition codes not be
|
|
+ // changed. Hence, we must change them back if we do so.
|
|
+ //
|
|
+ // .C will be set on less than but not equal. Hence !.C will
|
|
+ // be true on greater than or equal.
|
|
+ case GEU: sprintf(result, "XOR\t2,CC\n%s.C\t%%%d,%%0\n\tXOR\t2,CC", op, opno); break;
|
|
+ default:
|
|
+ internal_error("MOVSICC(BINARY) Unsupported condition");
|
|
+ return NULL;
|
|
+ } return result;
|
|
+}
|
|
+*/
|
|
+
|
|
+int
|
+int
|
+zip_supported_condition(int c) {
|
+zip_supported_condition(int c) {
|
+ switch(c) {
|
+ switch(c) {
|
+ case NE: case LT: case EQ: case GT: case GE: case LTU:
|
+ case EQ: case NE: case LT: case GE: case LTU: case GEU:
|
+ return 1;
|
+ return 1;
|
+ break;
|
+ break;
|
+ default:
|
+ default:
|
+ break;
|
+ break;
|
+ } return 0;
|
+ } return 0;
|
+}
|
+}
|
+
|
+
|
+bool
|
+bool
|
+zip_signed_comparison(int c) {
|
+zip_signed_comparison(int c) {
|
+ switch(c) {
|
+ switch(c) {
|
+ case NE: case LT: case EQ: case GT: case GE:
|
+ case NE: case LT: case EQ: case GE:
|
+ return true;
|
+ return true;
|
+ default:
|
+ default:
|
+ break;
|
+ break;
|
+ } return false;
|
+ } return false;
|
+}
|
+}
|
+
|
+
|
+int
|
+int
|
+zip_expand_movsicc(rtx dst, rtx condition, rtx iftrue, rtx iffalse) {
|
+zip_expand_movdi(rtx dst, rtx src) {
|
+ rtx_insn *insn;
|
+ ZIPDEBUGFLAG(dbg, false);
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
+
|
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC\n");
|
+ if (dbg) fprintf(stderr, "\nZIP::MOVDI\n");
|
+ if (dbg) zip_debug_rtx_pfx("DST", dst);
|
+ if (dbg) zip_debug_rtx_pfx("DST", dst);
|
+ if (dbg) zip_debug_rtx_pfx("CND", condition);
|
+ if (dbg) zip_debug_rtx_pfx("SRC", src);
|
+ if (dbg) zip_debug_rtx_pfx("TRU", iftrue);
|
|
+ if (dbg) zip_debug_rtx_pfx("FAL", iffalse);
|
|
+
|
+
|
+ // Start with the condition
|
+ // MOV !REG->!REG
|
+ rtx cmpa = XEXP(condition,0), cmpb=XEXP(condition,1);
|
+ if ((!REG_P(dst))&&(!REG_P(src))&&(can_create_pseudo_p())) {
|
+ enum rtx_code cmpcode = GET_CODE(condition);
|
+ // This includes:
|
+
|
+ // MOV MEM->MEM
|
+ // Want to always do the false expression, and only sometimes the
|
+ // MOV IMM->MEM
|
+ // true expression. If, however, the false is a constant and the
|
+ if (dbg) fprintf(stderr, "ZIP::MOVDI -- !REG->!REG\n");
|
+ // true and destination are the same thing, this doesn't work.
|
+
|
+ if (rtx_equal_p(dst, iftrue)) {
|
+ rtx tmp = gen_reg_rtx(DImode);
|
+ // If the true value is the same as the destination already,
|
+ emit_insn(gen_movdi(tmp, src));
|
+ // then swap so we only do the condition on true
|
+ emit_insn(gen_movdi(dst, tmp));
|
+ rtx tem = iffalse;
|
+ return 1;
|
+ iffalse = iftrue;
|
|
+ iftrue = tem;
|
|
+ cmpcode = reverse_condition(cmpcode);
|
|
+ }
|
|
+
|
|
+ //; Do we need to swap or adjust the condition?
|
|
+ if (zip_supported_condition((int)cmpcode)) {
|
|
+ // Keep everything as is
|
|
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- Condition is supported\n");
|
|
+ } else if ((zip_supported_condition(reverse_condition(cmpcode)))
|
|
+ &&(!MEM_P(iffalse))
|
|
+ &&(!rtx_equal_p(dst,iffalse))) {
|
|
+ rtx tem = iffalse;
|
|
+ iffalse = iftrue;
|
|
+ iftrue = tem;
|
|
+
|
|
+ cmpcode = reverse_condition(cmpcode);
|
|
+ } else if ((zip_supported_condition((int)swap_condition(cmpcode)))
|
|
+ &&((REG_P(cmpb))||(can_create_pseudo_p()))) {
|
|
+ rtx tem = cmpa;
|
|
+ cmpa = cmpb;
|
|
+ cmpa = tem;
|
|
+ cmpcode = swap_condition(cmpcode);
|
|
+
|
|
+ if ((GET_CODE(cmpa)==PLUS)&&(zip_signed_comparison((int)cmpcode))
|
|
+ &&(REG_P(XEXP(cmpa,0)))
|
|
+ &&(CONST_INT_P(XEXP(cmpa,1)))
|
|
+ &&(abs(INTVAL(XEXP(cmpa,1)))<(1<<17))) {
|
|
+
|
|
+ // If we were doing CMP x(Rb),Ra
|
|
+ // and we just changed it to CMP Ra,x(Rb)
|
|
+ // adjust it to CMP -x(Ra),Rb
|
|
+ cmpb = plus_constant(SImode, cmpb, -INTVAL(XEXP(cmpa,1)));
|
|
+ cmpa = XEXP(cmpa,0);
|
|
+ } else if (!REG_P(cmpa)) {
|
|
+ // Otherwise, if we had anything else in Rb other than
|
|
+ // a register ... such as a constant, then load it into
|
|
+ // a register before comparing it. So
|
|
+ // CMP x,Ra
|
|
+ // became
|
|
+ // CMP Ra,x
|
|
+ // now becomes
|
|
+ // LDI x,Rt
|
|
+ // CMP Ra,Rt
|
|
+ // (We already tested for can_create_pseudo_p() above..)
|
|
+ tem = gen_reg_rtx(SImode);
|
|
+ emit_move_insn(tem, cmpa);
|
|
+ cmpa = tem;
|
|
+ }
|
|
+ } else {
|
|
+ // Here's our last chance.
|
|
+ // This will adjust for less than equal types of stuff
|
|
+ int cod = (int)cmpcode;
|
|
+ zip_canonicalize_comparison(&cod, &cmpa, &cmpb, false);
|
|
+ cmpcode = (enum rtx_code)cod;
|
|
+ }
|
+ }
|
+
|
+
|
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- Post-Modes\n");
|
+ // MOV REG->REG
|
+ if (dbg) zip_debug_rtx_pfx("DST-P: ", dst);
|
+ if ((REG_P(dst))&&(REG_P(src))) {
|
+ if (dbg) zip_debug_rtx_pfx("CND-P: ", condition);
|
+ if (dbg) fprintf(stderr, "ZIP::MOVDI -- REG->REG\n");
|
+ if (dbg) zip_debug_rtx_pfx("TRU-P: ", iftrue);
|
|
+ if (dbg) zip_debug_rtx_pfx("FAL-P: ", iffalse);
|
|
+
|
+
|
+ if (!zip_supported_condition((int)cmpcode)) {
|
+ emit_insn(gen_movdi_raw(dst, src));
|
+ if (dbg) {
|
+ return 1;
|
+ fprintf(stderr, "ZIP::MOVSICC -- Unsupported condition: ");
|
|
+ zip_debug_ccode(cmpcode);
|
|
+ fprintf(stderr, "\n");
|
|
+ }
|
|
+ return 0;
|
|
+ }
|
+ }
|
+ gcc_assert(zip_supported_condition((int)cmpcode));
|
|
+
|
+
|
+ //; Always do the default move
|
+ // MOV REG->MEM (a store instruction)
|
+ bool conditionally_do_false = false;
|
+ if ((MEM_P(dst))&&(REG_P(src))) {
|
+ conditionally_do_false = (MEM_P(iffalse))
|
+ rtx addr = XEXP(dst,0);
|
+ &&(!rtx_equal_p(dst,iffalse))
|
+ long offset = 0;
|
+ &&(zip_supported_condition(reverse_condition(cmpcode)));
|
+ if ((GET_CODE(addr)==PLUS)&&(CONST_INT_P(XEXP(addr,1))))
|
+ conditionally_do_false = conditionally_do_false || (rtx_equal_p(dst,iftrue));
|
+ offset = INTVAL(XEXP(addr,1));
|
+ if ((conditionally_do_false)&&(!zip_supported_condition(reverse_condition(cmpcode)))) {
|
+
|
+ if (dbg) {
|
+ if (dbg) fprintf(stderr, "ZIP::MOVDI -- REG->MEM\n");
|
+ fprintf(stderr, "ZIP::MOVSICC -- Cant support the reverse condition: ");
|
+ if (REG_P(addr)) {
|
+ zip_debug_ccode(cmpcode);
|
+ emit_insn(gen_movdi_raw(dst, src));
|
+ fprintf(stderr, "\n");
|
+ return 1;
|
|
+ } else if ((GET_CODE(addr)==PLUS)
|
|
+ &&(REG_P(XEXP(addr,0)))
|
|
+ &&(CONST_INT_P(XEXP(addr,1)))
|
|
+ &&(offset>=(long)zip_min_anchor_offset)
|
|
+ &&(offset+4<(long)zip_max_anchor_offset)) {
|
|
+ // Demonstrated and works
|
|
+ emit_insn(gen_movdi_raw(dst, src));
|
|
+ return 1;
|
|
+ } else if (can_create_pseudo_p()) {
|
|
+ rtx tmp = gen_reg_rtx(Pmode);
|
|
+ emit_insn(gen_movsi(tmp, addr));
|
|
+ emit_insn(gen_movdi_raw(gen_rtx_MEM(DImode, tmp), src));
|
|
+ return 1;
|
+ }
|
+ }
|
+ return 0;
|
|
+ }
|
+ }
|
+
|
+
|
+ if ((!rtx_equal_p(dst, iffalse))&&(!conditionally_do_false)) {
|
+ // MOV MEM->REG (a load instruction)
|
+ if (dbg)
|
+ if ((REG_P(dst))&&(MEM_P(src))) {
|
+ fprintf(stderr, "ZIP::MOVSICC -- EMITTING MOVE FALSE->DST\n");
|
+ rtx addr = XEXP(src,0);
|
+ insn = emit_move_insn(dst, iffalse);
|
+ long offset = 0;
|
+ if (dbg) zip_debug_rtx_pfx("BARE-U: ", insn);
|
+ if ((GET_CODE(addr)==PLUS)&&(CONST_INT_P(XEXP(addr,1))))
|
+ }
|
+ offset = INTVAL(XEXP(addr,1));
|
+
|
+
|
+ rtx cc_rtx = gen_rtx_REG(CCmode, zip_CC);
|
+ if (dbg) fprintf(stderr, "ZIP::MOVDI -- MEM->REG\n");
|
+
|
+ if (REG_P(addr)) {
|
+ //; Now let's get our comparison right
|
+ if (dbg) fprintf(stderr, "ZIP::MOVDI -- MEM[R]->REG\n");
|
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- EMITTING COMPARISON\n");
|
+ emit_insn(gen_movdi_raw(dst, src));
|
+ insn = emit_insn(gen_rtx_SET(VOIDmode, cc_rtx,
|
+ return 1;
|
+ gen_rtx_COMPARE(CCmode, cmpa, cmpb)));
|
+ } else if ((GET_CODE(addr)==PLUS)
|
+ if (dbg) zip_debug_rtx_pfx("BARE-C: ", insn);
|
+ &&(REG_P(XEXP(addr,0)))
|
+
|
+ &&(CONST_INT_P(XEXP(addr,1)))
|
+ //; Finally, let's load the value on true
|
+ &&(offset>=(long)zip_min_anchor_offset)
|
+ if (!rtx_equal_p(dst, iftrue)) {
|
+ &&(offset+4<(long)zip_max_anchor_offset)) {
|
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- EMITTING BARE\n");
|
+ if (dbg) fprintf(stderr, "ZIP::MOVDI -- MEM[#+R]->REG -- DONE\n");
|
+ insn=emit_insn(gen_movsicc_bare(dst,
|
+ emit_insn(gen_movdi_raw(dst, src));
|
+ gen_rtx_fmt_ee(cmpcode, SImode, NULL_RTX, NULL_RTX),
|
+ return 1;
|
+ iftrue, dst));
|
+ } else if (can_create_pseudo_p()) {
|
+ if (dbg) zip_debug_rtx_pfx("BARE-T: ", insn);
|
+ if (dbg) fprintf(stderr, "ZIP::MOVDI -- LDI #,R, MEM[R]->REG\n");
|
+ }
|
+ rtx tmp = gen_reg_rtx(Pmode);
|
+
|
+ emit_insn(gen_movsi(tmp, addr));
|
+ if (conditionally_do_false) {
|
+ emit_insn(gen_movdi_raw(dst,
|
+ gcc_assert(zip_supported_condition(reverse_condition(cmpcode)));
|
+ gen_rtx_MEM(DImode, tmp)));
|
+ insn=emit_insn(gen_movsicc_bare(dst,
|
+ return 1;
|
+ gen_rtx_fmt_ee(reverse_condition(cmpcode), SImode,
|
+ } else if (dbg)
|
+ NULL_RTX, NULL_RTX), iffalse, dst));
|
+ fprintf(stderr, "ZIP::MOVDI -- MEM[?]->REG (no match)\n");
|
+ if (dbg) zip_debug_rtx_pfx("BARE-F: ", insn);
|
|
+ }
|
+ }
|
+
|
+
|
+ // Return true on success
|
+ // MOV #->REG (An LDI instruction, but for DIwords)
|
|
+ if ((CONST_INT_P(src))&&(REG_P(dst))) {
|
|
+ if (dbg) fprintf(stderr, "ZIP::MOVDI -- IMM->REG\n");
|
|
+ emit_insn(gen_movdi_raw(dst, src));
|
+ return 1;
|
+ return 1;
|
+}
|
+}
|
+
|
+
|
+const char *zip_addsicc(rtx dst, rtx condition, rtx ifsrc, rtx addv ATTRIBUTE_UNUSED) {
|
+ return 0;
|
|
+}
|
|
+
|
|
+const char *
|
|
+zip_addsicc(rtx dst, rtx condition, rtx ifsrc, rtx addv) {
|
+ // We know upon entry that REG_P(dst) must be true
|
+ // We know upon entry that REG_P(dst) must be true
|
+ if (!REG_P(dst))
|
+ if (!REG_P(dst))
|
+ internal_error("%s","ADDSICC into something other than register");
|
+ internal_error("%s","ADDSICC into something other than register");
|
|
+
|
|
+ if ((REG_P(dst))&&(REG_P(ifsrc))&&(REG_P(addv))
|
|
+ &&(REGNO(dst)!=REGNO(ifsrc))) {
|
|
+ switch (GET_CODE(condition)) {
|
|
+ case EQ: return "MOV.Z\t%2,%0\n\tADD.Z\t%3,%0";
|
|
+ case NE: return "MOV.NZ\t%2,%0\n\tADD.NZ\t%3,%0";
|
|
+ case LT: return "MOV.LT\t%2,%0\n\tADD.LT\t%3,%0";
|
|
+
|
|
+ case LE: return "MOV.LT\t%3,%0\n\tMOV.Z\t%3,%0\n\tADD.LT\t%3,%0\n\tADD.Z\t%3,%0";
|
|
+ case GE: return "MOV.GE\t%2,%0\n\tADD.GE\t%3,%0";
|
|
+
|
|
+ case GT: return "BLT\t%.Laddsi%=\n\tBZ\t%%.Laddsi%=\n\tMOV\t%2,%0\n\tADD\t%3,%0\n.Laddsi%=:";
|
|
+ case LTU: return "MOV.C\t%2,%0\n\tADD.C\t%3,%0";
|
|
+
|
|
+ case LEU: return "MOV.C\t%2,%0\n\tMOV.Z\t%2,%0\n\tADD.C\t%3,%0\n\tADD.Z\t%3,%0";
|
|
+ case GEU: return "MOV.NC\t%2,%0\n\tADD.NC\t%3,%0";
|
|
+ case GTU: return "BZ\t%.Laddsi%=\n\tMOV.NC\t%3,%0\n\tADD.NC\t%3,%0\n.Laddsi%=:";
|
|
+ default:
|
|
+ internal_error("%s", "Zip/No usable addsi expansion");
|
|
+ break;
|
|
+ }
|
|
+ }
|
|
+
|
+ if ((REG_P(ifsrc))&&(REGNO(dst)==REGNO(ifsrc))) {
|
+ if ((REG_P(ifsrc))&&(REGNO(dst)==REGNO(ifsrc))) {
|
+ switch (GET_CODE(condition)) {
|
+ switch (GET_CODE(condition)) {
|
+ case EQ: return "ADD.Z\t%3,%0";
|
+ case EQ: return "ADD.Z\t%3,%0";
|
+ case NE: return "ADD.NZ\t%3,%0";
|
+ case NE: return "ADD.NZ\t%3,%0";
|
+ case LT: return "ADD.LT\t%3,%0";
|
+ case LT: return "ADD.LT\t%3,%0";
|
+ case GT: return "ADD.GT\t%3,%0";
|
|
+ case LE: return "ADD.LT\t%3,%0\n\tADD.Z\t%3,%0";
|
+ case LE: return "ADD.LT\t%3,%0\n\tADD.Z\t%3,%0";
|
+ case GE: return "ADD.GE\t%3,%0";
|
+ case GE: return "ADD.GE\t%3,%0";
|
|
+ case GT: return "ADD.GE\t%3,%0\n\tSUB.Z\t%3,%0";
|
+ case LTU: return "ADD.C\t%3,%0";
|
+ case LTU: return "ADD.C\t%3,%0";
|
+ case LEU: return "ADD.C\t%3,%0\n\tADD.Z\t%3,%0";
|
+ case LEU: return "ADD.C\t%3,%0\n\tADD.Z\t%3,%0";
|
+ case GEU: return "XOR\t2,CC\n\tADD.C\t%3,%0\n\tXOR\t2,CC";
|
+ case GEU: return "ADD.NC\t%3,%0";
|
+ // Can do a GEU comparison, and then undo on the Zero condition
|
+ case GTU: return "SUB.Z\t%3,%0\n\tADD.NC\t%3,%0";
|
+ case GTU: return "XOR\t2,CC\n\tADD.C\t%3,%0\n\tSUB.Z\t%3,%0\n\tXOR\t2,CC";
|
|
+ default:
|
+ default:
|
+ internal_error("%s", "Zip/No usable addsi expansion");
|
+ internal_error("%s", "Zip/No usable addsi expansion");
|
+ break;
|
+ break;
|
+ }
|
+ }
|
+ } else {
|
+ } else {
|
+ // MOV A+REG,REG
|
+ // MOV A+REG,REG
|
+ switch (GET_CODE(condition)) {
|
+ switch (GET_CODE(condition)) {
|
+ case EQ: return "MOV.Z\t%3+%2,%0";
|
+ case EQ: return "MOV.Z\t%3+%2,%0";
|
+ case NE: return "MOV.NZ\t%3+%2,%0";
|
+ case NE: return "MOV.NZ\t%3+%2,%0";
|
+ case LT: return "MOV.LT\t%3+%2,%0";
|
+ case LT: return "MOV.LT\t%3+%2,%0";
|
+ case GT: return "MOV.GT\t%3+%2,%0";
|
+ case GT: return "BLT\t.Laddcc%=\n\tBZ\t.Laddcc%=\n\tMOV\t%3+%2,%0\n.Laddcc%=";
|
+ case LE: return "MOV.LT\t%3+%2,%0\n\tMOV.Z\t%3+%2,%0";
|
+ case LE: return "MOV.LT\t%3+%2,%0\n\tMOV.Z\t%3+%2,%0";
|
+ case GE: return "MOV.GE\t%3+%2,%0";
|
+ case GE: return "MOV.GE\t%3+%2,%0";
|
+ case LTU: return "MOV.C\t%3+%2,%0";
|
+ case LTU: return "MOV.C\t%3+%2,%0";
|
+ case LEU: return "MOV.C\t%3+%2,%0\n\tMOV.Z\t%3+%2,%0";
|
+ case LEU: return "MOV.C\t%3+%2,%0\n\tMOV.Z\t%3+%2,%0";
|
+ case GEU: return "XOR\t2,CC\n\tMOV.C\t%3+%2,%0\n\tXOR\t2,CC";
|
+ case GEU: return "MOV.NC\t%3+%2,%0";
|
+ // Can do a GEU comparison, and then undo on the Zero condition
|
+ case GTU: return "BZ\t.Laddcc%=\n\tMOV.NC\t%3+%2,%0\n\t.Laddcc%=:";
|
+ // EXCEPT: with a move instruction, what's there to undo? We
|
|
+ // just clobbered our register!
|
|
+ // case GTU: return "XOR\t2,CC\n\tMOV.C\t%3,%0\n\tSUB.Z\t%3,%0XOR\t2,CC";
|
|
+ default:
|
+ default:
|
+ internal_error("%s", "Zip/No usable addsi(reg,reg) expansion");
|
+ internal_error("%s", "Zip/No usable addsi(reg,reg) expansion");
|
+ break;
|
+ break;
|
+ }
|
+ }
|
+ }
|
+ }
|
| Line 2897... |
Line 3097... |
+
|
+
|
+rtx_insn *zip_ifcvt_info;
|
+rtx_insn *zip_ifcvt_info;
|
+
|
+
|
+void
|
+void
|
+zip_ifcvt_modify_tests(ce_if_block *ce_info ATTRIBUTE_UNUSED, rtx *true_expr, rtx *false_expr) {
|
+zip_ifcvt_modify_tests(ce_if_block *ce_info ATTRIBUTE_UNUSED, rtx *true_expr, rtx *false_expr) {
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
+ const bool dbg = ((ZIP_ALL_DEBUG_ON)||(false))&&(!ZIP_ALL_DEBUG_OFF);
|
+ if (dbg) fprintf(stderr, "IFCVT-MODIFY-TESTS\n");
|
+ if (dbg) fprintf(stderr, "IFCVT-MODIFY-TESTS\n");
|
+ if (*true_expr) switch(GET_CODE(*true_expr)) {
|
+ if (*true_expr) switch(GET_CODE(*true_expr)) {
|
|
+ // These are our unsupported conditions
|
+ case LE:
|
+ case LE:
|
+ case GTU:
|
+ case GT:
|
+ case GEU:
|
|
+ case LEU:
|
+ case LEU:
|
|
+ case GTU:
|
+ if (dbg) fprintf(stderr, "TRUE, missing expr\n");
|
+ if (dbg) fprintf(stderr, "TRUE, missing expr\n");
|
+ if (dbg) zip_debug_rtx(*true_expr);
|
+ if (dbg) zip_debug_rtx(*true_expr);
|
+ *true_expr = NULL_RTX;
|
+ *true_expr = NULL_RTX;
|
+ break;
|
+ break;
|
+ default: // LT, GT, GTE, LTU, NE, EQ
|
+ default: // LT, GT, GTE, LTU, NE, EQ
|
+ break;
|
+ break;
|
+ }
|
+ }
|
+
|
+
|
+ if (*false_expr) switch(GET_CODE(*false_expr)) {
|
+ if (*false_expr) switch(GET_CODE(*false_expr)) {
|
+ case LE:
|
+ case LE:
|
+ case GTU:
|
+ case GT:
|
+ case GEU:
|
|
+ case LEU:
|
+ case LEU:
|
|
+ case GTU:
|
+ if (dbg) fprintf(stderr, "FALSE, missing expr\n");
|
+ if (dbg) fprintf(stderr, "FALSE, missing expr\n");
|
+ if (dbg) zip_debug_rtx(*false_expr);
|
+ if (dbg) zip_debug_rtx(*false_expr);
|
+ *false_expr = NULL_RTX;
|
+ *false_expr = NULL_RTX;
|
+ default:
|
+ default:
|
+ break;
|
+ break;
|
| Line 2996... |
Line 3197... |
+
|
+
|
+int zip_insn_sets_cc(rtx_insn *insn) {
|
+int zip_insn_sets_cc(rtx_insn *insn) {
|
+ return (get_attr_ccresult(insn)==CCRESULT_SET);
|
+ return (get_attr_ccresult(insn)==CCRESULT_SET);
|
+}
|
+}
|
+
|
+
|
+int zip_is_conditional(rtx_insn *insn) {
|
+const char *
|
+ return (get_attr_conditional(insn)==CONDITIONAL_YES);
|
+zip_cbranchdi_const(rtx comparison,
|
|
+ rtx a ATTRIBUTE_UNUSED,
|
|
+ rtx b,
|
|
+ rtx label ATTRIBUTE_UNUSED) {
|
|
+ gcc_assert(CONST_INT_P(b));
|
|
+ long value = INTVAL(b);
|
|
+
|
|
+ // Look into the combine routines to find out why this routine never
|
|
+ // gets called.
|
|
+
|
|
+ switch(GET_CODE(comparison)) {
|
|
+ case EQ:
|
|
+ if (value < 0)
|
|
+ return "CMP\t-1,%H1\t; cbranchdi/# EQ (neg)\n\tCMP.Z\t%2,%L1\n\tBZ\t%3";
|
|
+ else
|
|
+ return "CMP\t0,%H1\t; cbranchdi/# EQ\n\tCMP.Z\t%2,%L1\n\tBZ\t%3";
|
|
+ case NE:
|
|
+ if (value < 0)
|
|
+ return "CMP\t-1,%H1\t; cbranchdi/# NE (neg)\n\tCMP.Z\t%2,%L1\n\tBNZ\t%3";
|
|
+ else
|
|
+ return "CMP\t0,%H1\t; cbranchdi/# NE\n\tCMP.Z\t%2,%L1\n\tBNZ\t%3";
|
|
+ case LE:
|
|
+ if (value == 0)
|
|
+ return "CMP\t0,%H1\t; cbranchdi/# LE 0\n\tBLT\t%3\n\tCMP.Z\t0,%L1\n\tBZ\t%3";
|
|
+ else if (value == -1)
|
|
+ return "CMP\t0,%H1\t; cbranchdi/# LE -1\n\tBLT\t%3";
|
|
+ else if (value < 0) {
|
|
+ char tmp[128];
|
|
+ sprintf(tmp, "CMP\t-1,%%H1\t; cbranchdi/# LE (neg)\n"
|
|
+ "\tBLT\t.Lcmpdile%%=\n"
|
|
+ "\tBNZ\t%%3\n"
|
|
+ "\tCMP\t%ld,%%L1\n"
|
|
+ "\tBC\t%%3", (value+1l)&0x0ffffffff);
|
|
+ return ggc_alloc_string(tmp, -1);
|
|
+ } else { //; value > 0
|
|
+ char tmp[128];
|
|
+ sprintf(tmp, "CMP\t0,%%H1\t; cbranchdi/# LE\n"
|
|
+ "\tBLT\t%%3\n"
|
|
+ "\tBNZ\t.Lcmple%%=\n"
|
|
+ "\tCMP\t%ld,%%L1\n"
|
|
+ "\tBC\t%%3\n"
|
|
+ ".Lcmple%%=:", value-1);
|
|
+ return ggc_alloc_string(tmp, -1);
|
|
+ }
|
|
+ case LT:
|
|
+ if (value == 0)
|
|
+ return "CMP\t0,%H1\t; cbranchdi/# LT 0\n\tBLT\t%3";
|
|
+ else if (value < 0)
|
|
+ return "CMP\t-1,%H1\t; cbranchdi/# LT neg\n\tCMP.Z\t%2,%L1\n\tBC\t%3";
|
|
+ else
|
|
+ return "CMP\t0,%H1\t; cbranchdi/# LT\n"
|
|
+ "\tBLT\t%3\n"
|
|
+ "\tBNZ\t.Lcmplt%=\n"
|
|
+ "\tCMP\t%2,%L1\n"
|
|
+ "\tBC\t%3\n"
|
|
+ ".Lcmplt%=:";
|
|
+ case GT:
|
|
+ if (value == 0)
|
|
+ return "CMP\t1,%H1\t; cbranchdi/# GT 0\n"
|
|
+ "\tBGE\t%3\n"
|
|
+ "\tBNZ\t.Lcmpgt%=\n"
|
|
+ "\tCMP\t0,%L1\n"
|
|
+ "\tBNZ\t%3\n"
|
|
+ ".Lcmpgt%=:";
|
|
+ else if (value == -1)
|
|
+ return "CMP\t0,%H1\t; cbranchdi/# GT -1\n"
|
|
+ "\tBGE\t%3\n";
|
|
+ else if (value < 0) {
|
|
+ char tmp[128];
|
|
+ sprintf(tmp, "CMP\t-1,%%H1\t; cbranchdi/# GT neg\n"
|
|
+ "\tBLT\t.Lcmpgt%%=\n"
|
|
+ "\tBNZ\t%%3\n"
|
|
+ "\tCMP\t%ld,%%H3\n"
|
|
+ "\tBNC\t%%3\n"
|
|
+ ".Lcmpgt%%=:", value+1l);
|
|
+ return ggc_alloc_string(tmp, -1);
|
|
+ } else {
|
|
+ char tmp[128];
|
|
+ sprintf(tmp, "CMP\t0,%%H1\t; cbranchdi/# GT\n"
|
|
+ "\tBLT\t.Lcmpgt%%=\n"
|
|
+ "\tBNZ\t%%3\n"
|
|
+ "\tCMP\t%ld,%%L1\n"
|
|
+ "\tBNC\t%%3\n"
|
|
+ ".Lcmpgt%%=:", value+1l);
|
|
+ return ggc_alloc_string(tmp, -1);
|
|
+ }
|
|
+ case GE:
|
|
+ if (value == 0)
|
|
+ return "CMP\t0,%H1\t; cbranchdi/# GE 0\n"
|
|
+ "\tBLT\t.Lcmpge%=\n"
|
|
+ "\tBNZ\t%3\n"
|
|
+ "\tCMP\t0,%L1\n"
|
|
+ "\tBNC\t%3\n"
|
|
+ ".Lcmpge%=:";
|
|
+ else if (value == -1)
|
|
+ return "CMP\t-1,%H1\t; cbranchdi/# GE -1\n"
|
|
+ "\tBLT\t.Lcmpge%=\n"
|
|
+ "\tBNZ\t%3\n"
|
|
+ "\tCMP\t-1,%L1\n"
|
|
+ "\tBZ\t%3\n"
|
|
+ ".Lcmpge%=:";
|
|
+ else if (value < 0)
|
|
+ return "CMP\t-1,%H1\t; cbranchdi/# GE <\n"
|
|
+ "\tBLT\t.Lcmpge%=\n"
|
|
+ "\tBNZ\t%3\n"
|
|
+ "\tCMP\t%2,%L1\n"
|
|
+ "\tBNC\t%3\n"
|
|
+ ".Lcmpge%=:";
|
|
+ else
|
|
+ return "CMP\t0,%H1\t; cbranchdi/# GE\n"
|
|
+ "\tBLT\t.Lcmpge%=\n"
|
|
+ "\tBNZ\t%3\n"
|
|
+ "\tCMP\t%2,%L1\n"
|
|
+ "\tBNC\t%3\n"
|
|
+ ".Lcmpge%=:";
|
|
+ case LTU:
|
|
+ if (value == 0) { //; Impossible, cannot be < 0 unsignd
|
|
+ return "; cbranchdi/# LTU 0 (Impossible!)";
|
|
+ } else
|
|
+ return "CMP\t0,%H1\t; cbranchdi/#\n\tCMP.Z\t%2,%L1\n\tBC\t%3\n";
|
|
+ case LEU:
|
|
+ if (value == 0) { //; Only possible if == 0
|
|
+ return "CMP\t0,%%H0\t; cbranchdi/# LEU 0\n"
|
|
+ "\tCMP.Z\t0,%%L0\n"
|
|
+ "\tBZ\t%3";
|
|
+ } else {
|
|
+ //; Subtract one, and LTU works
|
|
+ char tmp[128];
|
|
+ sprintf(tmp, "CMP\t0,%%H1\t; cbranchdi/# LEU\n"
|
|
+ "\tCMP.Z\t%ld,%%L1\n"
|
|
+ "\tBC\t%%3\n", value-1);
|
|
+ return ggc_alloc_string(tmp, -1);
|
|
+ }
|
|
+ case GTU:
|
|
+ if (value == 0) {
|
|
+ //; Equivalent to not equal to zero
|
|
+ return "CMP\t0,%H1\t; cbranchdi/# GTU 0\n\tCMP.Z\t0,%L1\n\tBNZ\t%3";
|
|
+ } else {
|
|
+ char tmp[128];
|
|
+ sprintf(tmp,
|
|
+ "CMP\t0,%%H1\t; cbranchdi/# GTU\n"
|
|
+ "\tBNZ\t%%3\n"
|
|
+ "\tCMP\t%ld,%%L1\n"
|
|
+ "\tBNC\t%%3\n", value+1);
|
|
+ return ggc_alloc_string(tmp, -1);
|
|
+ }
|
|
+ case GEU:
|
|
+ if (value == 0) //; Unsigned, always true
|
|
+ return "BRA\t%3\t; cbranchdi/# GEU 0";
|
|
+ else
|
|
+ return "CMP\t0,%H1\t; cbranchdi/# GEU\n"
|
|
+ "\tBNZ\t%3\n"
|
|
+ "\tCMP\t%2,%L1\n"
|
|
+ "\tBNC\t%3";
|
|
+ default:
|
|
+ gcc_unreachable();
|
|
+ }
|
|
+}
|
|
+
|
|
+const char *
|
|
+zip_cbranchdi_reg(rtx comparison,
|
|
+ rtx a ATTRIBUTE_UNUSED,
|
|
+ rtx b ATTRIBUTE_UNUSED,
|
|
+ rtx label ATTRIBUTE_UNUSED) {
|
|
+
|
|
+ switch(GET_CODE(comparison)) {
|
|
+ case EQ:
|
|
+ return "CMP\t%H2,%H1\t; cbranchdi/r EQ\n\tCMP.Z\t%L2,%L1\n\tBZ\t%3";
|
|
+ case NE:
|
|
+ return "CMP\t%H2,%H1\t; cbranchdi/r NE\n\tCMP.Z\t%L2,%L1\n\tBNZ\t%3";
|
|
+ case LE:
|
|
+ return "CMP\t%H2,%H1\t; cbranchdi/r LE\n"
|
|
+ "\tBLT\t%3\n"
|
|
+ "\tBNZ\t.Ldi%=\n"
|
|
+ "\tCMP\t%L1,%L2\n"
|
|
+ "\tBNC\t%3\n"
|
|
+ ".Ldi%=:";
|
|
+ case GT:
|
|
+ return "CMP\t%H1,%H2\t; cbranchdi/r GT\n"
|
|
+ "\tBLT\t%3\n"
|
|
+ "\tBNZ\t.Ldi%=\n"
|
|
+ "\tCMP\t%L1,%L2\n"
|
|
+ "\tBC\t%3\n"
|
|
+ ".Ldi%=:";
|
|
+ case LT:
|
|
+ return "CMP\t%H2,%H1\t; cbranchdi/r LT\n"
|
|
+ "\tBLT\t%3\n"
|
|
+ "\tBNZ\t.Ldi%=\n"
|
|
+ "\tCMP\t%L2,%L1\n"
|
|
+ "\tBC\t%3\n"
|
|
+ ".Ldi%=:";
|
|
+ case GE:
|
|
+ return "CMP\t%H1,%H2\t; cbranchdi/r GE\n"
|
|
+ "\tBLT\t%3\n"
|
|
+ "\tBNZ\t.Ldi%=\n"
|
|
+ "\tCMP\t%L2,%L1\n"
|
|
+ "\tBNC\t%3\n"
|
|
+ ".Ldi%=:";
|
|
+ case LTU:
|
|
+ return "CMP\t%H2,%H1\t; cbranchdi/r LTU\n"
|
|
+ "\tCMP.Z\t%L2,%L1\n"
|
|
+ "\tBC\t%3\n";
|
|
+ case LEU:
|
|
+ return "CMP\t%H1,%H2\t; cbranchdi/r LEU\n"
|
|
+ "\tBC\t.Ldi%=\n" //; H1 > H2, skip
|
|
+ "\tCMP.Z\t%L1,%L2\n" //; (H1==H2) test L1-L2
|
|
+ "\tBNC\t%3\n" //; If (L1>=L2)||(H1>H2)
|
|
+ ".Ldi%=:";
|
|
+ case GTU:
|
|
+ return "CMP\t%H1,%H2\t; cbranchdi/r GTU\n"
|
|
+ "\tCMP.Z\t%L1,%L2\n"
|
|
+ "\tBC\t%3";
|
|
+ case GEU:
|
|
+ return "CMP\t%H2,%H1\t; cbranchdi/r GEU\n"
|
|
+ "\tBC\t.Ldi%=\n"
|
|
+ "\tCMP.Z\t%L2,%L1\n"
|
|
+ "\tBNC\t%3\n"
|
|
+ ".Ldi%=:";
|
|
+ default:
|
|
+ gcc_unreachable();
|
|
+ }
|
|
+}
|
|
+
|
|
+const char *
|
|
+zip_cbranchdi(rtx comparison, rtx a, rtx b, rtx label) {
|
|
+ if (REG_P(b))
|
|
+ return zip_cbranchdi_reg(comparison, a, b, label);
|
|
+ else
|
|
+ return zip_cbranchdi_const(comparison, a, b, label);
|
+}
|
+}
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-float.md gcc-5.3.0-zip/gcc/config/zip/zip-float.md
|
+
|
--- gcc-5.3.0-original/gcc/config/zip/zip-float.md 1969-12-31 19:00:00.000000000 -0500
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zipdbg.h gcc-6.2.0-zip/gcc/config/zip/zipdbg.h
|
+++ gcc-5.3.0-zip/gcc/config/zip/zip-float.md 2016-11-10 10:17:53.248750791 -0500
|
--- gcc-6.2.0/gcc/config/zip/zipdbg.h 1969-12-31 19:00:00.000000000 -0500
|
@@ -0,0 +1,138 @@
|
+++ gcc-6.2.0-zip/gcc/config/zip/zipdbg.h 2017-02-17 16:47:25.727651898 -0500
|
|
@@ -0,0 +1,8 @@
|
|
+#define DO_ZIP_DEBUGS
|
|
+#ifdef DO_ZIP_DEBUGS
|
|
+#include <stdio.h>
|
|
+#define ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
|
|
+extern void zip_debug_rtx(const_rtx);
|
|
+#else
|
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
|
+#endif
|
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip-di.md gcc-6.2.0-zip/gcc/config/zip/zip-di.md
|
|
--- gcc-6.2.0/gcc/config/zip/zip-di.md 1969-12-31 19:00:00.000000000 -0500
|
|
+++ gcc-6.2.0-zip/gcc/config/zip/zip-di.md 2017-02-22 15:56:17.195319460 -0500
|
|
@@ -0,0 +1,528 @@
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;
|
+;;
|
+;; Filename: zip-float.md
|
+;; Filename: zip-di.md
|
+;;
|
+;;
|
+;; Project: Zip CPU -- a small, lightweight, RISC CPU soft core
|
+;; Project: Zip CPU -- a small, lightweight, RISC CPU soft core
|
+;;
|
+;;
|
+;; Purpose: This is the machine description of the ZipCPU floating point
|
+;; Purpose: This is the machine description of the Zip CPU as needed by the
|
+;; unit (if installed).
|
+;; GNU compiler collection (GCC). Specifically, this is the
|
|
+;; section of the description associated with 64-bit values and
|
|
+;; arithmetic.
|
+;;
|
+;;
|
+;;
|
+;;
|
+;; Creator: Dan Gisselquist, Ph.D.
|
+;; Creator: Dan Gisselquist, Ph.D.
|
+;; Gisselquist Technology, LLC
|
+;; Gisselquist Technology, LLC
|
+;;
|
+;;
|
| Line 3040... |
Line 3484... |
+;;
|
+;;
|
+;;
|
+;;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+(define_expand "movdi"
|
+;;
|
+ [(set (match_operand:DI 0 "nonimmediate_operand" "")
|
+;; Floating point Op-codes
|
+ (match_operand:DI 1 "general_operand" ""))]
|
+;;
|
+ "(ZIP_HAS_DI)"
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+ {
|
|
+ if (zip_expand_movdi(operands[0], operands[1]))
|
|
+ DONE;
|
|
+ FAIL;
|
|
+ }
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+(define_insn "addsf3"
|
+(define_insn "movdi_raw"
|
+ [(set (match_operand:SF 0 "register_operand" "=r")
|
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,Q,r,r")
|
+ (plus:SF (match_operand:SF 1 "register_operand" "0")
|
+ (match_operand:DI 1 "general_operand" "r,r,Q,i"))]
|
+ (match_operand:SF 2 "register_operand" "r")))
|
+ "(ZIP_HAS_DI)"
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ "(ZIP_FPU)"
|
|
+ "FPADD %2,%0"
|
|
+ [(set_attr "ccresult" "unknown")])
|
|
+(define_insn "subsf3"
|
|
+ [(set (match_operand:SF 0 "register_operand" "=r")
|
|
+ (minus:SF (match_operand:SF 1 "register_operand" "0")
|
|
+ (match_operand:SF 2 "register_operand" "r")))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ "(ZIP_FPU)"
|
|
+ "FPSUB %2,%0"
|
|
+ [(set_attr "ccresult" "unknown")])
|
|
+(define_insn "mulsf3"
|
|
+ [(set (match_operand:SF 0 "register_operand" "=r")
|
|
+ (mult:SF (match_operand:SF 1 "register_operand" "0")
|
|
+ (match_operand:SF 2 "register_operand" "r")))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ "(ZIP_FPU)"
|
|
+ "FPMUL %2,%0"
|
|
+ [(set_attr "ccresult" "unknown")])
|
|
+(define_insn "divsf3"
|
|
+ [(set (match_operand:SF 0 "register_operand" "=r")
|
|
+ (div:SF (match_operand:SF 1 "register_operand" "0")
|
|
+ (match_operand:SF 2 "register_operand" "r")))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ "(ZIP_FPU)"
|
|
+ "FPDIV %2,%0"
|
|
+ [(set_attr "ccresult" "unknown")])
|
|
+; (define_insn "floatsisf2"
|
|
+; [(set (match_operand:SF 0 "register_operand" "=r"
|
|
+; (float:SI (match_operand:SF 1 "register_operand" "r"))))
|
|
+; (set (reg:CC CC_REG) (compare:CC (match_dup 1) (const_int 0)))]
|
|
+; "(ZIP_FPU)"
|
|
+; "FPI2F %1,%0")
|
|
+; (define_insn "floatunssisf2" ... ?)
|
|
+; (define_insn "fix_truncsfsi2"
|
|
+; [(set (match_operand:SI 0 "register_operand" "=r"
|
|
+; (float:SF (match_operand:SF 1 "register_operand" "r"))))
|
|
+; (set (reg:CC CC_REG) (compare:CC (match_dup 1) (const_int 0)))]
|
|
+; "(ZIP_FPU)"
|
|
+; "FPI2F %1,%0")
|
|
+; (define_insn "nearbyintsf2" ... ?)
|
|
+; (define_insn "truncsfsi2" ... ?)
|
|
+(define_expand "negsf2"
|
|
+ [(set (match_operand:SF 0 "register_operand" "=r")
|
|
+ (neg:SF (match_operand:SF 1 "register_operand" "0")))
|
|
+ ]
|
|
+ ""
|
|
+ {
|
+ {
|
+ operands[0] = gen_rtx_SUBREG(SImode, operands[0], 0);
|
+ if ((REG_P(operands[0]))&&(REG_P(operands[1])))
|
+ if (can_create_pseudo_p()) {
|
+ return "MOV %H1,%H0\t; MOV:DI\n\tMOV %L1,%L0";
|
+ rtx tmp = gen_reg_rtx(SImode);
|
+ else if (MEM_P(operands[0])) //; StoreDI
|
+ emit_insn(gen_movsi_ldi(tmp,gen_int_mode(0x80000000,SImode)));
|
+ return "SW %H1,%0\t; Store:DI\n\tSW %L1,4+%0";
|
+ emit_insn(gen_xorsi3(operands[0], operands[0], tmp));
|
+ else if (MEM_P(operands[1])) //; LoadDI
|
+ DONE;
|
+ return "LW %1,%H0\t; Load:DI\n\tLW 4+%1,%L0";
|
+ } else {
|
+ else if (CONST_INT_P(operands[1])) {
|
+ emit_insn(gen_zip_bitrev(operands[0],operands[0]));
|
+ char tmp[128];
|
+ emit_insn(gen_iorsi3(operands[0], operands[0],
|
+ HOST_WIDE_INT v = INTVAL(operands[1]);
|
+ gen_int_mode(1,SImode)));
|
+ sprintf(tmp, "LDI\t0x%08x,%%H0\t; LDI #:DI,%%H0\n\tLDI\t0x%08x,%%L0",
|
+ emit_insn(gen_zip_bitrev(operands[0],operands[0]));
|
+ (unsigned)(v>>32),
|
+ DONE;
|
+ (unsigned)(v));
|
|
+ return ggc_alloc_string(tmp, -1);
|
|
+ } else
|
|
+ gcc_unreachable();
|
+ }
|
+ }
|
+ })
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
+(define_expand "abssf2"
|
+;
|
+ [(set (match_operand:SF 0 "register_operand" "=r")
|
+;
|
+ (abs:SF (match_operand:SF 1 "register_operand" "0")))
|
+;
|
|
+; ADD
|
|
+;
|
|
+;
|
|
+(define_insn "adddi3" ; Fastest/best instruction always goes first
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
|
+ (plus:DI (match_operand:DI 1 "register_operand" "0")
|
|
+ (match_operand:DI 2 "register_operand" "r")))
|
|
+ (clobber (reg:CC CC_REG))
|
+ ]
|
+ ]
|
+ ""
|
+ "(ZIP_HAS_DI)"
|
+ {
|
+ "ADD %L2,%L0\n\tADD.C\t1,%H0\n\tADD\t%H2,%H0"
|
+ operands[0] = gen_rtx_SUBREG(SImode, operands[0], 0);
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+ if (can_create_pseudo_p()) {
|
|
+ rtx tmp = gen_reg_rtx(SImode);
|
|
+ emit_insn(gen_movsi_ldi(tmp,gen_int_mode(0x7fffffff,SImode)));
|
|
+ emit_insn(gen_andsi3(operands[0], operands[0], tmp));
|
|
+ DONE;
|
|
+ } else {
|
|
+ emit_insn(gen_zip_bitrev(operands[0],operands[0]));
|
|
+ emit_insn(gen_andsi3(operands[0], operands[0],
|
|
+ gen_int_mode(-2,SImode)));
|
|
+ emit_insn(gen_zip_bitrev(operands[0],operands[0]));
|
|
+ DONE;
|
|
+ }
|
|
+ })
|
|
+;
|
+;
|
+;
|
+;
|
+; STILL MISSING:
|
|
+;
|
+;
|
|
+; SUB
|
+;
|
+;
|
+;
|
+;
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.h gcc-5.3.0-zip/gcc/config/zip/zip.h
|
+(define_insn "subdi3"
|
--- gcc-5.3.0-original/gcc/config/zip/zip.h 1969-12-31 19:00:00.000000000 -0500
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
+++ gcc-5.3.0-zip/gcc/config/zip/zip.h 2016-11-19 08:26:58.092386679 -0500
|
+ (minus:DI (match_operand:DI 1 "register_operand" "0")
|
@@ -0,0 +1,4096 @@
|
+ (match_operand:DI 2 "register_operand" "r")))
|
+////////////////////////////////////////////////////////////////////////////////
|
+ (clobber (reg:CC CC_REG))
|
+//
|
+ ]
|
+// Filename: gcc/config/zip/zip.h
|
+ "(ZIP_HAS_DI)"
|
+//
|
+ "SUB %L2,%L0\n\tSUB.C\t1,%H0\n\tSUB\t%H2,%H0"
|
+// Project: Zip CPU backend for the GNU Compiler Collection
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+//
|
+;
|
+// Purpose:
|
+;
|
+//
|
+;
|
+// Creator: Dan Gisselquist, Ph.D.
|
+; AND
|
+// Gisselquist Technology, LLC
|
+;
|
+//
|
+;
|
+////////////////////////////////////////////////////////////////////////////////
|
+(define_insn "anddi3"
|
+//
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
+// Copyright (C) 2016, Gisselquist Technology, LLC
|
+ (and:DI (match_operand:DI 1 "register_operand" "%0")
|
+//
|
+ (match_operand:DI 2 "register_operand" "r")))
|
+// This program is free software (firmware): you can redistribute it and/or
|
+ (clobber (reg:CC CC_REG))
|
+// modify it under the terms of the GNU General Public License as published
|
+ ]
|
+// by the Free Software Foundation, either version 3 of the License, or (at
|
+ "(ZIP_HAS_DI)"
|
+// your option) any later version.
|
+ "AND %L2,%L0\t; AND:DI\n\tAND\t%H2,%H0"
|
+//
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+// This program is distributed in the hope that it will be useful, but WITHOUT
|
+;
|
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
+;
|
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
+;
|
|
+; iOR
|
|
+;
|
|
+;
|
|
+(define_insn "iordi3"
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
|
+ (ior:DI (match_operand:DI 1 "register_operand" "%0")
|
|
+ (match_operand:DI 2 "register_operand" "r")))
|
|
+ (clobber (reg:CC CC_REG))
|
|
+ ]
|
|
+ "(ZIP_HAS_DI)"
|
|
+ "OR %L2,%L0\t; OR:DI\n\tOR\t%H2,%H0"
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
|
+;
|
|
+;
|
|
+;
|
|
+; XOR
|
|
+;
|
|
+;
|
|
+(define_insn "xordi3"
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
|
+ (xor:DI (match_operand:DI 1 "register_operand" "%0")
|
|
+ (match_operand:DI 2 "register_operand" "r")))
|
|
+ (clobber (reg:CC CC_REG))
|
|
+ ]
|
|
+ "(ZIP_HAS_DI)"
|
|
+ "XOR %L2,%L0\t; XOR:DI\n\tXOR\t%H2,%H0"
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
|
+;
|
|
+;
|
|
+; NEG
|
|
+;
|
|
+;
|
|
+(define_insn "negdi2"
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
|
+ (neg:DI (match_operand:DI 1 "register_operand" "0")))
|
|
+ (clobber (reg:CC CC_REG))
|
|
+ ]
|
|
+ "(ZIP_HAS_DI)"
|
|
+ "XOR -1,%L0\t; NEG:DI\n\tXOR\t-1,%H0\n\tADD\t1,%L0\n\tADD.C\t1,%H0"
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
|
+;
|
|
+;
|
|
+;
|
|
+; ABS
|
|
+;
|
|
+;
|
|
+(define_insn "absdi2"
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
|
+ (abs:DI (match_operand:DI 1 "register_operand" "0")))
|
|
+ (clobber (match_scratch:SI 2 "=r"))
|
|
+ (clobber (reg:CC CC_REG))
|
|
+ ]
|
|
+ "(ZIP_HAS_DI)"
|
|
+ "CLR %2 ; ABSDI
|
|
+ TEST %H0
|
|
+ LDILO.LT 1,%2
|
|
+ XOR.LT -1,%L0
|
|
+ XOR.LT -1,%H0
|
|
+ ADD %2,%L0
|
|
+ ADD.C 1,%H0"
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
|
+;
|
|
+;
|
|
+; NOT
|
|
+;
|
|
+;
|
|
+(define_insn "one_cmpldi2"
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
|
+ (not:DI (match_operand:DI 1 "register_operand" "0")))
|
|
+ (clobber (reg:CC CC_REG))
|
|
+ ]
|
|
+ "(ZIP_HAS_DI)"
|
|
+ "XOR -1,%L0\t; NOT:DI\n\tXOR\t-1,%H0"
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
|
+;
|
|
+;
|
|
+; Unsigned min/max
|
|
+;
|
|
+;
|
|
+(define_insn "umindi3"
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
|
+ (umin:DI (match_operand:DI 1 "register_operand" "%0")
|
|
+ (match_operand:DI 2 "register_operand" "r")))
|
|
+ (clobber (reg:CC CC_REG))
|
|
+ ]
|
|
+ "(ZIP_HAS_DI)"
|
|
+ "CMP %H0,%H2 ; umin:DI
|
|
+ CMP.Z %L0,%L2
|
|
+ MOV.C %H2,%H0
|
|
+ MOV.C %L2,%L0"
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
|
+(define_insn "umaxdi3"
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
|
+ (umax:DI (match_operand:DI 1 "register_operand" "%0")
|
|
+ (match_operand:DI 2 "register_operand" "r")))
|
|
+ (clobber (reg:CC CC_REG))
|
|
+ ]
|
|
+ "(ZIP_HAS_DI)"
|
|
+ "CMP %H2,%H0 ; umax:DI
|
|
+ CMP.Z %L2,%L0
|
|
+ MOV.C %H2,%H0
|
|
+ MOV.C %L2,%L0"
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
|
+;
|
|
+;
|
|
+; Multiply
|
|
+;
|
|
+;
|
|
+(define_expand "muldi3"
|
|
+ [(parallel [(set (match_operand:DI 0 "register_operand" "=r")
|
|
+ (mult:DI (match_operand:DI 1 "register_operand" "r")
|
|
+ (match_operand:DI 2 "register_operand" "r")))
|
|
+ (clobber (match_dup 1))
|
|
+ (clobber (match_dup 2))
|
|
+ (clobber (match_scratch:SI 3 "=r"))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ "(ZIP_HAS_DI)")
|
|
+;
|
|
+(define_insn "muldi3_raw"
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
|
+ (mult:DI (match_operand:DI 1 "register_operand" "r")
|
|
+ (match_operand:DI 2 "register_operand" "r")))
|
|
+ (clobber (match_dup 1))
|
|
+ (clobber (match_dup 2))
|
|
+ (clobber (match_scratch:SI 3 "=r"))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ "(ZIP_HAS_DI)"
|
|
+ {
|
|
+ int regno[3];
|
|
+ regno[0] = REGNO(operands[0]);
|
|
+ regno[1] = REGNO(operands[1]);
|
|
+ regno[2] = REGNO(operands[2]);
|
|
+ //; We need to adjust what we are doing based upon which
|
|
+ //; registers are in common. We have a couple of cases:
|
|
+ //;
|
|
+ if ((regno[0] == regno[1])&&(regno[0] == regno[2])) {
|
|
+ //; RA = RA * RA
|
|
+ //;
|
|
+ //; (H0:L0) = (H0:L0) * (H0:L0)
|
|
+ //; (H0:L0) = (H0*2^32 + L0) * (H0 * 2^32 + L0)
|
|
+ //; (H0:L0) = (H0*H0*2^64 + (H0*L0+L0*H0)*2^32 + L0 *L0)
|
|
+ //; = (H0*L0+L0*H1):(L0*L0)
|
|
+ //; :L0 = LOPART(L0 * L0)
|
|
+ //; H0 = HIPART(L0 * L0)
|
|
+ //; H0 += LOPART(H0 * L0)
|
|
+ //; H0 += LOPART(L0 * H0)
|
|
+ //;
|
|
+ //; Rx = L0
|
|
+ //; H0 *= L0 ( = LOPART( HI * LO )
|
|
+ //; H0 <<= 1 ( = 2*LOPART( HI * LO ) )
|
|
+ //; Rx *= L0 ( = HIPART( LO * LO )
|
|
+ //; L0 *= L0 ( = LOPART( LO * LO )
|
|
+ //; H0 += Rx ( = 2*LOPART( HI * LO ) + HIPART( LO *LO)
|
|
+ //;
|
|
+ return "; muldi3_raw/A (%H0:%L0) = (%H1:%L1) * (%H2:%L2)\n"
|
|
+ "\tMOV\t%L0,%3\n"
|
|
+ "\tMPY\t%L0,%H0\n"
|
|
+ "\tLSL\t1,%H0\n"
|
|
+ "\tMPYUHI\t%L0,%3\n"
|
|
+ "\tMPY\t%L0,%L0\n"
|
|
+ "\tADD\t%3,%H0";
|
|
+ } else if ((regno[0] != regno[1])&&(regno[1] == regno[2])) {
|
|
+ //; RA = RB * RB
|
|
+ //;
|
|
+ //; (H0:L0) = (H1:L1) * (H1:L1)
|
|
+ //; (H0:L0) = (H1*2^32 + L1) * (H1 * 2^32 + L1)
|
|
+ //; (H0:L0) = (H1*H1*2^64 + (H1*L1+L1*H1)*2^32 + L1 * L1)
|
|
+ //; = (H1*L1+L1*H1):(L1*L1)
|
|
+ //; :L0 = LOPART(L1 * L1)
|
|
+ //; H0 = HIPART(L1 * L1)
|
|
+ //; H0 += LOPART(H1 * L1)
|
|
+ //; H0 += LOPART(L1 * H1)
|
|
+ //;
|
|
+ //; -------------------
|
|
+ //; L0 = L1
|
|
+ //; L0 = LOPART(L0 * L1)
|
|
+ //; H0 = H1
|
|
+ //; H0 = LOPART(H0 * L1)
|
|
+ //; H0 <<= 1; i.e. *= 2
|
|
+ //; L1 = HIPART(L1 * L1)
|
|
+ //; H0 += L1
|
|
+ //;
|
|
+ return "; muldi3_raw/B (%H0:%L0) = (%H1:%L1) * (%H2:%L2)\n"
|
|
+ "\tMOV\t%L1,%L0\n"
|
|
+ "\tMPY\t%L1,%L0\n"
|
|
+ "\tMOV\t%H1,%H0\n"
|
|
+ "\tMPY\t%H1,%H0\n"
|
|
+ "\tLSL\t1,%H0\n"
|
|
+ "\tMPY\t%L1,%L1\n"
|
|
+ "\tADD\t%L2,%H0";
|
|
+ } else if ((regno[0] == regno[1])&&(regno[1] != regno[2])) {
|
|
+ //; RA = RA * RB, with scratch Rx
|
|
+ //;
|
|
+ //; (H0:L0) = (H0:L0) * (H1:L1)
|
|
+ //; (H0:L0) = (H0*2^32 + L0) * (H1 * 2^32 + L1)
|
|
+ //; (H0:L0) = (H0*H1*2^64 + (H0*L1+L0*H1)*2^32 + L0 *L1)
|
|
+ //; = (H0*L1+L0*H1):(L0*L1)
|
|
+ //; Rx = L0
|
|
+ //; :L0 = LOPART(L1 * R0)
|
|
+ //; H0 = LOPART(H0 * L1)
|
|
+ //; H0 += H1 = LOPART(Rx * H1)
|
|
+ //; H0 += HIPART(L1 * Rx)
|
|
+ //;
|
|
+ return "; muldi3_raw/C (%H0:%L0) = (%H1:%L1) * (%H2:%L2)\n"
|
|
+ "\tMOV\t%L0,%3\n"
|
|
+ "\tMPY\t%L1,%L0\n"
|
|
+ "\tMOV\t%L1,%H0\n"
|
|
+ "\tMPY\t%H1,%H0\n"
|
|
+ "\tMPY\t%3,%H1\n"
|
|
+ "\tADD\t%H1,%H0\n"
|
|
+ "\tMPY\t%3,%L1\n"
|
|
+ "\tADD\t%L1,%H0";
|
|
+ } else {
|
|
+ //; RA = RB * RC
|
|
+ //;
|
|
+ //; (H0:L0) = (H1:L1) * (H2:L2)
|
|
+ //; (H0:L0) = (H1*2^32 + L1) * (H2 * 2^32 + L2)
|
|
+ //; (H0:L0) = (H1*H2*2^64 + (H1*L2+L1*H2)*2^32 + L1 *L2)
|
|
+ //; = (H1*L2+L1*H2):(L1*L2)
|
|
+ //; :L0 = LOPART(L1 * L2)
|
|
+ //; H0 = HIPART(L1 * L2)
|
|
+ //; H0 += LOPART(H1 * L2)
|
|
+ //; H0 += LOPART(L1 * H2)
|
|
+ //;
|
|
+ //; We can re-order this to try to save some registers
|
|
+ //;
|
|
+ //; H1 *= L0 // Was H1 * L2
|
|
+ //; :L0 = LOPART(L1 * L2)
|
|
+ //; H0 = LOPART(L1 * R1)
|
|
+ //; H0 += HIPART(L1 * H2)
|
|
+ //; H0 += H1
|
|
+ //;
|
|
+ return "; muldi3_raw/D (%H0:%L0) = (%H1:%L1) * (%H2:%L2)\n"
|
|
+ "\tMPY %L2,%H1 ; H1 = H1 * L2\n"
|
|
+ "\tMPY %L1,%H2 ; H2 = L1 * L2\n"
|
|
+ "\tMOV %L2,%L0 ; H0:L0 = L1 * L2\n"
|
|
+ "\tMOV %L2,%H0\n"
|
|
+ "\tMPY %L1,%L0\n"
|
|
+ "\tMPYUHI %L1,%H0\n"
|
|
+ "\tADD %H2,%H0 ; H0 += (H2 = L1 * H2)\n"
|
|
+ "\tADD %H1,%H0 ; H0 += (H1 = H1 * L2)";
|
|
+ }
|
|
+ }
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
|
+;
|
|
+;
|
|
+; Still missing DI instructions for smin:DI, smax:DI, movdicc, adddicc,
|
|
+; div:di, divu:di (library routine)
|
|
+;
|
|
+;
|
|
+;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;;
|
|
+;; Conditional arithmetic instructions
|
|
+;;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;
|
|
+;
|
|
+;
|
|
+;
|
|
+(define_insn "cstoredi4" ; Store 0 or 1 in %0 based on cmp between %2&%3
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (if_then_else:SI (match_operator 1 "ordered_comparison_operator"
|
|
+ [(match_operand:DI 2 "register_operand" "r")
|
|
+ (match_operand:DI 3 "register_operand" "r")])
|
|
+ (const_int 1) (const_int 0)))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ "(ZIP_HAS_DI)&&(0)"
|
|
+ {
|
|
+ switch(GET_CODE(operands[1])) {
|
|
+ case EQ: return "CLR\t%0\t; CSTORE-EQ\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.Z\t1,%0\n";
|
|
+ case NE: return "CLR\t%0\t; CSTORE-NE\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.NZ\t1,%0\n";
|
|
+ //; Missing LT
|
|
+ //; Missing LE
|
|
+ //; Missing GT
|
|
+ //; Missing GE
|
|
+ case LTU: return "CLR\t%0\t; CSTORE-LTU\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.C\t1,%0\n";
|
|
+ case LEU:
|
|
+ return "CLR\t%0\t; CSTORE-LEU\n\tCMP\t%H2,%H3\n\tCMP.Z\t%L2,%L3\n\tLDILO.NC\t1,%0\n";
|
|
+ case GTU: return "CLR\t%0\t; CSTORE-GTU\n\tCMP\t%H2,%H3\n\tCMP.Z\t%L2,%L3\n\tLDILO.C\t1,%0\n";
|
|
+ case GEU:
|
|
+ return "CLR\t%0\t; CSTORE-GEU\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.NC\t1,%0\n";
|
|
+ default:
|
|
+ gcc_unreachable();
|
|
+ }
|
|
+ }
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
|
+;
|
|
+;
|
|
+;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;;
|
|
+;; Comparison instructions, both compare and test
|
|
+;;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;
|
|
+;
|
|
+;
|
|
+(define_expand "cmpdi"
|
|
+ [(set (reg:CC CC_REG) (compare:CC
|
|
+ (match_operand:DI 0 "register_operand" "r")
|
|
+ (match_operand:DI 1 "nonmemory_operand" "")))]
|
|
+ ""
|
|
+ {
|
|
+ if (!REG_P(operands[1])) {
|
|
+ if (can_create_pseudo_p()) {
|
|
+ //; fprintf(stderr, "Generating pseudo register for compare\n");
|
|
+ rtx tmp = gen_reg_rtx(DImode);
|
|
+ emit_insn(gen_movdi(tmp,operands[1]));
|
|
+ operands[1] = tmp;
|
|
+ emit_insn(gen_cmpdi_reg(operands[0],tmp));
|
|
+ DONE;
|
|
+ } else FAIL;
|
|
+ }
|
|
+ })
|
|
+(define_insn "cmpdi_reg"
|
|
+ [(set (reg:CC CC_REG) (compare:CC
|
|
+ (match_operand:SI 0 "register_operand" "r")
|
|
+ (match_operand:SI 1 "register_operand" "r")))]
|
|
+ ""
|
|
+ "CMP\t%H1,%H0
|
|
+ CMP.Z\t%L1,%L0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+;
|
|
+;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;;
|
|
+;; Conditional move instructions, since these won't accept conditional
|
|
+;; execution RTL
|
|
+;;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;
|
|
+(define_expand "cbranchdi4"
|
|
+ [(set (pc) (if_then_else
|
|
+ (match_operator 0 "ordered_comparison_operator"
|
|
+ [(match_operand:DI 1 "register_operand" "r")
|
|
+ (match_operand:DI 2 "nonimmediate_operand" "")])
|
|
+ (label_ref (match_operand 3 "" ""))
|
|
+ (pc)))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ "(ZIP_HAS_DI)"
|
|
+ {
|
|
+ if (!REG_P(operands[2])) {
|
|
+ if ((CONST_INT_P(operands[2]))
|
|
+ &&(INTVAL(operands[2])> -(1l<<17))
|
|
+ &&(INTVAL(operands[2])<(1l<<17)-1)) {
|
|
+ emit_jump_insn(gen_cbranchdi4_internal(operands[0],
|
|
+ operands[1], operands[2], operands[3]));
|
|
+ DONE;
|
|
+ } if (can_create_pseudo_p()) {
|
|
+ rtx tmp = gen_reg_rtx(DImode);
|
|
+ emit_insn(gen_movsi(tmp, operands[2]));
|
|
+ operands[2] = tmp;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ if (REG_P(operands[2])) {
|
|
+ emit_jump_insn(gen_cbranchdi4_internal(operands[0],
|
|
+ operands[1], operands[2], operands[3]));
|
|
+ DONE;
|
|
+ }
|
|
+ })
|
|
+(define_insn "cbranchdi4_internal"
|
|
+ [(set (pc) (if_then_else
|
|
+ (match_operator 0 "ordered_comparison_operator"
|
|
+ [(match_operand:DI 1 "register_operand" "r,r,r")
|
|
+ (match_operand:DI 2 "nonmemory_operand" "K,x,r")])
|
|
+ (label_ref (match_operand 3 "" ""))
|
|
+ (pc)))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ "(ZIP_HAS_DI)"
|
|
+ {
|
|
+ return zip_cbranchdi(operands[0], operands[1], operands[2], operands[3]);
|
|
+ }
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
|
+;
|
|
+;
|
|
+;
|
|
+;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;;
|
|
+;; Unimplemented (or not yet implemented) RTL Codes
|
|
+;;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;
|
|
+;
|
|
+;
|
|
+;
|
|
+;(define_insn "addvdi4"
|
|
+; )
|
|
+;(define_insn "subvdi4"
|
|
+; )
|
|
+;(define_insn "mulvdi4"
|
|
+; )
|
|
+;(define_insn "umulvdi4"
|
|
+; )
|
|
+;(define_insn "umulvdi4"
|
|
+; )
|
|
+;(define_insn "negvdi3"
|
|
+; )
|
|
+;
|
|
+;(define_insn "maddsidi4"
|
|
+;(define_insn "umaddsidi4"
|
|
+;(define_insn "msubsidi4"
|
|
+;(define_insn "umsubsidi4"
|
|
+;
|
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip-float.md gcc-6.2.0-zip/gcc/config/zip/zip-float.md
|
|
--- gcc-6.2.0/gcc/config/zip/zip-float.md 1969-12-31 19:00:00.000000000 -0500
|
|
+++ gcc-6.2.0-zip/gcc/config/zip/zip-float.md 2017-01-10 14:01:42.029341062 -0500
|
|
@@ -0,0 +1,138 @@
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;;
|
|
+;; Filename: zip-float.md
|
|
+;;
|
|
+;; Project: Zip CPU -- a small, lightweight, RISC CPU soft core
|
|
+;;
|
|
+;; Purpose: This is the machine description of the ZipCPU floating point
|
|
+;; unit (if installed).
|
|
+;;
|
|
+;;
|
|
+;; Creator: Dan Gisselquist, Ph.D.
|
|
+;; Gisselquist Technology, LLC
|
|
+;;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;;
|
|
+;; Copyright (C) 2015,2017, Gisselquist Technology, LLC
|
|
+;;
|
|
+;; This program is free software (firmware): you can redistribute it and/or
|
|
+;; modify it under the terms of the GNU General Public License as published
|
|
+;; by the Free Software Foundation, either version 3 of the License, or (at
|
|
+;; your option) any later version.
|
|
+;;
|
|
+;; This program is distributed in the hope that it will be useful, but WITHOUT
|
|
+;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
|
+;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
|
+;; for more details.
|
|
+;;
|
|
+;; License: GPL, v3, as defined and found on www.gnu.org,
|
|
+;; http://www.gnu.org/licenses/gpl.html
|
|
+;;
|
|
+;;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;;
|
|
+;;
|
|
+;
|
|
+;
|
|
+;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;;
|
|
+;; Floating point Op-codes
|
|
+;;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;
|
|
+;
|
|
+;
|
|
+(define_insn "addsf3"
|
|
+ [(set (match_operand:SF 0 "register_operand" "=r")
|
|
+ (plus:SF (match_operand:SF 1 "register_operand" "0")
|
|
+ (match_operand:SF 2 "register_operand" "r")))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ "(ZIP_FPU)"
|
|
+ "FPADD %2,%0"
|
|
+ [(set_attr "ccresult" "unknown")])
|
|
+(define_insn "subsf3"
|
|
+ [(set (match_operand:SF 0 "register_operand" "=r")
|
|
+ (minus:SF (match_operand:SF 1 "register_operand" "0")
|
|
+ (match_operand:SF 2 "register_operand" "r")))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ "(ZIP_FPU)"
|
|
+ "FPSUB %2,%0"
|
|
+ [(set_attr "ccresult" "unknown")])
|
|
+(define_insn "mulsf3"
|
|
+ [(set (match_operand:SF 0 "register_operand" "=r")
|
|
+ (mult:SF (match_operand:SF 1 "register_operand" "0")
|
|
+ (match_operand:SF 2 "register_operand" "r")))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ "(ZIP_FPU)"
|
|
+ "FPMUL %2,%0"
|
|
+ [(set_attr "ccresult" "unknown")])
|
|
+(define_insn "divsf3"
|
|
+ [(set (match_operand:SF 0 "register_operand" "=r")
|
|
+ (div:SF (match_operand:SF 1 "register_operand" "0")
|
|
+ (match_operand:SF 2 "register_operand" "r")))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ "(ZIP_FPU)"
|
|
+ "FPDIV %2,%0"
|
|
+ [(set_attr "ccresult" "unknown")])
|
|
+; (define_insn "floatsisf2"
|
|
+; [(set (match_operand:SF 0 "register_operand" "=r"
|
|
+; (float:QI (match_operand:SF 1 "register_operand" "r"))))
|
|
+; (set (reg:CC CC_REG) (compare:CC (match_dup 1) (const_int 0)))]
|
|
+; "(ZIP_FPU)"
|
|
+; "FPI2F %1,%0")
|
|
+; (define_insn "floatunssisf2" ... ?)
|
|
+; (define_insn "fix_truncsfsi2"
|
|
+; [(set (match_operand:QI 0 "register_operand" "=r"
|
|
+; (float:SF (match_operand:SF 1 "register_operand" "r"))))
|
|
+; (set (reg:CC CC_REG) (compare:CC (match_dup 1) (const_int 0)))]
|
|
+; "(ZIP_FPU)"
|
|
+; "FPI2F %1,%0")
|
|
+; (define_insn "nearbyintsf2" ... ?)
|
|
+; (define_insn "truncsfsi2" ... ?)
|
|
+(define_expand "negsf2"
|
|
+ [(set (match_operand:SF 0 "register_operand" "=r")
|
|
+ (neg:SF (match_operand:SF 1 "register_operand" "0")))
|
|
+ ]
|
|
+ ""
|
|
+ {
|
|
+ operands[0] = gen_rtx_SUBREG(SImode, operands[0], 0);
|
|
+ if (can_create_pseudo_p()) {
|
|
+ rtx tmp = gen_reg_rtx(SImode);
|
|
+ emit_insn(gen_movsi_ldi(tmp,gen_int_mode(0x80000000,SImode)));
|
|
+ emit_insn(gen_xorsi3(operands[0], operands[0], tmp));
|
|
+ DONE;
|
|
+ } else {
|
|
+ emit_insn(gen_zip_bitrev(operands[0],operands[0]));
|
|
+ emit_insn(gen_iorsi3(operands[0], operands[0],
|
|
+ gen_int_mode(1,SImode)));
|
|
+ emit_insn(gen_zip_bitrev(operands[0],operands[0]));
|
|
+ DONE;
|
|
+ }
|
|
+ })
|
|
+(define_expand "abssf2"
|
|
+ [(set (match_operand:SF 0 "register_operand" "=r")
|
|
+ (abs:SF (match_operand:SF 1 "register_operand" "0")))
|
|
+ ]
|
|
+ ""
|
|
+ {
|
|
+ operands[0] = gen_rtx_SUBREG(SImode, operands[0], 0);
|
|
+ if (can_create_pseudo_p()) {
|
|
+ rtx tmp = gen_reg_rtx(SImode);
|
|
+ emit_insn(gen_movsi_ldi(tmp,gen_int_mode(0x7fffffff,SImode)));
|
|
+ emit_insn(gen_andsi3(operands[0], operands[0], tmp));
|
|
+ DONE;
|
|
+ } else {
|
|
+ emit_insn(gen_zip_bitrev(operands[0],operands[0]));
|
|
+ emit_insn(gen_andsi3(operands[0], operands[0],
|
|
+ gen_int_mode(-2,SImode)));
|
|
+ emit_insn(gen_zip_bitrev(operands[0],operands[0]));
|
|
+ DONE;
|
|
+ }
|
|
+ })
|
|
+;
|
|
+;
|
|
+; STILL MISSING:
|
|
+;
|
|
+;
|
|
+;
|
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip.h gcc-6.2.0-zip/gcc/config/zip/zip.h
|
|
--- gcc-6.2.0/gcc/config/zip/zip.h 1969-12-31 19:00:00.000000000 -0500
|
|
+++ gcc-6.2.0-zip/gcc/config/zip/zip.h 2017-03-03 09:30:57.671304970 -0500
|
|
@@ -0,0 +1,4114 @@
|
|
+////////////////////////////////////////////////////////////////////////////////
|
|
+//
|
|
+// Filename: gcc/config/zip/zip.h
|
|
+//
|
|
+// Project: Zip CPU backend for the GNU Compiler Collection
|
|
+//
|
|
+// Purpose:
|
|
+//
|
|
+// Creator: Dan Gisselquist, Ph.D.
|
|
+// Gisselquist Technology, LLC
|
|
+//
|
|
+////////////////////////////////////////////////////////////////////////////////
|
|
+//
|
|
+// Copyright (C) 2016-2017, Gisselquist Technology, LLC
|
|
+//
|
|
+// This program is free software (firmware): you can redistribute it and/or
|
|
+// modify it under the terms of the GNU General Public License as published
|
|
+// by the Free Software Foundation, either version 3 of the License, or (at
|
|
+// your option) any later version.
|
|
+//
|
|
+// This program is distributed in the hope that it will be useful, but WITHOUT
|
|
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
|
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
+// for more details.
|
+// for more details.
|
+//
|
+//
|
+// You should have received a copy of the GNU General Public License along
|
+// You should have received a copy of the GNU General Public License along
|
+// with this program. (It's in the $(ROOT)/doc directory, run make with no
|
+// with this program. (It's in the $(ROOT)/doc directory, run make with no
|
+// target there if the PDF file isn't present.) If not, see
|
+// target there if the PDF file isn't present.) If not, see
|
| Line 3194... |
Line 4168... |
+#define ZIP_USER 0 // Assume we are in supervisor mode
|
+#define ZIP_USER 0 // Assume we are in supervisor mode
|
+#define ZIP_MULTIPLY 1 // Assume we have multiply instructions
|
+#define ZIP_MULTIPLY 1 // Assume we have multiply instructions
|
+#define ZIP_DIVIDE 1 // Assume we have divide instructions
|
+#define ZIP_DIVIDE 1 // Assume we have divide instructions
|
+#define ZIP_FPU 0 // Assume we have no floating point instructions
|
+#define ZIP_FPU 0 // Assume we have no floating point instructions
|
+#define ZIP_PIPELINED 1 // Assume our instructions are pipelined
|
+#define ZIP_PIPELINED 1 // Assume our instructions are pipelined
|
+#define ZIP_VLIW 1 // Assume we have the VLIW feature
|
+#define ZIP_THUMB 1 // Assume we have the THUMB feature
|
+#define ZIP_ATOMIC (ZIP_PIPELINED)
|
+#define ZIP_ATOMIC (ZIP_PIPELINED)
|
+#define ZIP_PIC 0 // Attempting to produce PIC code, with GOT
|
+#define ZIP_PIC 0 // Attempting to produce PIC code, with GOT
|
+#define ZIP_HAS_DI 1
|
+#define ZIP_HAS_DI 1
|
+// Should we use the peephole optimizations?
|
+// Should we use the peephole optimizations?
|
+#define ZIP_PEEPHOLE 1 // 0 means no peephole optimizations.
|
+#define ZIP_PEEPHOLE 1 // 0 means no peephole optimizations.
|
+// How about the new long multiply instruction set?
|
+#define ZIP_NOT_AN_INSTRUCTION "NAI\t;// This is not an instruction. Getting here implies a compiler error. Please contact help support\n"
|
+#define ZIP_LONGMPY 1 // 0 means use the old instruction set
|
|
+#define ZIP_NEW_CONDITION_CODE 0 // 0 means use the old condition codes
|
|
+
|
+
|
+// Zip has 16 registers in each user mode.
|
+// Zip has 16 registers in each user mode.
|
+// Register 15 is the program counter (PC)
|
+// Register 15 is the program counter (PC)
|
+// Register 14 is the condition codes (CC)
|
+// Register 14 is the condition codes (CC)
|
+// Register 13 is the stack pointer (SP)
|
+// Register 13 is the stack pointer (SP)
|
| Line 3221... |
Line 4193... |
+#define zip_CC 14
|
+#define zip_CC 14
|
+#define zip_SP 13
|
+#define zip_SP 13
|
+#define zip_FP 12
|
+#define zip_FP 12
|
+#define zip_GOT 11
|
+#define zip_GOT 11
|
+// #define zip_AP 10 // We're using a PSEUDO REG instead
|
+// #define zip_AP 10 // We're using a PSEUDO REG instead
|
|
+#define zip_R5 5 // Used for the static chain, if it exists
|
+#define zip_R1 1
|
+#define zip_R1 1
|
+#define zip_R0 0
|
+#define zip_R0 0
|
|
+#define zip_LR zip_R0 // Link Register is also R0
|
+
|
+
|
+#define ZIP_FIRST_ARG_REGNO 1
|
+#define ZIP_FIRST_ARG_REGNO 1
|
+#define ZIP_LAST_ARG_REGNO 5
|
+#define ZIP_LAST_ARG_REGNO 5
|
+#define NUM_ARG_REGS (ZIP_LAST_ARG_REGNO-ZIP_FIRST_ARG_REGNO+1)
|
+#define NUM_ARG_REGS (ZIP_LAST_ARG_REGNO-ZIP_FIRST_ARG_REGNO+1)
|
+#define MAX_PARM_REGS (ZIP_LAST_ARG_REGNO-ZIP_FIRST_ARG_REGNO+1)
|
+#define MAX_PARM_REGS (ZIP_LAST_ARG_REGNO-ZIP_FIRST_ARG_REGNO+1)
|
| Line 3240... |
Line 4214... |
+#define FILE_ASM_OP "\t.file\n"
|
+#define FILE_ASM_OP "\t.file\n"
|
+
|
+
|
+/* Output and Generation of Labels */
|
+/* Output and Generation of Labels */
|
+#define GLOBAL_ASM_OP "\t.global\t"
|
+#define GLOBAL_ASM_OP "\t.global\t"
|
+
|
+
|
+#undef BITS_PER_UNIT
|
+#define BITS_PER_WORD 32
|
+#define BITS_PER_UNIT (32)
|
|
+
|
|
+/* Assembler Commands for Alignment */
|
|
+#define ASM_OUTPUT_ALIGN(STREAM,POWER) \
|
|
+ { int pwr = POWER; fprintf(STREAM, "\t.p2align %d\n", (pwr<2)?2:pwr); }
|
|
+
|
+
|
+
|
+
|
+/* A C compound statement to output to stdio stream STREAM the assembler syntax
|
+/* A C compound statement to output to stdio stream STREAM the assembler syntax
|
+ * for an instruction operand X. */
|
+ * for an instruction operand X. */
|
+#define PRINT_OPERAND(STREAM, X, CODE) zip_print_operand(STREAM, X, CODE)
|
+#define PRINT_OPERAND(STREAM, X, CODE) zip_print_operand(STREAM, X, CODE)
|
| Line 3280... |
Line 4249... |
+
|
+
|
+
|
+
|
+/* The best alignment to use in cases where we have a choice. */
|
+/* The best alignment to use in cases where we have a choice. */
|
+#define FASTEST_ALIGNMENT BITS_PER_WORD
|
+#define FASTEST_ALIGNMENT BITS_PER_WORD
|
+
|
+
|
+/* MAX_FIXED_MODE_SIZE -- An integer expression for the size in bits of the
|
|
+ * largest integer machine mode that should actually be used. All integer
|
|
+ * machine modes of this size and smaller can be used for structures and unions
|
|
+ * with the appropriate sizes. If this macro is undefined,
|
|
+ * GET_MODE_BITSIZE(DImode) is assumed.
|
|
+ *
|
|
+ * ZipCPU -- The default looks good enough for us.
|
|
+ */
|
|
+
|
|
+/* Generate Code for Profiling
|
+/* Generate Code for Profiling
|
+ */
|
+ */
|
+#define FUNCTION_PROFILER(FILE,LABELNO) (abort(), 0)
|
+#define FUNCTION_PROFILER(FILE,LABELNO) (abort(), 0)
|
+
|
+
|
+
|
+
|
| Line 3335... |
Line 4295... |
+ * difference between the two is that LIB_SPEC is used at the end of the
|
+ * difference between the two is that LIB_SPEC is used at the end of the
|
+ * command given to the linker.
|
+ * command given to the linker.
|
+ *
|
+ *
|
+ * If this macro is not defined, a default is provided that loads the standard
|
+ * If this macro is not defined, a default is provided that loads the standard
|
+ * C library from the usual place. See 'gcc.c'.
|
+ * C library from the usual place. See 'gcc.c'.
|
|
+ *
|
|
+ * ZipCPU ... We need this at its default value. It is necessary to build
|
|
+ * the various GCC libraries that depend upon one another and newlib. Hence,
|
|
+ * as an example we *must* include the library containing strnlen or libgfortran
|
|
+ * will not. Alternatively, we might figure out how to pass arguments to the
|
|
+ * compiler via the configure process ... but we'll just allow this to have its
|
|
+ * default value for now.
|
+ */
|
+ */
|
+#undef LIB_SPEC
|
+// #undef LIB_SPEC
|
+// #define LIB_SPEC "%{!g:-lc} %{g:-lg} -lzip"
|
+// #define LIB_SPEC "%{!g:-lc} %{g:-lg} -lzip"
|
+#define LIB_SPEC ""
|
+// #define LIB_SPEC ""
|
+
|
+
|
+/* LIBGCC_SPEC ... Another C string constant that tells the GCC driver program
|
+/* LIBGCC_SPEC ... Another C string constant that tells the GCC driver program
|
+ * hoow and when to place a reference to 'libgcc.a' into the linker command
|
+ * hoow and when to place a reference to 'libgcc.a' into the linker command
|
+ * line. This constant is placed both before and after the value of LIB_SPEC.
|
+ * line. This constant is placed both before and after the value of LIB_SPEC.
|
+ *
|
+ *
|
| Line 3421... |
Line 4388... |
+ * command line parameters we've been given indicate that our CPU has. That
|
+ * command line parameters we've been given indicate that our CPU has. That
|
+ * way, code can be adjusted depending upon the CPU's capabilities.
|
+ * way, code can be adjusted depending upon the CPU's capabilities.
|
+ */
|
+ */
|
+#define TARGET_CPU_CPP_BUILTINS() \
|
+#define TARGET_CPU_CPP_BUILTINS() \
|
+ { builtin_define("__ZIPCPU__"); \
|
+ { builtin_define("__ZIPCPU__"); \
|
|
+ builtin_define("__IEEE_BIG_ENDIAN"); \
|
|
+ builtin_define("_LDBL_EQ_DBL"); \
|
+ if (ZIP_FPU) builtin_define("__ZIPFPU__"); \
|
+ if (ZIP_FPU) builtin_define("__ZIPFPU__"); \
|
|
+ else builtin_define("_SOFT_FLOAT"); \
|
+ if (ZIP_ATOMIC) builtin_define("__ZIPATOMIC__"); \
|
+ if (ZIP_ATOMIC) builtin_define("__ZIPATOMIC__"); \
|
+ }
|
+ }
|
+ // If (zip_param_has_fpu) builtin_define("__ZIPFPU__");
|
+ // If (zip_param_has_fpu) builtin_define("__ZIPFPU__");
|
+ // If (zip_param_has_div) builtin_define("__ZIPDIV__");
|
+ // If (zip_param_has_div) builtin_define("__ZIPDIV__");
|
+ // If (zip_param_has_mpy) builtin_define("__ZIPMPY__");
|
+ // If (zip_param_has_mpy) builtin_define("__ZIPMPY__");
|
| Line 3483... |
Line 4453... |
+ * any RTL has begun. The intention is to allow the initialization of the
|
+ * any RTL has begun. The intention is to allow the initialization of the
|
+ * function pointer init_machine_status.
|
+ * function pointer init_machine_status.
|
+ */
|
+ */
|
+// #warning "I may need to define this to handle function return addresses ..."
|
+// #warning "I may need to define this to handle function return addresses ..."
|
+
|
+
|
|
+
|
+/* 17.05 Storage Layout */
|
+/* 17.05 Storage Layout */
|
+
|
+
|
|
+
|
+/* Storage Layout */
|
+/* Storage Layout */
|
+#define BITS_BIG_ENDIAN 0 // MSB has highest number
|
+#define BITS_BIG_ENDIAN 0 // MSB has highest number
|
+#define BYTES_BIG_ENDIAN 1 // 1 if MSB is lowest number
|
+#define BYTES_BIG_ENDIAN 1 // 1 if MSB is lowest number
|
+#define WORDS_BIG_ENDIAN 1 // 1 if MSW is lowest number
|
+#define WORDS_BIG_ENDIAN 1 // 1 if MSW is lowest number
|
+#define FLOAT_WORDS_BIG_ENDIAN 1
|
+#define FLOAT_WORDS_BIG_ENDIAN 1
|
+#define BITS_PER_WORD 32
|
+#define UNITS_PER_WORD 4 // Storage units in a word, pwr of 2:1-8
|
+// #define MAX_BITS_PER_WORD // defaults to BITS_PER_WORD
|
|
+#define UNITS_PER_WORD 1 // Storage units in a word, pwr of 2:1-8
|
|
+#define MIN_UNITS_PER_WORD 1 // Default is UNITS_PER_WORD
|
|
+/* POINTER_SIZE ... Width of a pointer in bits. You must specify a value no
|
+/* POINTER_SIZE ... Width of a pointer in bits. You must specify a value no
|
+ * wider than the width of Pmode. If it is not equal to the width of Pmode,
|
+ * wider than the width of Pmode. If it is not equal to the width of Pmode,
|
+ * you must define POINTERS_EXTEND_UNSIGNED. If you do not specify a value the
|
+ * you must define POINTERS_EXTEND_UNSIGNED. If you do not specify a value the
|
+ * default is BITS_PER_WORD.
|
+ * default is BITS_PER_WORD.
|
+ *
|
+ *
|
+ * ZipCPU --- All of our pointers are 32-bits, the width of our address bus.
|
+ * ZipCPU --- All of our pointers are 32-bits, the width of our address bus.
|
+ */
|
+ */
|
+#define POINTER_SIZE 32 // Ptr width in bits
|
+#define POINTER_SIZE 32 // Ptr width in bits
|
|
+
|
+/* POINTERS_EXTEND_UNSIGNED ... A C expression that determines how pointers
|
+/* POINTERS_EXTEND_UNSIGNED ... A C expression that determines how pointers
|
+ * should be extended from ptr_mode to either Pmode or word_mode. It is greater
|
+ * should be extended from ptr_mode to either Pmode or word_mode. It is greater
|
+ * than zero if pointers should be zero-extended, zero if they should be sign
|
+ * than zero if pointers should be zero-extended, zero if they should be sign
|
+ * extended, and negative if some other conversion is needed. In the last case,
|
+ * extended, and negative if some other conversion is needed. In the last case,
|
+ * the extension is done by the target's ptr_extend instruction.
|
+ * the extension is done by the target's ptr_extend instruction.
|
+ *
|
+ *
|
+ * You need not define this macro if the ptr_mode, Pmode, and word_mode are all
|
+ * You need not define this macro if the ptr_mode, Pmode, and word_mode are all
|
+ * the same width.
|
+ * the same width.
|
+ *
|
+ *
|
+ * ZipCPU --- While we shouldn't need this, QImode and HImode have the same
|
+ * ZipCPU --- We don't need to define this macro, since PMode and ptr_mode, and
|
+ * number of bits as SImode. Therefore, one might wish to convert between the
|
+ * our word_mode (SImode) all have the same width.
|
+ * two. Hence, we specify how we would do that here.
|
|
+ */
|
+ */
|
+#define POINTERS_EXTEND_UNSIGNED 1
|
+// #define POINTERS_EXTEND_UNSIGNED 1
|
+
|
+
|
+/* PROMOTE_MODE(m,unsignedp,type) ... A macro to update m and unsignedp when an
|
+/* PROMOTE_MODE(m,unsignedp,type) ... A macro to update m and unsignedp when an
|
+ * object whose type is type and which has he specified mode and signedness is
|
+ * object whose type is type and which has he specified mode and signedness is
|
+ * to be stored in a register. This macro is only called when type is a scalar
|
+ * to be stored in a register. This macro is only called when type is a scalar
|
+ * type.
|
+ * type.
|
| Line 3537... |
Line 4506... |
+ * 64-bits. On such machines, set unsignedp according to which kind of extension
|
+ * 64-bits. On such machines, set unsignedp according to which kind of extension
|
+ * is more efficient.
|
+ * is more efficient.
|
+ *
|
+ *
|
+ * Do not define this macro if it would never modify m.
|
+ * Do not define this macro if it would never modify m.
|
+ *
|
+ *
|
+ * ZipCPU --- We need to always (if possible) promote everything to SImode where
|
+ * ZipCPU ---
|
+ * we can handle things. HImode and QImode just don't make sense on this CPU.
|
|
+ */
|
+ */
|
+#define PROMOTE_MODE(M,U,T) if ((GET_MODE_CLASS(M)==MODE_INT)&&(GET_MODE_SIZE(M)<2)) (M)=SImode;
|
+#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
|
|
+ do { \
|
|
+ if ((GET_MODE_CLASS(MODE) == MODE_INT) \
|
|
+ && (GET_MODE_SIZE(MODE) < 4)) { \
|
|
+ (MODE) = SImode; \
|
|
+ (UNSIGNEDP) = 1; \
|
|
+ } \
|
|
+ } while(0)
|
+
|
+
|
+// TARGET_PROMOTE_FUNCTION_MODE
|
+// TARGET_PROMOTE_FUNCTION_MODE
|
|
+#define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
|
|
+
|
+/* PARM_BOUNDARY ... Normal alignment required for function parameters on the
|
+/* PARM_BOUNDARY ... Normal alignment required for function parameters on the
|
+ * stack, in bits. All stack parameters receive at least this much alignment
|
+ * stack, in bits. All stack parameters receive at least this much alignment
|
+ * regardless of data type. On most machines, this is the same as the size of
|
+ * regardless of data type. On most machines, this is the same as the size of
|
+ * an integer.
|
+ * an integer.
|
+ */
|
+ */
|
| Line 3595... |
Line 4572... |
+/* BIGGEST_FIELD_ALIGNMENT ... Biggest alignment that any structure or union
|
+/* BIGGEST_FIELD_ALIGNMENT ... Biggest alignment that any structure or union
|
+ * field can require on this machine, in bits. If defined, this overrides
|
+ * field can require on this machine, in bits. If defined, this overrides
|
+ * BIGGEST_ALIGNMENT for structure and union fields only, unless the field
|
+ * BIGGEST_ALIGNMENT for structure and union fields only, unless the field
|
+ * alignment has been set by the __attribute__((aligned(n))) construct.
|
+ * alignment has been set by the __attribute__((aligned(n))) construct.
|
+ */
|
+ */
|
+#define BIGGEST_FIELD_ALIGNMENT BITS_PER_UNIT
|
+#define BIGGEST_FIELD_ALIGNMENT BITS_PER_WORD
|
+
|
+
|
+/* ADJUST_FIELD_ALIGN
|
+/* ADJUST_FIELD_ALIGN(FIELD, COMPUTED) ... An expression for the alignment of
|
|
+ * a structure field FIELD if the alignment computed in the usual way (including
|
|
+ * applying BIGGEST_ALIGNMENT and BIGGEST_FIELD_ALIGNMENT) is COMPUTED.
|
+ */
|
+ */
|
+#define ADJUST_FIELD_ALIGN(A,B) BITS_PER_WORD
|
+// #define ADJUST_FIELD_ALIGN(A,B) BITS_PER_WORD
|
+
|
+
|
+/* MAX_STACK_ALIGNMENT
|
+/* MAX_STACK_ALIGNMENT ... Biggest stack alignment guaranteed by the backend.
|
|
+ * Use this macro to specify the maximum alignment of a variable on the stack.
|
|
+ *
|
|
+ * If not defined, the default value is STACK_BOUNDARY
|
+ */
|
+ */
|
+#define MAX_STACK_ALIGNMENT BITS_PER_WORD
|
+// #define MAX_STACK_ALIGNMENT BITS_PER_WORD
|
+
|
+
|
+/* MAX_OFILE_ALIGNMENT
|
+/* MAX_OFILE_ALIGNMENT
|
+ */
|
+ */
|
+
|
+
|
+/* DATA_ALIGNMENT(TYPE, BASIC-ALIGN) ... If defined, a C expression to compute
|
+/* DATA_ALIGNMENT(TYPE, BASIC-ALIGN) ... If defined, a C expression to compute
|
| Line 3615... |
Line 4597... |
+ * BASIC-ALIGN is the alignment that the object would ordinarily have. The
|
+ * BASIC-ALIGN is the alignment that the object would ordinarily have. The
|
+ * value of this macro is used instead of that alignment to align the object.
|
+ * value of this macro is used instead of that alignment to align the object.
|
+ *
|
+ *
|
+ * If this macro is not defined, then BASIC-ALIGN is used.
|
+ * If this macro is not defined, then BASIC-ALIGN is used.
|
+ *
|
+ *
|
+ * ZipCPU -- in hindsight, if this macro is not defined then the compiler is
|
+ * ZipCPU --
|
+ * broken. So we define it to be our fastest alignment, or 32-bits.
|
|
+ */
|
+ */
|
+#define DATA_ALIGNMENT(TYPE, ALIGN) BITS_PER_WORD
|
+// #define DATA_ALIGNMENT(TYPE, ALIGN) BITS_PER_WORD
|
+
|
+
|
+
|
+
|
+/* DATA_ABI_ALIGNMENT(TYPE,BASIC-ALIGN)
|
+/* DATA_ABI_ALIGNMENT(TYPE,BASIC-ALIGN)
|
+ */
|
+ */
|
+
|
+
|
| Line 3640... |
Line 4621... |
+ */
|
+ */
|
+#define CONSTANT_ALIGNMENT(EXP, ALIGN) BITS_PER_WORD
|
+#define CONSTANT_ALIGNMENT(EXP, ALIGN) BITS_PER_WORD
|
+
|
+
|
+/* LOCAL_ALIGNMENT(TYPE,BASIC-ALIGN) ... If defined ...
|
+/* LOCAL_ALIGNMENT(TYPE,BASIC-ALIGN) ... If defined ...
|
+ */
|
+ */
|
+#define LOCAL_ALIGNMENT(TYP,ALIGN) BITS_PER_WORD
|
+// #define LOCAL_ALIGNMENT(TYP,ALIGN) BITS_PER_WORD
|
+
|
+
|
+/* TARGET_VECTOR_ALIGNMENT
|
+/* TARGET_VECTOR_ALIGNMENT
|
+ */
|
+ */
|
+
|
+
|
+/* STACK_SLOT_ALIGNMENT
|
+/* STACK_SLOT_ALIGNMENT
|
+ */
|
+ */
|
+#define STACK_SLOT_ALIGNMENT(T,M,B) BITS_PER_WORD
|
+#define STACK_SLOT_ALIGNMENT(T,M,B) BITS_PER_WORD
|
+
|
+
|
+/* LOCAL_DECL_ALIGNMEN(DECL)
|
+/* LOCAL_DECL_ALIGNMEN(DECL)
|
+ */
|
+ */
|
+#define LOCAL_DECL_ALIGNMENT(DECL) BITS_PER_WORD
|
+// #define LOCAL_DECL_ALIGNMENT(DECL) BITS_PER_WORD
|
+
|
+
|
+/* MINIMUM_ALIGNMENT
|
+/* MINIMUM_ALIGNMENT
|
+ */
|
+ */
|
+#define MINIMUM_ALIGNMENT(EXP,MOD,ALIGN) BITS_PER_WORD
|
+// #define MINIMUM_ALIGNMENT(EXP,MOD,ALIGN) BITS_PER_WORD
|
+
|
+
|
+/* EMPTY_FIELD_BOUNDARY
|
+/* EMPTY_FIELD_BOUNDARY
|
+ * Alignment of field after 'int : 0' in a structure.
|
+ * Alignment of field after 'int : 0' in a structure.
|
+ */
|
+ */
|
+#define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
|
+#define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
|
| Line 3671... |
Line 4652... |
+
|
+
|
+/* STRICT_ALIGNMENT ... Set this nonzero if move instructions will actually
|
+/* STRICT_ALIGNMENT ... Set this nonzero if move instructions will actually
|
+ * fail to work when given unaligned data. If instructions will merely go
|
+ * fail to work when given unaligned data. If instructions will merely go
|
+ * slower in that case, define this macro as 0.
|
+ * slower in that case, define this macro as 0.
|
+ *
|
+ *
|
+ * ZipCPU -- Since we have defined our smallest addressable unit to be a 32-bit
|
+ * ZipCPU --
|
+ * word (one byte, on our machine), and since reading any amount of 32-bit words
|
|
+ * is easy, then there really are no instructions that will ever fail.
|
|
+ */
|
+ */
|
+#define STRICT_ALIGNMENT 0
|
+#define STRICT_ALIGNMENT 1
|
+
|
+
|
+/* PCC_BITFIELD_TYPE_MATTERS -- define this if you wish to imitate the the way
|
+/* PCC_BITFIELD_TYPE_MATTERS -- define this if you wish to imitate the the way
|
+ * other C compilers handle alignment of bit-fields and the structures that
|
+ * other C compilers handle alignment of bit-fields and the structures that
|
+ * contain them.
|
+ * contain them.
|
+ *
|
+ *
|
| Line 3710... |
Line 4689... |
+ * largest integer machine mode that should actually be used. All integer
|
+ * largest integer machine mode that should actually be used. All integer
|
+ * machine modes of this size or smaller can be used for structures and unions
|
+ * machine modes of this size or smaller can be used for structures and unions
|
+ * with the appropriate sizes. If this macro is undefined,
|
+ * with the appropriate sizes. If this macro is undefined,
|
+ * GET_MODE_BITSIZE(DImode) is assumed.
|
+ * GET_MODE_BITSIZE(DImode) is assumed.
|
+ *
|
+ *
|
+ * ZipCPU ... Get_MOD_BITSIZE(DImode) will be 64, and this is really not the
|
+ * ZipCPU ... Get_MODE_BITSIZE(DImode) will be 64, and this really is the
|
+ * size on bits of the largest integer machine mode. However, that's the case
|
+ * size in bits of the largest integer machine mode. However, that's the case
|
+ * with most DI implementations: A long is two words, spliced together. We'd
|
+ * with most DI implementations: A long is two words, spliced together. We'd
|
+ * like to support that eventually, but we need to get there. Hence, let's use
|
+ * like to support that eventually, but we need to get there. Hence, let's use
|
+ * compile time flag (ZIP_HAS_DI) that we can enable when we're ready.
|
+ * compile time flag (ZIP_HAS_DI) that we can enable when we're ready.
|
+ */
|
+ */
|
+#if (ZIP_HAS_DI != 0)
|
+#undef MAX_FIXED_MODE_SIZE
|
+#define MAX_FIXED_MODE_SIZE 64
|
+#ifdef ZIP_HAS_DI
|
|
+# define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE(DImode)
|
+#else
|
+#else
|
+#define MAX_FIXED_MODE_SIZE 32
|
+# define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE(SImode)
|
+#endif
|
+#endif
|
+
|
+
|
+
|
+
|
|
+
|
+/* 17.06 Layout of Source Language Data Types */
|
+/* 17.06 Layout of Source Language Data Types */
|
+
|
+
|
+#undef CHAR_TYPE_SIZE
|
|
+#undef SHORT_TYPE_SIZE
|
|
+#undef INT_TYPE_SIZE
|
|
+#undef LONG_TYPE_SIZE
|
+#undef LONG_TYPE_SIZE
|
+#undef LONG_LONG_TYPE_SIZE
|
+#undef LONG_LONG_TYPE_SIZE
|
+//
|
+//
|
+#define CHAR_TYPE_SIZE 32
|
|
+#define SHORT_TYPE_SIZE 32
|
|
+#define INT_TYPE_SIZE 32
|
|
+#define LONG_TYPE_SIZE 64
|
+#define LONG_TYPE_SIZE 64
|
+#define LONG_LONG_TYPE_SIZE 64
|
+#define LONG_LONG_TYPE_SIZE 64
|
+// BOOL_TYPE_SIZE defaults to CHAR_TYPE_SIZE
|
|
+#undef FLOAT_TYPE_SIZE
|
|
+#undef DOUBLE_TYPE_SIZE
|
|
+#undef LONG_DOUBLE_TYPE_SIZE
|
|
+#define FLOAT_TYPE_SIZE 32
|
|
+#define DOUBLE_TYPE_SIZE 64 // This'll need to be done via emulation
|
|
+#define LONG_DOUBLE_TYPE_SIZE 64 // This'll need to be done via emulation
|
|
+// SHORT_FRAC_TYPE_SIZE
|
+// SHORT_FRAC_TYPE_SIZE
|
+// LONG_FFRACT_TYPE_SIZE
|
+// LONG_FFRACT_TYPE_SIZE
|
+// LONG_LONG_FRACT_TIME_SIZE
|
+// LONG_LONG_FRACT_TIME_SIZE
|
+#undef SHORT_ACCUM_TYPE_SIZE
|
|
+#undef ACCUM_TYPE_SIZE
|
|
+#undef LONG_ACCUM_TYPE_SIZE
|
|
+#define SHORT_ACCUM_TYPE_SIZE SHORT_TYPE_SIZE
|
|
+#define ACCUM_TYPE_SIZE INT_TYPE_SIZE
|
|
+#define LONG_ACCUM_TYPE_SIZE LONG_TYPE_SIZE
|
|
+
|
+
|
+/* LIBGCC2_GNU_PREFIX ... This macro corresponds to the TARGET_GNU_PREFIX target
|
+/* LIBGCC2_GNU_PREFIX ... This macro corresponds to the TARGET_GNU_PREFIX target
|
+ * hook and should be defined if that hook is overriden to be true. It causes
|
+ * hook and should be defined if that hook is overriden to be true. It causes
|
+ * function names in libgcc to be changed to use a __gnu_ prefix for their name
|
+ * function names in libgcc to be changed to use a __gnu_ prefix for their name
|
+ * rather than the default __. A port which uses this macro should also arrange
|
+ * rather than the default __. A port which uses this macro should also arrange
|
| Line 3793... |
Line 4755... |
+/* DEFAULT_SIGNED_CHAR ... An expression whose value is 1 or 0, according to
|
+/* DEFAULT_SIGNED_CHAR ... An expression whose value is 1 or 0, according to
|
+ * whether the type char should be signed or unsigned by default. The user
|
+ * whether the type char should be signed or unsigned by default. The user
|
+ * can always override this default with the options -fsigned-char and
|
+ * can always override this default with the options -fsigned-char and
|
+ * -funsigned-char.
|
+ * -funsigned-char.
|
+ *
|
+ *
|
+ * ZipCPU--let's go with the default behavior.
|
+ * ZipCPU--Our hardware produces unsigned characters (and shorts) by default,
|
|
+ * so let's stick to that.
|
+ */
|
+ */
|
+#define DEFAULT_SIGNED_CHAR 1
|
+#define DEFAULT_SIGNED_CHAR 0
|
+
|
+
|
+/* TARGET_DEFAULT_SHORT_ENUMS(VOID) ... This target hook should return true if
|
+/* TARGET_DEFAULT_SHORT_ENUMS(VOID) ... This target hook should return true if
|
+ * the compiler should give an enum type only as many bytes as it takes to
|
+ * the compiler should give an enum type only as many bytes as it takes to
|
+ * represent the range of possible values of that type. It should return
|
+ * represent the range of possible values of that type. It should return
|
+ * false if all enum types should be allocated like int.
|
+ * false if all enum types should be allocated like int.
|
| Line 3838... |
Line 4801... |
+/* WCHAR_TYPE ... A C expression for a string describing the name of the data
|
+/* WCHAR_TYPE ... A C expression for a string describing the name of the data
|
+ * type to use for wide characters. The typedef name wchar_t is defined using
|
+ * type to use for wide characters. The typedef name wchar_t is defined using
|
+ * the contents of the string. If you don't define this macro, the default is
|
+ * the contents of the string. If you don't define this macro, the default is
|
+ * 'int'--good enough for ZipCPU.
|
+ * 'int'--good enough for ZipCPU.
|
+ */
|
+ */
|
|
+// #define WCHAR_TYPE "int"
|
+
|
+
|
+/* WCHAR_TYPE_SIZE ... A C expression for the size in bits of the data type for
|
+/* WCHAR_TYPE_SIZE ... A C expression for the size in bits of the data type for
|
+ * wide characters. This is used in cpp, which cannot make use of WCHAR_TYPE.
|
+ * wide characters. This is used in cpp, which cannot make use of WCHAR_TYPE.
|
|
+ *
|
|
+ * ZipCPU -- This defaults to INT_TYPE_SIZE, which will work for us
|
+ */
|
+ */
|
+#undef WCHAR_TYPE_SIZE
|
+// #define WCHAR_TYPE_SIZE 32
|
+#define WCHAR_TYPE_SIZE 32
|
|
+
|
+
|
+/* WINT_TYPE ... A C expression for a string describing the name of the data
|
+/* WINT_TYPE ... A C expression for a string describing the name of the data
|
+ * type to use for wide characters passed to printf and returned from getwc.
|
+ * type to use for wide characters passed to printf and returned from getwc.
|
+ * The typedef name wint_t is defined using the contents of the string. See
|
+ * The typedef name wint_t is defined using the contents of the string. See
|
+ *
|
+ *
|
+ * ZipCPU -- If you don't define this macro, the default is "unsigned int"--also
|
+ * ZipCPU -- The default should work well enough for us.
|
+ * best for us again.
|
|
+ */
|
+ */
|
|
+// #define WINT_TYPE "int"
|
+
|
+
|
+/* INTMAX_TYPE ... A C expression for a string describing the name of the
|
+/* INTMAX_TYPE ... A C expression for a string describing the name of the
|
+ * data type that can represent any value of any standard or extended signed
|
+ * data type that can represent any value of any standard or extended signed
|
+ * integer type. The typedef name intmax_t is defined using the contents of
|
+ * integer type. The typedef name intmax_t is defined using the contents of
|
+ * the string.
|
+ * the string.
|
| Line 3872... |
Line 4837... |
+#define SIG_ATOMIC_TYPE "int"
|
+#define SIG_ATOMIC_TYPE "int"
|
+#else
|
+#else
|
+#define SIG_ATOMIC_TYPE NULL // We have no atomic types, but registers
|
+#define SIG_ATOMIC_TYPE NULL // We have no atomic types, but registers
|
+#endif
|
+#endif
|
+#undef INT8_TYPE
|
+#undef INT8_TYPE
|
+#define INT8_TYPE NULL // We have no 8-bit integer type
|
+#define INT8_TYPE "char"
|
+#undef INT16_TYPE
|
+#undef INT16_TYPE
|
+#define INT16_TYPE NULL
|
+#define INT16_TYPE "short int"
|
+#undef INT32_TYPE
|
+#undef INT32_TYPE
|
+#define INT32_TYPE "int"
|
+#define INT32_TYPE "int"
|
+#undef UINT8_TYPE
|
+#undef UINT8_TYPE
|
+#define UINT8_TYPE NULL
|
+#define UINT8_TYPE "unsigned char"
|
+#undef UINT16_TYPE
|
+#undef UINT16_TYPE
|
+#define UINT16_TYPE NULL
|
+#define UINT16_TYPE "short unsigned int"
|
+#undef UINT32_TYPE
|
+#undef UINT32_TYPE
|
+#define UINT32_TYPE "unsigned int"
|
+#define UINT32_TYPE "unsigned int"
|
+#undef INT_LEAST8_TYPE
|
+#undef INT_LEAST8_TYPE
|
+#define INT_LEAST8_TYPE "int"
|
+#define INT_LEAST8_TYPE "char"
|
+#undef INT_LEAST16_TYPE
|
+#undef INT_LEAST16_TYPE
|
+#define INT_LEAST16_TYPE "int"
|
+#define INT_LEAST16_TYPE "short int"
|
+#undef INT_LEAST32_TYPE
|
+#undef INT_LEAST32_TYPE
|
+#define INT_LEAST32_TYPE "int"
|
+#define INT_LEAST32_TYPE "int"
|
+#undef UINT_LEAST8_TYPE
|
+#undef UINT_LEAST8_TYPE
|
+#define UINT_LEAST8_TYPE "unsigned int"
|
+#define UINT_LEAST8_TYPE "unsigned char"
|
+#undef UINT_LEAST16_TYPE
|
+#undef UINT_LEAST16_TYPE
|
+#define UINT_LEAST16_TYPE "unsigned int"
|
+#define UINT_LEAST16_TYPE "short unsigned int"
|
+#undef UINT_LEAST32_TYPE
|
+#undef UINT_LEAST32_TYPE
|
+#define UINT_LEAST32_TYPE "unsigned int"
|
+#define UINT_LEAST32_TYPE "unsigned int"
|
+#undef INT_FAST8_TYPE
|
+#undef INT_FAST8_TYPE
|
+#define INT_FAST8_TYPE "int"
|
+#define INT_FAST8_TYPE "char"
|
+#undef INT_FAST16_TYPE
|
+#undef INT_FAST16_TYPE
|
+#define INT_FAST16_TYPE "int"
|
+#define INT_FAST16_TYPE "short int"
|
+#undef INT_FAST32_TYPE
|
+#undef INT_FAST32_TYPE
|
+#define INT_FAST32_TYPE "int"
|
+#define INT_FAST32_TYPE "int"
|
+#undef UINT_FAST8_TYPE
|
+#undef UINT_FAST8_TYPE
|
+#define UINT_FAST8_TYPE "unsigned int"
|
+#define UINT_FAST8_TYPE "unsigned char"
|
+#undef UINT_FAST16_TYPE
|
+#undef UINT_FAST16_TYPE
|
+#define UINT_FAST16_TYPE "unsigned int"
|
+#define UINT_FAST16_TYPE "short unsigned int"
|
+#undef UINT_FAST32_TYPE
|
+#undef UINT_FAST32_TYPE
|
+#define UINT_FAST32_TYPE "unsigned int"
|
+#define UINT_FAST32_TYPE "unsigned int"
|
+#undef INTPTR_TYPE
|
+#undef INTPTR_TYPE
|
+#define INTPTR_TYPE "unsigned int"
|
+#define INTPTR_TYPE "unsigned int"
|
+#undef UINTPTR_TYPE
|
+#undef UINTPTR_TYPE
|
| Line 4076... |
Line 5041... |
+ * hold a value of mode MODE.
|
+ * hold a value of mode MODE.
|
+ *
|
+ *
|
+ * On a machine where all registers are exactly one word, a suitable definition
|
+ * On a machine where all registers are exactly one word, a suitable definition
|
+ * is given of ((GET_MODE_SIZE(MODE)+UNITS_PER_WORD-1)/UNITS_PER_WORD.
|
+ * is given of ((GET_MODE_SIZE(MODE)+UNITS_PER_WORD-1)/UNITS_PER_WORD.
|
+ *
|
+ *
|
+ * On ZipCPU, we might do
|
|
+ * ((((MODE)==DImode)||((MODE)==DFmode))?2:1)
|
|
+ * but I think the default (above) code should work as well. Hence, let's stick
|
|
+ * with the default, lest someone try to create larger modes (TImode, OImode,
|
|
+ * XImode) and expect us to follow them properly some how.
|
|
+ *
|
|
+ * Okay, now in hind sight, we know that the default doesn't work for our
|
|
+ * architecture, since GET_MODE_SIZE(SImode)=4, not 1. Thus, let's rearrange
|
|
+ * this expression to work in bits rather than in bytes and we'll know more
|
|
+ * of what we are doing.
|
|
+ */
|
+ */
|
+#undef HARD_REGNO_NREGS
|
+#undef HARD_REGNO_NREGS
|
+#define HARD_REGNO_NREGS(REGNO, MODE) ((GET_MODE_SIZE(MODE)+UNITS_PER_WORD-1)\
|
+#define HARD_REGNO_NREGS(REGNO, MODE) ((GET_MODE_SIZE(MODE)+UNITS_PER_WORD-1)\
|
+ / (UNITS_PER_WORD))
|
+ / (UNITS_PER_WORD))
|
+
|
+
|
| Line 4150... |
Line 5105... |
+ */
|
+ */
|
+#define MODES_TIEABLE_P(M1,M2) 1
|
+#define MODES_TIEABLE_P(M1,M2) 1
|
+
|
+
|
+/* TARGET_HARD_REGNO_SCRATCH_OK(REGNO)
|
+/* TARGET_HARD_REGNO_SCRATCH_OK(REGNO)
|
+ * This target hook should return true if it is OK to use a hard register
|
+ * This target hook should return true if it is OK to use a hard register
|
+ * REGNO has a scratch register in peephole2. One common use of this macro is
|
+ * REGNO as a scratch register in peephole2. One common use of this macro is
|
+ * to prevent using of a register that is not saved by a prologue in an
|
+ * to prevent using of a register that is not saved by a prologue in an
|
+ * interrupt handler. The default version of this hook always returns true.
|
+ * interrupt handler. The default version of this hook always returns true.
|
+ *
|
+ *
|
+ * ZipCPU --- the default works for us as well. If you are in an interrupt
|
+ * ZipCPU --- the default works for us as well. If you are in an interrupt
|
+ * context, you have an entirely new set of registers (the supervisor set), so
|
+ * context, you have an entirely new set of registers (the supervisor set), so
|
| Line 4173... |
Line 5128... |
+ *
|
+ *
|
+ * Zip CPU has no stack-like registers, as their definition is different from
|
+ * Zip CPU has no stack-like registers, as their definition is different from
|
+ * the ZipCPU stack pointer register.
|
+ * the ZipCPU stack pointer register.
|
+ */
|
+ */
|
+
|
+
|
+// #define ZIP_REG_BYTE_SIZE 1
|
|
+
|
|
+/* 17.08 Register Classes */
|
+/* 17.08 Register Classes */
|
+
|
+
|
+/* enum reg_class ... An enumerate type that must be defined with all the
|
+/* enum reg_class ... An enumerate type that must be defined with all the
|
+ * register class names as enumerated values. NO_REGS must be first. ALL_REGS
|
+ * register class names as enumerated values. NO_REGS must be first. ALL_REGS
|
+ * must be the last register class, followed by one more enumerated value,
|
+ * must be the last register class, followed by one more enumerated value,
|
| Line 4418... |
Line 5371... |
+ * user set of registers. However, we're not building for that mode (now),
|
+ * user set of registers. However, we're not building for that mode (now),
|
+ * so we'll leave this at the default of NO_REGS.
|
+ * so we'll leave this at the default of NO_REGS.
|
+ */
|
+ */
|
+
|
+
|
+/* TARGET_CSTORE_MODE(ICODE) ... Defines the machine mode to use for the
|
+/* TARGET_CSTORE_MODE(ICODE) ... Defines the machine mode to use for the
|
+ * boolean result of conditional store patterns. The OCIDE argument is the
|
+ * boolean result of conditional store patterns. The ICODE argument is the
|
+ * instruction code for the cstore being performed. Not defining this hook is
|
+ * instruction code for the cstore being performed. Not defining this hook is
|
+ * the same as accepting the mode encoded into operand 0 of the cstore expander
|
+ * the same as accepting the mode encoded into operand 0 of the cstore expander
|
+ * patterns.
|
+ * patterns.
|
+ *
|
+ *
|
+ * ??? ZipCPU --- I don't follow this documentation. We'll leave this at the
|
+ * ??? ZipCPU --- I don't follow this documentation. We'll leave this at the
|
| Line 4490... |
Line 5443... |
+
|
+
|
+/* STACK_ALIGNMENT_NEEDED ... Define to zero to disable final alignment of the
|
+/* STACK_ALIGNMENT_NEEDED ... Define to zero to disable final alignment of the
|
+ * stack during reload. The nonzero default for this macro is suitable for most
|
+ * stack during reload. The nonzero default for this macro is suitable for most
|
+ * ports.
|
+ * ports.
|
+ *
|
+ *
|
+ * ZipCPU --- we'll leave this at the default, although if any alignment code
|
+ * ZipCPU --- Yes, our stack needs to be aligned. The default should work
|
+ * shows up on the stack we may need to adjust it.
|
+ * nicely.
|
+ */
|
+ */
|
+
|
+
|
+/* STACK_POINTER_OFFSET ... Offset from the SP register to the first location at
|
+/* STACK_POINTER_OFFSET ... Offset from the SP register to the first location at
|
+ * which outgoing arguments are placed. If not specified, the default value
|
+ * which outgoing arguments are placed. If not specified, the default value
|
+ * of zero is used. This is the proper value for most machines.
|
+ * of zero is used. This is the proper value for most machines.
|
| Line 4554... |
Line 5507... |
+ * of the COUNT frame, or the frame pointer of the COUNT-1 frame if
|
+ * of the COUNT frame, or the frame pointer of the COUNT-1 frame if
|
+ * RETURN_ADDR_IN_PREVIOUS_FRAME is nonzero. The value of the expression must
|
+ * RETURN_ADDR_IN_PREVIOUS_FRAME is nonzero. The value of the expression must
|
+ * always be the correct address when COUNT is nonzero, but may be NULL_RTX if
|
+ * always be the correct address when COUNT is nonzero, but may be NULL_RTX if
|
+ * there is no way to determine the return address of other frames.
|
+ * there is no way to determine the return address of other frames.
|
+ *
|
+ *
|
+ * ZipCPU --- I have no idea how we'd do this, so let's just return NULL_RTX.
|
+ * ZipCPU --- Our answer for the current frame is ... it depends. If we can
|
|
+ * force the use of a frame in every debug context, we could compute this for
|
|
+ * COUNT != 0. For now, we'll just look at the registers we save and return
|
|
+ * where the return address is in the current frame. To do that, though, we
|
|
+ * need some help from C.
|
+ */
|
+ */
|
+#undef RETURN_ADDR_RTX
|
+#undef RETURN_ADDR_RTX
|
+#define RETURN_ADDR_RTX(COUNT,FRAMEADDR) NULL_RTX
|
+#define RETURN_ADDR_RTX(COUNT,FRAMEADDR) zip_return_addr_rtx(COUNT,FRAMEADDR)
|
+
|
+
|
+/* RETURN_ADDR_IN_PREVIOUS_FRAME ... Define this macro to nonzero value if the
|
+/* RETURN_ADDR_IN_PREVIOUS_FRAME ... Define this macro to nonzero value if the
|
+ * return address of a particular stack frame is accessed from the frame pointer
|
+ * return address of a particular stack frame is accessed from the frame pointer
|
+ * of the previous stack frame. The zero default for this macro is suitable
|
+ * of the previous stack frame. The zero default for this macro is suitable
|
+ * for most ports.
|
+ * for most ports.
|
| Line 4579... |
Line 5536... |
+ * ZipCPU --- While our incoming return address could theoretically be in any
|
+ * ZipCPU --- While our incoming return address could theoretically be in any
|
+ * register, our machine description file is going to place it into register
|
+ * register, our machine description file is going to place it into register
|
+ * R0, so that's what we return here.
|
+ * R0, so that's what we return here.
|
+ */
|
+ */
|
+#undef INCOMING_RETURN_ADDR_RTX
|
+#undef INCOMING_RETURN_ADDR_RTX
|
+#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG(SImode, zip_R0)
|
+#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG(SImode, zip_LR)
|
+
|
+
|
+
|
+
|
+/* DWARF_ALT_FRAME_RETURN_COLUMN
|
+/* DWARF_ALT_FRAME_RETURN_COLUMN
|
+ */
|
+ */
|
+
|
+
|
| Line 4632... |
Line 5589... |
+ * least 2 data registers, but should define 4 if their are enough free
|
+ * least 2 data registers, but should define 4 if their are enough free
|
+ * registers.
|
+ * registers.
|
+ *
|
+ *
|
+ * You must define this macro if you want to support call frame exception
|
+ * You must define this macro if you want to support call frame exception
|
+ * handling like that provided by DWARF 2.
|
+ * handling like that provided by DWARF 2.
|
|
+ *
|
|
+ * ZipCPU -- We copy much of our definition from Moxie.
|
+ */
|
+ */
|
+#define EH_RETURN_DATA_REGNO(N) (((N<ZIP_FIRST_ARG_REGNO)||(N>ZIP_LAST_ARG_REGNO))?(N-1):INVALID_REGNUM)
|
+#define EH_RETURN_DATA_REGNO(N) ((N<3)?(N+ZIP_FIRST_ARG_REGNO):INVALID_REGNUM)
|
+
|
+
|
+/* EH_RETURN_STACKADJ_RTX ... A C expression whose value is RTL representing
|
+/* EH_RETURN_STACKADJ_RTX ... A C expression whose value is RTL representing
|
+ * a location in which to store a stack adjustment to be applied before function
|
+ * a location in which to store a stack adjustment to be applied before function
|
+ * return. This is used to unwind the stack to an exception handler's call
|
+ * return. This is used to unwind the stack to an exception handler's call
|
+ * frame. It will be assigned zero on code paths that return normally.
|
+ * frame. It will be assigned zero on code paths that return normally.
|
| Line 4662... |
Line 5621... |
+ * EH_RETURN_STACKADJ_RTX will have already been assigned, so it may be used
|
+ * EH_RETURN_STACKADJ_RTX will have already been assigned, so it may be used
|
+ * to calculate the location of the target call frame.
|
+ * to calculate the location of the target call frame.
|
+ *
|
+ *
|
+ * If you want to support call frame exception handling, you must define either
|
+ * If you want to support call frame exception handling, you must define either
|
+ * this macro or the eh_return instruction pattern.
|
+ * this macro or the eh_return instruction pattern.
|
|
+ *
|
|
+ * ZipCPU --- We again copy from Moxie
|
+ */
|
+ */
|
+// #warning "I don't know what to do here."
|
+#define EH_RETURN_HANDLER_RTX \
|
|
+ gen_frame_mem(Pmode, plus_constant(Pmode, frame_pointer_rtx, UNITS_PER_WORD))
|
+
|
+
|
+/*
|
+/*
|
+ *
|
+ *
|
+ *
|
+ *
|
+ *
|
+ *
|
| Line 4803... |
Line 5765... |
+ * Do not define this macro unless there is no other way to get the return
|
+ * Do not define this macro unless there is no other way to get the return
|
+ * address from the stack.
|
+ * address from the stack.
|
+ *
|
+ *
|
+ * ZipCPU---we need this.
|
+ * ZipCPU---we need this.
|
+ */
|
+ */
|
+#define RETURN_ADDRESS_REGNUM zip_R0
|
+#define RETURN_ADDRESS_REGNUM zip_LR
|
+
|
+
|
+
|
+
|
+/* STATIC_CHAIN_REGNUM ... Register numbers used for passing a function's
|
+/* STATIC_CHAIN_REGNUM ... Register numbers used for passing a function's
|
+ * static chain pointer. If register windows are used, the register number as
|
+ * static chain pointer. If register windows are used, the register number as
|
+ * seen by the called function is STATIC_CHAIN_INCOMING_REGNUM, while the
|
+ * seen by the called function is STATIC_CHAIN_INCOMING_REGNUM, while the
|
+ * register number as seen by the calling function is STATIC_CHAIN_REGNUM. If
|
+ * register number as seen by the calling function is STATIC_CHAIN_REGNUM. If
|
+ * these register are the same, STATIC_CHAIN_INCOMING_REGNUM need not be
|
+ * these register are the same, STATIC_CHAIN_INCOMING_REGNUM need not be
|
+ * defined.
|
+ * defined.
|
+ *
|
+ *
|
+ * ZipCPU doesn't have register windows, so we don't need to define this.
|
+ * ZipCPU --- even without register windows, we still need to pick an
|
|
+ * (arbitrary) register to pass the pointer to the static chain in the case of
|
|
+ * nested functions. Let's arbitrarily pick R5, and ... see how that works for
|
|
+ * us.
|
+ */
|
+ */
|
+// #warning "I have no reason to believe this will even work"
|
+#define STATIC_CHAIN_REGNUM zip_R5
|
+#define STATIC_CHAIN_REGNUM zip_GOT
|
|
+
|
+
|
+/* TARGET_STATIC_CHAIN ... This hook replaces the use of STATIC_CHAIN_REGNUM et
|
+/* TARGET_STATIC_CHAIN ... This hook replaces the use of STATIC_CHAIN_REGNUM et
|
+ * al for targets that may use different static chain locations for different
|
+ * al for targets that may use different static chain locations for different
|
+ * nested functions. This may be required if the target has function attributes
|
+ * nested functions. This may be required if the target has function attributes
|
+ * that affect the calling conventions of the function and those calling
|
+ * that affect the calling conventions of the function and those calling
|
+ * conventions use different static chain locations.
|
+ * conventions use different static chain locations.
|
+ *
|
+ *
|
+ * ZipCPU --- don't need this.
|
+ * ZipCPU --- don't need this.
|
+ */
|
+ */
|
+// #define STATIC_CHAIN_REGNUM zip_R11
|
+// #define TARGET_STATIC_CHAIN zip_R11
|
+
|
+
|
+
|
+
|
+/* DWARF_FRAME_REGISTERS ... This macro specifies the maximum number of hard
|
+/* DWARF_FRAME_REGISTERS ... This macro specifies the maximum number of hard
|
+ * registers that can be saved in a call frame. This is used to size data
|
+ * registers that can be saved in a call frame. This is used to size data
|
+ * structures used in DWARF2 exception handling.
|
+ * structures used in DWARF2 exception handling.
|
| Line 5275... |
Line 6239... |
+ * ZipCPU --- Default sounds good to me.
|
+ * ZipCPU --- Default sounds good to me.
|
+ */
|
+ */
|
+
|
+
|
+
|
+
|
+/* TARGET_SCALAR_MODE_SUPPORTED_P(MODE) ... Define this to return nonzero if
|
+/* TARGET_SCALAR_MODE_SUPPORTED_P(MODE) ... Define this to return nonzero if
|
+ * the port is prepared to handl instructions involving scalar mode MODE. For
|
+ * the port is prepared to handle instructions involving scalar mode MODE. For
|
+ * a scalar mode to be considered supported, all the basic arithmetic and
|
+ * a scalar mode to be considered supported, all the basic arithmetic and
|
+ * comparisons must work.
|
+ * comparisons must work.
|
+ *
|
+ *
|
+ * The default version of this hook returns true for any mode required to
|
+ * The default version of this hook returns true for any mode required to
|
+ * handle the basic C types (as defined by the port). Included here are the
|
+ * handle the basic C types (as defined by the port). Included here are the
|
+ * double-word arithmetic supported by the code in optabs.c.
|
+ * double-word arithmetic supported by the code in optabs.c.
|
|
+ *
|
|
+ * ZipCPU --- This controls whether a data type of the given mode can even be
|
|
+ * declared in C/C++. Without support for such a mode, you can't even declare
|
|
+ * a data type of this type. Hence, we should support SFmode and DFmode, even
|
|
+ * though the hardware *may* support SFmode, and it will *never* support DFmode.
|
+ */
|
+ */
|
+#undef TARGET_SCALAR_MODE_SUPPORTED_P
|
+#undef TARGET_SCALAR_MODE_SUPPORTED_P
|
+#define TARGET_SCALAR_MODE_SUPPORTED_P zip_scalar_mode_supported_p
|
+#define TARGET_SCALAR_MODE_SUPPORTED_P zip_scalar_mode_supported_p
|
+
|
+
|
+/* TARGET_VECTOR_MODE_SUPPORTED_P(MODE) ... Define this to return nonzero if the
|
+/* TARGET_VECTOR_MODE_SUPPORTED_P(MODE) ... Define this to return nonzero if the
|
| Line 5297... |
Line 6266... |
+#undef TARGET_VECTOR_MODE_SUPPORTED_P
|
+#undef TARGET_VECTOR_MODE_SUPPORTED_P
|
+#define TARGET_VECTOR_MODE_SUPPORTED_P hook_bool_mode_false
|
+#define TARGET_VECTOR_MODE_SUPPORTED_P hook_bool_mode_false
|
+
|
+
|
+/* TARGET_ARRAY_MODE_SUPPORTED_P(MODE, NELEMS) ... Return true if GCC should
|
+/* TARGET_ARRAY_MODE_SUPPORTED_P(MODE, NELEMS) ... Return true if GCC should
|
+ * try to use a scalar mode to store an array of NELEMS elements, given that
|
+ * try to use a scalar mode to store an array of NELEMS elements, given that
|
+ * each element has mode MODE. Returning true here overrides the usual MAX_FIXED_MODE limit and allows GCC to use any defined integer mode.
|
+ * each element has mode MODE. Returning true here overrides the usual
|
|
+ * MAX_FIXED_MODE limit and allows GCC to use any defined integer mode.
|
+ *
|
+ *
|
+ * ZipCPU---Sounds good.
|
+ * ZipCPU---Sounds good.
|
+ */
|
+ */
|
+// #undef TARGET_ARRAY_MODE_SUPPORTED_P
|
+// #undef TARGET_ARRAY_MODE_SUPPORTED_P
|
+// #define TARGET_ARRAY_MODE_SUPPORTED_P zip_array_mode_supported_p
|
+// #define TARGET_ARRAY_MODE_SUPPORTED_P zip_array_mode_supported_p
|
| Line 5498... |
Line 6468... |
+ */
|
+ */
|
+
|
+
|
+/* TRAMPOLINE_SIZE ... A C expression for the size (in bytes) of the trampoline
|
+/* TRAMPOLINE_SIZE ... A C expression for the size (in bytes) of the trampoline
|
+ * as an integer.
|
+ * as an integer.
|
+ *
|
+ *
|
+ * ZipCPU--it's three instructions, or 96 bits. However, 32-bits is our minimal
|
+ * ZipCPU--it's three instructions, or 96 bits: BREV, LDILO, and JMP
|
+ * addressible unit, so what size do we offer here? We'll stick with the number
|
|
+ * of bytes, but we may need to change this later.
|
|
+ *
|
+ *
|
+ */
|
+ */
|
+// #warning "May need to redefine trampoline_size in words, not bytes"
|
+// #warning "May need to redefine trampoline_size in words, not bytes"
|
+#undef TRAMPOLINE_SIZE
|
+#undef TRAMPOLINE_SIZE
|
+#define TRAMPOLINE_SIZE 3
|
+#define TRAMPOLINE_SIZE 3*UNITS_PER_WORD
|
+
|
+
|
+/* TRAMPOLINE_ALIGNMENT ... alignment required for trampolines, in bits.
|
+/* TRAMPOLINE_ALIGNMENT ... alignment required for trampolines, in bits.
|
+ *
|
+ *
|
+ * Well that's well known in ZipCPU --- 32-bits.
|
+ * Well that's well known in ZipCPU --- 32-bits.
|
+ */
|
+ */
|
+#undef TRAMPOLINE_ALIGNMENT
|
+#undef TRAMPOLINE_ALIGNMENT
|
+#define TRAMPOLINE_ALIGNMENT 32
|
+#define TRAMPOLINE_ALIGNMENT UNITS_PER_WORD
|
+
|
+
|
+/* void TARGET_TRAMPOLINE_INIT(RTX,TREE,RTX CH) ... This hook is called to
|
+/* void TARGET_TRAMPOLINE_INIT(RTX,TREE,RTX CH) ... This hook is called to
|
+ * initialize a trampoline. m_tramp is an RTX for the memory block for the
|
+ * initialize a trampoline. m_tramp is an RTX for the memory block for the
|
+ * trampoline; TREE is the FUNCTION_DECL for the nested fucntion; CH is an
|
+ * trampoline; TREE is the FUNCTION_DECL for the nested fucntion; CH is an
|
+ * rtx for the static chain value that should be passed to the function when
|
+ * rtx for the static chain value that should be passed to the function when
|
| Line 5544... |
Line 6512... |
+ * macro would typically be a series of asm statements. Both BEG and END are
|
+ * macro would typically be a series of asm statements. Both BEG and END are
|
+ * pointer expressions.
|
+ * pointer expressions.
|
+ *
|
+ *
|
+ * ZipCPU --- Ouch! We have no way to do this (yet)!
|
+ * ZipCPU --- Ouch! We have no way to do this (yet)!
|
+ */
|
+ */
|
|
+#define CLEAR_INSN_CACHE(BEG,END) gcc_assert(0);
|
+
|
+
|
+/* TRANSFER_FROM_TRAMPOLINE ... Define this macro is trampolines need a special
|
+/* TRANSFER_FROM_TRAMPOLINE ... Define this macro is trampolines need a special
|
+ * subroutine to do their work. The macro should expand to a series of asm
|
+ * subroutine to do their work. The macro should expand to a series of asm
|
+ * statements which will be compiled with GCC. They go in a library function
|
+ * statements which will be compiled with GCC. They go in a library function
|
+ * named __transfer_from_trampoline.
|
+ * named __transfer_from_trampoline.
|
| Line 5805... |
Line 6774... |
+/* TARGET_MIN_ANCHOR_OFFSET ... The minimum offset that should be applied to
|
+/* TARGET_MIN_ANCHOR_OFFSET ... The minimum offset that should be applied to
|
+ * a section anchor. On most targets, it should be the smallest offset that
|
+ * a section anchor. On most targets, it should be the smallest offset that
|
+ * can be applied to a base register while still giving a legitimate address for
|
+ * can be applied to a base register while still giving a legitimate address for
|
+ * every mode. The default value is 0.
|
+ * every mode. The default value is 0.
|
+ *
|
+ *
|
+ * On the Zip CPU, this is the minimum operand B offset to a LOD or STO
|
+ * On the Zip CPU, this is the minimum operand B offset to a LW or SW
|
+ * operation, which would be a signed 14 bit number.
|
+ * operation, which would be a signed 14 bit number.
|
+ */
|
+ */
|
+#undef TARGET_MIN_ANCHOR_OFFSET
|
+#undef TARGET_MIN_ANCHOR_OFFSET
|
+#define TARGET_MIN_ANCHOR_OFFSET zip_min_anchor_offset
|
+#define TARGET_MIN_ANCHOR_OFFSET zip_min_anchor_offset
|
+
|
+
|
| Line 5828... |
Line 6797... |
+ * If ASM_OUTPUT_DEF is available, the hook's default definition uses it to
|
+ * If ASM_OUTPUT_DEF is available, the hook's default definition uses it to
|
+ * define the symbol as '. + SYMBOL_REF_BLOCK_OFFSET(RTL)'. If ASM_OUTPUT_DEF
|
+ * define the symbol as '. + SYMBOL_REF_BLOCK_OFFSET(RTL)'. If ASM_OUTPUT_DEF
|
+ * is not available, the hook's default definition is NULL, which disables the
|
+ * is not available, the hook's default definition is NULL, which disables the
|
+ * use of section anchors altogether.
|
+ * use of section anchors altogether.
|
+ *
|
+ *
|
+ * Section anchors will be very valuable in Zip CPU assembly, therefore we
|
+ * Section anchors would be very valuable in Zip CPU assembly, therefore we
|
+ * must define this hook.
|
+ * must define this hook. However ... no one else seems to ever define these
|
|
+ * hooks, so I really dont have much of an example to work with
|
+ */
|
+ */
|
|
+// #warning "Come back to this"
|
+// #undef TARGET_ASM_OUTPUT_ANCHOR
|
+// #undef TARGET_ASM_OUTPUT_ANCHOR
|
+// #define TARGET_ASM_OUTPUT_ANCHOR zip_asm_output_anchor
|
+// #define TARGET_ASM_OUTPUT_ANCHOR zip_asm_output_anchor
|
+
|
+
|
+/* TARGET_USE_ANCHORS_FOR_SYMBOL_P(RTX) ... Return true if GCC should attempt
|
+/* TARGET_USE_ANCHORS_FOR_SYMBOL_P(RTX) ... Return true if GCC should attempt
|
+ * to use anchors to access SYMBOL_REF X. You can assume SYMBOL_REF_HAS_BLOCK_INFO_P(X) and !SYMBOL_REF_ANCHOR_P(X).
|
+ * to use anchors to access SYMBOL_REF X. You can assume
|
|
+ * SYMBOL_REF_HAS_BLOCK_INFO_P(X) and !SYMBOL_REF_ANCHOR_P(X).
|
+ *
|
+ *
|
+ * The default version is correct for most targets, but you might need to intercept this hook to handle things like target specific attributes or target-specific sections.
|
+ * The default version is correct for most targets, but you might need to
|
|
+ * intercept this hook to handle things like target specific attributes or
|
|
+ * target-specific sections.
|
+ *
|
+ *
|
+ * Not knowing anything more, we'll leave the default as is for the Zip CPU.
|
+ * Not knowing anything more, we'll leave the default as is for the Zip CPU.
|
+ */
|
+ */
|
+// #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
|
+// #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
|
+// #define TARGET_USE_ANCHORS_FOR_SYMBOL_P zip_use_anchors_for_symbol_p
|
+// #define TARGET_USE_ANCHORS_FOR_SYMBOL_P zip_use_anchors_for_symbol_p
|
| Line 6072... |
Line 7046... |
+ *
|
+ *
|
+ * On the Zip CPU, constant function addresses--especially relative ones,
|
+ * On the Zip CPU, constant function addresses--especially relative ones,
|
+ * can be optimized into a single cycle delay. Register jumps will always
|
+ * can be optimized into a single cycle delay. Register jumps will always
|
+ * stall the whole (5-stage) pipeline.
|
+ * stall the whole (5-stage) pipeline.
|
+ */
|
+ */
|
+#define NO_FUNCTION_CSE
|
+#define NO_FUNCTION_CSE true
|
+
|
+
|
+/* TARGET_RTX_COSTS(X,CODE,OUTER,OPNO,TOTAL,SPD) ... This target hook describes
|
+/* TARGET_RTX_COSTS(X,CODE,OUTER,OPNO,TOTAL,SPD) ... This target hook describes
|
+ * the relative costs of RTL expressions.
|
+ * the relative costs of RTL expressions.
|
+ *
|
+ *
|
+ * The cost may depend on the precise form of the expression, which is avaialble
|
+ * The cost may depend on the precise form of the expression, which is avaialble
|
| Line 6139... |
Line 7113... |
+#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 0
|
+#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 0
|
+// #define LEGITIMATE_PIC_OPERAND_P(X) should evaluate to X(GOT) only
|
+// #define LEGITIMATE_PIC_OPERAND_P(X) should evaluate to X(GOT) only
|
+
|
+
|
+/* 17.20 Defining the Output Assembler Language */
|
+/* 17.20 Defining the Output Assembler Language */
|
+
|
+
|
+/* 17.20.4 Output of Data */
|
+/* 17.20.2 Output of Data */
|
+
|
+
|
+#undef TARGET_ASM_ALIGNED_HI_OP
|
|
+#undef TARGET_ASM_ALIGNED_SI_OP
|
|
+#define TARGET_ASM_UNALIGNED_HI_OP "\t.byte\t"
|
|
+#define TARGET_ASM_UNALIGNED_SI_OP "\t.byte\t"
|
|
+/* These hooks (above) specify assembly directives for creating certain kinds
|
+/* These hooks (above) specify assembly directives for creating certain kinds
|
+ * of integer objects. The TARGET_ASM_BYTE_OP directive creates a byte-sized
|
+ * of integer objects. The TARGET_ASM_BYTE_OP directive creates a byte-sized
|
+ * object. The TARGET_ASMALIGNED_HI_OP one creates an aligned two-byte object
|
+ * object. The TARGET_ASMALIGNED_HI_OP one creates an aligned two-byte object
|
+ * and so on. Any of the hookd may be NULL, indicating that no suitable
|
+ * and so on. Any of the hookd may be NULL, indicating that no suitable
|
+ * directive is available.
|
+ * directive is available.
|
| Line 6156... |
Line 7126... |
+ * The compiler will print these strings at the start of a new line, followed
|
+ * The compiler will print these strings at the start of a new line, followed
|
+ * immediately by the object's initial value. In most cases, the string should
|
+ * immediately by the object's initial value. In most cases, the string should
|
+ * contain a tab, a pseudo op, and then another tab.
|
+ * contain a tab, a pseudo op, and then another tab.
|
+ */
|
+ */
|
+
|
+
|
|
+#undef TARGET_ASM_ALIGNED_HI_OP
|
|
+#undef TARGET_ASM_ALIGNED_SI_OP
|
|
+// #undef TARGET_ASM_ALIGNED_DI_OP
|
|
+#define TARGET_ASM_ALIGNED_HI_OP ".short"
|
|
+// The assembler is set up to call a 4-byte integer a long. This definition of
|
|
+// a long isn't consistent with the compilers definition. For this reason,
|
|
+// the ZipCPU backend for the GNU Assembler defines a long as a 64-bit number,
|
|
+// and an int as a 32-bit number.
|
|
+#define TARGET_ASM_ALIGNED_SI_OP ".int"
|
|
+// #define TARGET_ASM_ALIGNED_DI_OP ".long"
|
|
+
|
|
+
|
+/* 17.20.4 Output and Generation of Labels */
|
+/* 17.20.4 Output and Generation of Labels */
|
+
|
+
|
+/* ASM_OUTPUT_LABEL
|
+/* ASM_OUTPUT_LABEL
|
+ * ... A default definition of this macro is provided which is correct for
|
+ * ... A default definition of this macro is provided which is correct for
|
+ * most systems.
|
+ * most systems.
|
| Line 6334... |
Line 7316... |
+ */
|
+ */
|
+
|
+
|
+/* TARGET_ASM_LABEL_ALIGN */
|
+/* TARGET_ASM_LABEL_ALIGN */
|
+/* Assembler Commands for Alignment */
|
+/* Assembler Commands for Alignment */
|
+#define ASM_OUTPUT_ALIGN(STREAM,POWER) \
|
+#define ASM_OUTPUT_ALIGN(STREAM,POWER) \
|
+ { int pwr = POWER; fprintf(STREAM, "\t.p2align %d\n", (pwr<2)?2:pwr); }
|
+ do { fprintf(STREAM, "\t.align\t%d\n", POWER); } while (0)
|
+
|
|
+
|
+
|
+
|
+
|
+/* 17.21 Controlling Debugging Information Format */
|
+/* 17.21 Controlling Debugging Information Format */
|
+/* 17.22 Cross Compilation and Floating Point */
|
+/* 17.22 Cross Compilation and Floating Point */
|
+
|
+
|
| Line 6397... |
Line 7378... |
+ */
|
+ */
|
+#define HAS_LONG_COND_BRANCH true
|
+#define HAS_LONG_COND_BRANCH true
|
+
|
+
|
+/* HAS_LONG_UNCOND_BRANCH ... Define this boolean macro to indicate whether
|
+/* HAS_LONG_UNCOND_BRANCH ... Define this boolean macro to indicate whether
|
+ * or not your architecture has unconditional branches that can span all of
|
+ * or not your architecture has unconditional branches that can span all of
|
+ * memory. (ZipCPU does ... via the LOD (PC),PC instruction.) It is used in
|
+ * memory. (ZipCPU does ... via the LW (PC),PC instruction.) It is used in
|
+ * conjunction with an optimization that partitions hot and cold basic blocks
|
+ * conjunction with an optimization that partitions hot and cold basic blocks
|
+ * into separate sections of the executable. If this macro is set to false,
|
+ * into separate sections of the executable. If this macro is set to false,
|
+ * gcc will convert any unconditional branches that attempt to cross between
|
+ * gcc will convert any unconditional branches that attempt to cross between
|
+ * sections into indirect jumps.
|
+ * sections into indirect jumps.
|
+ *
|
+ *
|
+ * ZipCPU has the LOD (PC),PC instruction which can be used to implement a long
|
+ * ZipCPU has the LW (PC),PC instruction which can be used to implement a long
|
+ * jump.
|
+ * jump.
|
+ */
|
+ */
|
+#define HAS_LONG_UNCOND_BRANCH true
|
+#define HAS_LONG_UNCOND_BRANCH true
|
+
|
+
|
+/* CASE_VECTOR_MODE ... An alias for a machine mode name. This is the machine
|
+/* CASE_VECTOR_MODE ... An alias for a machine mode name. This is the machine
|
+ * mode that eleemnts of a jump-table should have.
|
+ * mode that elements of a jump-table should have.
|
+ *
|
+ *
|
+ */
|
+ */
|
+#define CASE_VECTOR_MODE SImode
|
+#define CASE_VECTOR_MODE SImode
|
+
|
+
|
+/* CASE_VECTOR_SHORTEN_MODE(MIN,MAX,BODY) ... Optional: return the preferred
|
+/* CASE_VECTOR_SHORTEN_MODE(MIN,MAX,BODY) ... Optional: return the preferred
|
| Line 6445... |
Line 7426... |
+/* WORD_REGISTER_OPERATIONS ... Define this macro to 1 if operations between
|
+/* WORD_REGISTER_OPERATIONS ... Define this macro to 1 if operations between
|
+ * registers with integral mode smaller than a word are always performed on the
|
+ * registers with integral mode smaller than a word are always performed on the
|
+ * entire register. Most RISC machines have this property and most CISC
|
+ * entire register. Most RISC machines have this property and most CISC
|
+ * machines do not.
|
+ * machines do not.
|
+ *
|
+ *
|
+ * ZipCPU---We have the property, 'cause we're fairly risk.
|
+ * ZipCPU---We have the property, 'cause we're fairly risc.
|
+ */
|
+ */
|
+#undef WORD_REGISTER_OPERATIONS
|
+#undef WORD_REGISTER_OPERATIONS
|
+#define WORD_REGISTER_OPERATIONS 1
|
+#define WORD_REGISTER_OPERATIONS 1
|
+
|
+
|
+/* LOAD_EXTEND_OP(MEMODE) ... Define this macro to be a C expression indicating
|
+/* LOAD_EXTEND_OP(MEMODE) ... Define this macro to be a C expression indicating
|
| Line 6459... |
Line 7440... |
+ * for which the insn sign-extends, ZERO_EXTEND for which it zero-extends, and
|
+ * for which the insn sign-extends, ZERO_EXTEND for which it zero-extends, and
|
+ * UNKNOWN for other modes.
|
+ * UNKNOWN for other modes.
|
+ *
|
+ *
|
+ * Do not define this macro if it would always return UNKNOWN.
|
+ * Do not define this macro if it would always return UNKNOWN.
|
+ *
|
+ *
|
+ * ZipCPU---This should be irrelevant, so we leave it undefined.
|
+ * ZipCPU---Our memory unit zero extends registers, so we'll zero extend here.
|
+ */
|
+ */
|
+#undef LOAD_EXTEND_OP
|
+#undef LOAD_EXTEND_OP
|
+#define LOAD_EXTEND_OP(MEM) SIGN_EXTEND
|
+#define LOAD_EXTEND_OP(MEM) ZERO_EXTEND
|
+
|
+
|
+/* SHORT_IMMEDIATES_SIGN_EXTEND ... Define this macro to 1 if loading short immediate values into registers sign extends.
|
+/* SHORT_IMMEDIATES_SIGN_EXTEND ... Define this macro to 1 if loading short
|
|
+ * immediate values into registers sign extends.
|
+ *
|
+ *
|
+ * ZipCPU---All immediates are sign extended, so yes.
|
+ * ZipCPU---All immediates are sign extended, so yes.
|
+ */
|
+ */
|
+#undef SHORT_IMMEDIATES_SIGN_EXTEND
|
+#undef SHORT_IMMEDIATES_SIGN_EXTEND
|
+#define SHORT_IMMEDIATES_SIGN_EXTEND 1
|
+#define SHORT_IMMEDIATES_SIGN_EXTEND 1
|
| Line 6481... |
Line 7463... |
+ *
|
+ *
|
+ * ZipCPU --- Although we can move 32-bits at a time, and most people would call
|
+ * ZipCPU --- Although we can move 32-bits at a time, and most people would call
|
+ * this 4-bytes, the compiler defines a byte as the minimum addressable unit.
|
+ * this 4-bytes, the compiler defines a byte as the minimum addressable unit.
|
+ * Therefore, this is defined to be one.
|
+ * Therefore, this is defined to be one.
|
+ */
|
+ */
|
+#define MOVE_MAX 1
|
+#define MOVE_MAX UNITS_PER_WORD
|
+
|
+
|
+/* MAX_MOVE_MAX ... The maximum number of bytes that a single instruction can
|
+/* MAX_MOVE_MAX ... The maximum number of bytes that a single instruction can
|
+ * move quickly between memory and registers or between two memory ...
|
+ * move quickly between memory and registers or between two memory ...
|
+ *
|
+ *
|
+ * ZipCPU --- this sounds just the same as MOVE_MAX, which is the default
|
+ * ZipCPU --- this sounds just the same as MOVE_MAX, which is the default
|
| Line 6514... |
Line 7496... |
+/* TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) ... A C expression which is nonzero
|
+/* TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) ... A C expression which is nonzero
|
+ * if on this machine it is safe to "convert" an integer of INPREC bits to one
|
+ * if on this machine it is safe to "convert" an integer of INPREC bits to one
|
+ * of OUTPREC bits (where OUTPREC is smaller than INPREC) by merely operating on
|
+ * of OUTPREC bits (where OUTPREC is smaller than INPREC) by merely operating on
|
+ * it as if it had OUTPREC bist. On many machines, this expression can be 1.
|
+ * it as if it had OUTPREC bist. On many machines, this expression can be 1.
|
+ *
|
+ *
|
+ * ZiPCPU ... If both values are 32-bit, what conversion takes place? If one is
|
+ * ZiPCPU ...
|
+ * 64-bit and the other 32-bit ... I suppose it would then be safe.
|
|
+ */
|
+ */
|
+#undef TRULY_NOOP_TRUNCATION
|
+#undef TRULY_NOOP_TRUNCATION
|
+#define TRULY_NOOP_TRUNCATION(O,I) 1
|
+#define TRULY_NOOP_TRUNCATION(O,I) 1
|
+
|
+
|
+/* TARGET_MODE_REP_EXTENDED(MODE,REPMODE) ... The representation of an integral
|
+/* TARGET_MODE_REP_EXTENDED(MODE,REPMODE) ... The representation of an integral
|
+ * mode can be such that the values are always extended to a wider integral
|
+ * mode can be such that the values are always extended to a wider integral
|
+ * mode. Return SIGN_EXTEND if values of MODE are represented in sign-extended
|
+ * mode. Return SIGN_EXTEND if values of MODE are represented in sign-extended
|
+ * form to REPMODE. Return UNKNOWN otherwise. (Currently none of the targets
|
+ * form to REPMODE. Return UNKNOWN otherwise. (Currently none of the targets
|
+ * use zero-extended.
|
+ * use zero-extended this way so unlike LOAD_EXTEND_OP, TARGET_MODE_REP_EXTENDED
|
|
+ * is expected to return either SIGN_EXTEND or UNKNOWN. Also, no target extends
|
|
+ * MODE to REP_MODE so that REP_MODE is not the next widest integral mode and
|
|
+ * we currently take advantage of this fact.)
|
|
+ *
|
|
+ * Similarly to LOAD_EXTEND_OP you may return a non_UNKNOWN value even if the
|
|
+ * extension is not performed on certain hard registers as long as for the
|
|
+ * REGNO_REG_CLASS of tehsse hard registers CANNOT_CHANGE_MODE_CLASS returns
|
|
+ * zero.
|
|
+ *
|
|
+ * Not that TARGET_MODE_REP_EXTENDED and LOAD_EXTEND_OP describe two related
|
|
+ * properties. If you define TARGET_MODE_REP_EXTENDED(mode,wordmode) you
|
|
+ * probably also want to define LOAD_EXTEND_OP(mode) to return the same type
|
|
+ * of extension.
|
+ *
|
+ *
|
|
+ * In order to enforce the representation of mode, TRULY_NOOP_TRUNCATION should
|
|
+ * return false when truncating to MODE.
|
|
+ *
|
|
+ * ZipCPU ... ???
|
+ */
|
+ */
|
+// #undef TARGET_MODE_REP_EXTENDED
|
+// #undef TARGET_MODE_REP_EXTENDED
|
+// #define TARGET_MODE_REP_EXTENDED(R,M) SIGN_EXTEND
|
+// #define TARGET_MODE_REP_EXTENDED(R,M) UNKNOWN
|
+
|
+
|
+/* STORE_FLAG_VALUE ... A C expression describing the value returned by a
|
+/* STORE_FLAG_VALUE ... A C expression describing the value returned by a
|
+ * comparison operator with an integral mode and stored by a store-flag
|
+ * comparison operator with an integral mode and stored by a store-flag
|
+ * instruction (cstoremode4) when the condition is true. This description
|
+ * instruction (cstoremode4) when the condition is true. This description
|
+ * must apply to all the cstoremode4 patterns and all the comparison operators
|
+ * must apply to all the cstoremode4 patterns and all the comparison operators
|
| Line 6555... |
Line 7553... |
+/* CLZ_DEFINED_VALUE_AT_ZERO(MODE, VAL)
|
+/* CLZ_DEFINED_VALUE_AT_ZERO(MODE, VAL)
|
+ * CTZ_DEFINED_VALUE_AT_ZERO(MODE, VAL)
|
+ * CTZ_DEFINED_VALUE_AT_ZERO(MODE, VAL)
|
+ *
|
+ *
|
+ * A C expression that indicates whetther the architecture defines a value for
|
+ * A C expression that indicates whetther the architecture defines a value for
|
+ * clz or ctz with a zero operand. A result of 0 indicates the value is
|
+ * clz or ctz with a zero operand. A result of 0 indicates the value is
|
+ * undefined. If the value is defined for only the RTL expression, the macro should evaluate to 1. If the value also applies to the corresponding optab
|
+ * undefined. If the value is defined for only the RTL expression, the macro
|
|
+ * should evaluate to 1. If the value also applies to the corresponding optab
|
+ * entry, then the macro should evaluate to 2. In cases where the value is
|
+ * entry, then the macro should evaluate to 2. In cases where the value is
|
+ * defined, value should be set to this value.
|
+ * defined, value should be set to this value.
|
+ * If this macro is not defined, the value of clz or ctz at zero is assumed to
|
+ * If this macro is not defined, the value of clz or ctz at zero is assumed to
|
+ * be undefined.
|
+ * be undefined.
|
+ *
|
+ *
|
| Line 6569... |
Line 7568... |
+/* Pmode ... An alias for the machine mode for pointers. On most machines,
|
+/* Pmode ... An alias for the machine mode for pointers. On most machines,
|
+ * define this to be the integer mode corresponding to the width of a
|
+ * define this to be the integer mode corresponding to the width of a
|
+ * hardware pointer. SImode on 32-bits machines, or DImode on 64-bit machines.
|
+ * hardware pointer. SImode on 32-bits machines, or DImode on 64-bit machines.
|
+ * On some machines you must define this to be one of the partial
|
+ * On some machines you must define this to be one of the partial
|
+ * integer modes, such as PSImode.
|
+ * integer modes, such as PSImode.
|
|
+ *
|
|
+ * ZipCPU--the machine mode for pointers is one word (32-bits). The one word
|
|
+ * mode is the SImode, so that's what we use here.
|
+ */
|
+ */
|
+#undef Pmode
|
+#undef Pmode
|
+#define Pmode SImode
|
+#define Pmode SImode
|
+
|
+
|
+/* FUNCTION_MODE ... An alais for the machine mode used for memory references to
|
+/* FUNCTION_MODE ... An alias for the machine mode used for memory references to
|
+ * function being called, in call RTL expressions. On most CISC machines, where
|
+ * function being called, in call RTL expressions. On most CISC machines, where
|
+ * an instruction can begin at any byte address, this should be QImode. On most
|
+ * an instruction can begin at any byte address, this should be QImode. On most
|
+ * RISC machines, where all instructions have fixed size and alignment, this
|
+ * RISC machines, where all instructions have fixed size and alignment, this
|
+ * should be a mode with the same size and alignment as the machine instruction
|
+ * should be a mode with the same size and alignment as the machine instruction
|
+ * words--typically SImode or HImode.
|
+ * words--typically SImode or HImode.
|
| Line 7218... |
Line 8220... |
+// extern void zip_asm_output_def(FILE *s, const char *n, const char *v);
|
+// extern void zip_asm_output_def(FILE *s, const char *n, const char *v);
|
+// extern void zip_update_cc_notice(rtx exp, rtx_insn *insn);
|
+// extern void zip_update_cc_notice(rtx exp, rtx_insn *insn);
|
+// extern int zip_address_operand(rtx op);
|
+// extern int zip_address_operand(rtx op);
|
+// extern int zip_const_address_operand(rtx op);
|
+// extern int zip_const_address_operand(rtx op);
|
+// extern void zip_expand_prologue(void);
|
+// extern void zip_expand_prologue(void);
|
+// extern void zip_expand_epilogue(void);
|
+// extern void zip_expand_epilogue(void);
|
+// extern bool zip_gen_move_rtl(rtx, rtx);
|
+// extern bool zip_gen_move_rtl(rtx, rtx);
|
+// extern bool zip_load_address_lod(rtx, rtx);
|
+// extern bool zip_load_address_lod(rtx, rtx);
|
+// extern bool zip_load_address_sto(rtx, rtx);
|
+// extern bool zip_load_address_sto(rtx, rtx);
|
+// extern void zip_print_operand(FILE *fp, rtx x, int code);
|
+// extern void zip_print_operand(FILE *fp, rtx x, int code);
|
+// extern void zip_print_operand_address(FILE *fp, rtx x);
|
+// extern void zip_print_operand_address(FILE *fp, rtx x);
|
+// extern bool zip_use_return_insn(void);
|
+extern int zip_use_return_insn(void);
|
+
|
|
+#define UQQmode USQmode
|
|
+#define UHQmode USQmode
|
|
+#define UHAmode USAmode
|
|
+#define QQmode SQmode
|
|
+#define HQmode SQmode
|
|
+#define QImode SImode
|
|
+#define HImode SImode
|
|
+#define QAmode SAmode
|
|
+#define HAmode SAmode
|
|
+
|
|
+#include "insn-modes.h"
|
|
+// #include "zip-protos.h" // Cant include this here!
|
|
+
|
|
+#endif /* GCC_ZIP_H */
|
|
+
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.md gcc-5.3.0-zip/gcc/config/zip/zip.md
|
|
--- gcc-5.3.0-original/gcc/config/zip/zip.md 1969-12-31 19:00:00.000000000 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/zip/zip.md 2016-11-28 18:12:19.339493020 -0500
|
|
@@ -0,0 +1,3058 @@
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;;
|
|
+;; Filename: zip.md
|
|
+;;
|
|
+;; Project: Zip CPU -- a small, lightweight, RISC CPU soft core
|
|
+;;
|
|
+;; Purpose: This is the machine description of the Zip CPU as needed by the
|
|
+;; GNU compiler collection (GCC).
|
|
+;;
|
|
+;;
|
|
+;; Creator: Dan Gisselquist, Ph.D.
|
|
+;; Gisselquist Technology, LLC
|
|
+;;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;;
|
|
+;; Copyright (C) 2015, Gisselquist Technology, LLC
|
|
+;;
|
|
+;; This program is free software (firmware): you can redistribute it and/or
|
|
+;; modify it under the terms of the GNU General Public License as published
|
|
+;; by the Free Software Foundation, either version 3 of the License, or (at
|
|
+;; your option) any later version.
|
|
+;;
|
|
+;; This program is distributed in the hope that it will be useful, but WITHOUT
|
|
+;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
|
+;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
|
+;; for more details.
|
|
+;;
|
|
+;; License: GPL, v3, as defined and found on www.gnu.org,
|
|
+;; http://www.gnu.org/licenses/gpl.html
|
|
+;;
|
|
+;;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;;
|
|
+;;
|
|
+;; - Immediate integer operand constraints
|
|
+;; 'I' -2^22 ... 2^22-1, or -4194304 .. 4194303 (LDI insn)
|
|
+;; 'M' -2^12 ... 2^12-1, or -4096 ... 4095 (MOV offset)
|
|
+;; 'N' -2^14 ... 2^14-1, or -16384 ... 16383 (OpB offset)
|
|
+;; 'O' -2^17 ... 2^17-1, or -131072 ... 131071 (OpB Immediate)
|
|
+;; 'R' 0...31 (Shift value)
|
|
+;; - Memory constraints
|
|
+;; "Q" Op-B capable references to memory
|
|
+;; "S" References to constant memory
|
|
+;; - Address constraints
|
|
+;; "U" Op-B capable address that references to memory
|
|
+;; "T" Constant memory addresses
|
|
+(define_constraint "M"
|
|
+ "An 13-bit signed immediate such as a MOV instruction can handle"
|
|
+ (and (match_code "const_int")
|
|
+ (match_test "(ival < 0x1000) && (ival >= -0x1000)")))
|
|
+(define_constraint "N"
|
|
+ "An 14-bit signed immediate offset such as an Op-B register offset"
|
|
+ (and (match_code "const_int")
|
|
+ (match_test "(ival < 0x2000) && (ival >= -0x2000)")))
|
|
+(define_constraint "O"
|
|
+ "An 18-bit signed immediate such as an Op-B Immediate can handle"
|
|
+ (and (match_code "const_int")
|
|
+ (match_test "(ival < 0x20000) && (ival >= -0x20000)")))
|
|
+(define_constraint "R"
|
|
+ "Bits that a value may be shifted"
|
|
+ (and (match_code "const_int")
|
|
+ (match_test "(ival < 32) && (ival >= 0)")))
|
|
+;;
|
|
+;
|
|
+;
|
|
+; Our builtin functions, by identifier
|
|
+;
|
|
+(define_constants
|
|
+ [(UNSPEC_RTU 1)
|
|
+ (UNSPEC_HALT 2)
|
|
+ (UNSPEC_IDLE 3)
|
|
+ (UNSPEC_SYSCALL 4)
|
|
+ (UNSPEC_SAVE_CONTEXT 5)
|
|
+ (UNSPEC_RESTORE_CONTEXT 6)
|
|
+ (UNSPEC_BITREV 7)
|
|
+ (UNSPEC_GETUCC 8)
|
|
+ (UNSPEC_GETCC 9)
|
|
+ (UNSPEC_LDILO 10)
|
|
+ ; (UNSPEC_RAW_CALL 11)
|
|
+ ])
|
|
+;
|
|
+;
|
|
+; Registers by name
|
|
+(define_constants
|
|
+ [(RTN_REG 0) ; Return address register
|
|
+ (RTNV_REG 1) ; Subroutine return value register
|
|
+ (AP_REG 10) ; Hopefully never used
|
|
+ (GBL_REG 11) ; Hopefully never used, but just in case ...
|
|
+ (FP_REG 12)
|
|
+ (SP_REG 13)
|
|
+ (CC_REG 14)
|
|
+ (PC_REG 15)
|
|
+ ])
|
|
+;
|
|
+;
|
|
+;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;;
|
|
+;; Predicates
|
|
+;;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;
|
|
+;
|
|
+;
|
|
+(define_predicate "zip_const_address_operand_p"
|
|
+ (match_code "symbol_ref,const,label_ref,code_label")
|
|
+{
|
|
+ return zip_const_address_operand(op);
|
|
+})
|
|
+
|
|
+(define_predicate "zip_address_operand_p"
|
|
+ (match_code "reg,plus")
|
|
+{
|
|
+ return zip_pd_opb_operand(op);
|
|
+})
|
|
+
|
|
+(define_predicate "zip_opb_operand_p"
|
|
+ (match_code "reg,plus,const_int,subreg")
|
|
+{
|
|
+ return zip_pd_opb_operand(op);
|
|
+})
|
|
+
|
|
+(define_predicate "zip_opb_immv_p"
|
|
+ (match_code "const_int")
|
|
+{
|
|
+ return (INTVAL(op)<((1<<13)-1))&&(INTVAL(op)>=-((1<<13)));
|
|
+})
|
|
+
|
|
+(define_predicate "zip_opb_single_operand_p"
|
|
+ (match_code "reg,subreg,const_int")
|
|
+{
|
|
+ return zip_pd_opb_operand(op);
|
|
+})
|
|
+
|
|
+(define_predicate "zip_mov_operand_p"
|
|
+ (match_code "reg,plus")
|
|
+{
|
|
+ return zip_pd_mov_operand(op);
|
|
+})
|
|
+
|
|
+(define_predicate "zip_memory_operand_p"
|
|
+ (match_code "mem")
|
|
+{
|
|
+ return zip_pd_opb_operand(XEXP(op,0));
|
|
+})
|
|
+
|
|
+(define_predicate "zip_imm_operand_p"
|
|
+ (match_code "const_int")
|
|
+{
|
|
+ return zip_pd_imm_operand(op);
|
|
+})
|
|
+
|
|
+(define_predicate "zip_mvimm_operand_p"
|
|
+ (match_code "const_int")
|
|
+{
|
|
+ return zip_pd_mvimm_operand(op);
|
|
+})
|
|
+
|
+
|
+(define_predicate "zip_movdst_operand_p"
|
+#include "insn-modes.h"
|
+ (match_code "mem,reg,subreg")
|
+// #include "zip-protos.h" // Cant include this here!
|
+{
|
|
+ if (MEM_P(op)) // Check for valid store address
|
|
+ return zip_pd_opb_operand(XEXP(op,0));
|
|
+ else if (SUBREG_P(op))
|
|
+ return 1;
|
|
+ else if ((REG_P(op))||(SUBREG_P(op)))
|
|
+ return register_operand(op, GET_MODE(op));
|
|
+ return 1;
|
|
+})
|
|
+
|
+
|
+(define_predicate "zip_movsrc_operand_p"
|
+#endif /* GCC_ZIP_H */
|
+ (match_code "mem,reg,subreg,const_int,const,symbol_ref,label_ref,code_label")
|
|
+{
|
|
+ if (MEM_P(op))
|
|
+ return zip_pd_opb_operand(XEXP(op,0));
|
|
+ else if (GET_CODE(op)==PLUS)
|
|
+ return zip_pd_opb_operand(op);
|
|
+ else if (SUBREG_P(op)) {
|
|
+ //; As far as predicates are concerned, subregs must be valid.
|
|
+ //; The details of them are settled within the constraints.
|
|
+ return 1;
|
|
+ } else if ((REG_P(op))||(SUBREG_P(op)))
|
|
+ return register_operand(op,SImode);
|
|
+ else if (CONST_INT_P(op))
|
|
+ return 1;
|
|
+ return 1;
|
|
+})
|
|
+
|
+
|
+;
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip.md gcc-6.2.0-zip/gcc/config/zip/zip.md
|
+;
|
--- gcc-6.2.0/gcc/config/zip/zip.md 1969-12-31 19:00:00.000000000 -0500
|
+;
|
+++ gcc-6.2.0-zip/gcc/config/zip/zip.md 2017-03-07 12:02:29.862582673 -0500
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
@@ -0,0 +1,1968 @@
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;
|
+;;
|
+;; Constraints
|
+;; Filename: zip.md
|
+;;
|
+;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;; Project: Zip CPU -- a small, lightweight, RISC CPU soft core
|
+;
|
|
+;
|
|
+;
|
|
+(define_memory_constraint "S"
|
|
+ "Any memory referenced by a constant address, possibly unknown at compile time"
|
|
+ (and (match_code "mem")
|
|
+ (match_test "zip_ct_const_address_operand(XEXP(op,0))")))
|
|
+(define_memory_constraint "Q"
|
|
+ "Any memory addressed suitably for a load or store instruction"
|
|
+ (and (match_code "mem")
|
|
+ (match_test "zip_ct_address_operand(XEXP(op,0))")))
|
|
+(define_address_constraint "U"
|
|
+ "An address suitable for a load or store instruction"
|
|
+ (and (match_code "reg,plus")
|
|
+ (match_test "zip_ct_address_operand(op)")))
|
|
+(define_address_constraint "T"
|
|
+ "Any constant address, to include those made by symbols unknown at compile time"
|
|
+ (and (match_code "label_ref,code_label,symbol_ref,const")
|
|
+ (match_test "zip_ct_const_address_operand(op)")))
|
|
+;
|
|
+;
|
|
+;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;;
|
+;;
|
+;; Attributes
|
+;; Purpose: This is the machine description of the Zip CPU as needed by the
|
|
+;; GNU compiler collection (GCC).
|
+;;
|
+;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;
|
|
+;
|
|
+;
|
|
+;
|
|
+;
|
|
+(define_attr "predicable" "no,yes" (const_string "yes"))
|
|
+(define_attr "conditional" "no,yes" (const_string "no"))
|
|
+(define_attr "ccresult" "set,unknown,unchanged,validzn" (const_string "set"))
|
|
+;
|
|
+; Mode attributes
|
|
+; (define_mode_iterator ZI [QI HI SI])
|
|
+; (define_mode_attr zipa [(QI "") (HI "") (SI "")])
|
|
+(define_mode_iterator ZI [SI])
|
|
+(define_mode_attr zipa [(SI "")])
|
|
+;
|
|
+;
|
|
+;
|
|
+;
|
|
+;
|
|
+;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;;
|
+;;
|
+;; Instructions
|
+;; Creator: Dan Gisselquist, Ph.D.
|
|
+;; Gisselquist Technology, LLC
|
+;;
|
+;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;
|
|
+;
|
|
+;
|
|
+;; Instructions
|
|
+;
|
|
+; (define_insn
|
|
+; optional name
|
|
+; RTL template -- a vector of incomplete RTL expressions describing the
|
|
+; semantics of the instruction. It is incomplete because it may
|
|
+; contain match_operand, match_operator, and match_dup expressions
|
|
+; The condition --- contains a C expression, may be an empty string
|
|
+; output template or output statement--fragment of C code returning a str
|
|
+; Attributes --
|
|
+; )
|
|
+;
|
|
+; (match_operand:m n predicate constraint)
|
|
+; Placeholder for operand #n of the instruction
|
|
+; Predicate string that is the name of a fucntion w/ 2 arguments:
|
|
+; (expression, machine mode)
|
|
+; we can build functions:
|
|
+; "isregister" to describe a register
|
|
+; "isimmediate" to describe an immediate
|
|
+; "offsetreg" to describe a register plus offset
|
|
+; "anyregister" to describe *ANY* register (uRx or Rx)
|
|
+; But ... functions "address_operand", "immediate_operand",
|
|
+; "register_operand", "indirect_operand"
|
|
+; "comparison_operatot" and "ordered_comparison_operator"
|
|
+; are also available--be aware, they include more comparisons
|
|
+; than Zip CPU can do.
|
|
+;
|
|
+;
|
|
+;
|
|
+;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;;
|
+;;
|
+;; Move instructions: both
|
+;; Copyright (C) 2015-2017, Gisselquist Technology, LLC
|
+;; (arbitrary) from variables to variables, but this gets
|
|
+;; expanded into:
|
|
+;; from registers to registers
|
|
+;; from immediates to registers
|
|
+;;
|
+;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;; This program is free software (firmware): you can redistribute it and/or
|
+;
|
+;; modify it under the terms of the GNU General Public License as published
|
+;
|
+;; by the Free Software Foundation, either version 3 of the License, or (at
|
+;
|
+;; your option) any later version.
|
+(define_expand "mov<mode>"
|
|
+ [(set (match_operand:ZI 0 "nonimmediate_operand" "")
|
|
+ (match_operand:ZI 1 "general_operand" ""))]
|
|
+ ""
|
|
+ {//; Everything except mem=const or mem=mem can be done easily
|
|
+ //; extern void zip_debug_rtx_pfx(const char *, const_rtx);
|
|
+ //; fprintf(stderr, "ZIP-GEN-MOVE\n");
|
|
+ //; zip_debug_rtx_pfx("FROM: ", operands[1]);
|
|
+ //; zip_debug_rtx_pfx("TO : ", operands[0]);
|
|
+
|
|
+ //; Need to load into a register between memory slots
|
|
+ if ((MEM_P(operands[0]))&&(MEM_P(operands[1]))) {
|
|
+ //; fprintf(stderr, "GEN-MOVSI: MEM -> MEM\n");
|
|
+ if (can_create_pseudo_p()) {
|
|
+ rtx tmp = gen_reg_rtx(GET_MODE(operands[1]));
|
|
+ emit_insn(gen_movsi(tmp,operands[1]));
|
|
+ operands[1] = tmp;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ //; Op[0] has a bad address, need to legitimize it
|
|
+ if ((MEM_P(operands[0]))&&
|
|
+ ((zip_const_address_operand(XEXP(operands[0],0)))
|
|
+ ||(!zip_pd_opb_operand(XEXP(operands[0],0))))
|
|
+ )
|
|
+ {
|
|
+ //; fprintf(stderr, "GEN-MOVSI: Not to a MEM(REG)\n");
|
|
+ if (can_create_pseudo_p()) {
|
|
+ rtx tmp = gen_reg_rtx(Pmode);
|
|
+ //; Load the address into a register
|
|
+ emit_insn(gen_movsi(tmp,XEXP(operands[0],0)));
|
|
+ XEXP(operands[0],0) = tmp;
|
|
+ mark_reg_pointer(tmp,1);
|
|
+ }
|
|
+ }
|
|
+ //; Op[1] is a constant. Need to load into a register before we can
|
|
+ //; place it into memory.
|
|
+ if ((MEM_P(operands[0]))&&
|
|
+ ((CONSTANT_P(operands[1]))
|
|
+ ||(CONST_INT_P(operands[1])))) {
|
|
+ //; fprintf(stderr, "GEN-MOVSI: CONST -> MEM\n");
|
|
+ //; zip_debug_rtx_pfx("MEM : ", operands[0]);
|
|
+ //; zip_debug_rtx_pfx("CONST: ", operands[1]);
|
|
+ if (can_create_pseudo_p()) {
|
|
+ rtx tmp = gen_reg_rtx(GET_MODE(operands[0]));
|
|
+ emit_insn(gen_movsi(tmp,operands[1]));
|
|
+ operands[1] = tmp;
|
|
+ }
|
|
+ }
|
|
+ //; Op[1] has a bad address, need to legitimize it
|
|
+ if ((MEM_P(operands[1]))&&
|
|
+ //; (!REG_P(XEXP(operands[1],0)))
|
|
+ ((zip_const_address_operand(XEXP(operands[1],0)))
|
|
+ ||(!zip_pd_opb_operand(XEXP(operands[1],0))))) {
|
|
+ //; fprintf(stderr, "GEN-MOVSI: Not from a MEM(REG)\n");
|
|
+ if (can_create_pseudo_p()) {
|
|
+ rtx tmp = gen_reg_rtx(Pmode);
|
|
+ emit_insn(gen_movsi(tmp,XEXP(operands[1],0)));
|
|
+ XEXP(operands[1],0) = tmp;
|
|
+ } else if (REG_P(operands[0])) { //; Can we steal Op[0]'s reg?
|
|
+ rtx tmp = operands[0];
|
|
+ emit_insn(gen_movsi(tmp,XEXP(operands[1],0)));
|
|
+ XEXP(operands[1],0) = tmp;
|
|
+ }
|
|
+ }
|
|
+ }
|
|
+ [(set_attr "ccresult" "unchanged")])
|
|
+(define_insn "movsi_raw"
|
|
+ [(set (match_operand:SI 0 "zip_movdst_operand_p" "=r,Q,r,r")
|
|
+ (match_operand:SI 1 "zip_movsrc_operand_p" "r,r,Q,i"))]
|
|
+ "(register_operand(operands[0],SImode))||(register_operand(operands[1],SImode))"
|
|
+ "@
|
|
+ MOV\t%1,%0
|
|
+ STO\t%1,%0
|
|
+ LOD\t%1,%0
|
|
+ LDI\t%1,%0"
|
|
+ [(set_attr "ccresult" "unchanged")])
|
|
+(define_insn "mov<mode>_reg" ; Register to register move
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (match_operand:ZI 1 "register_operand" "r"))]
|
|
+ ""
|
|
+ "MOV %1,%0"
|
|
+ [(set_attr "ccresult" "unchanged")])
|
|
+(define_insn "mov<mode>_reg_off" ; Register to register move, used by prologue
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (plus:ZI (match_operand:ZI 1 "register_operand" "r")
|
|
+ (match_operand:ZI 2 "zip_mvimm_operand_p" "M")))
|
|
+ ]
|
|
+ ""
|
|
+ "MOV %2(%1),%0"
|
|
+ [(set_attr "ccresult" "unchanged")])
|
|
+;(define_insn "mov<mode>_lod" ; Load from memory
|
|
+; [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+; (match_operand:ZI 1 "zip_memory_operand_p" "Q"))]
|
|
+; ""
|
|
+; "LOD %1,%0"
|
|
+; [(set_attr "ccresult" "unchanged")])
|
|
+;(define_insn "mov<mode>_sto" ; Store into memory
|
|
+; [(set (match_operand:ZI 0 "zip_memory_operand_p" "=Q")
|
|
+; (match_operand:ZI 1 "register_operand" "r"))]
|
|
+; ""
|
|
+; "STO %1,%0"
|
|
+; [(set_attr "ccresult" "unchanged")])
|
|
+(define_expand "mov<mode>_lod" ; Load from memory
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (match_operand:ZI 1 "zip_memory_operand_p" "Q"))]
|
|
+ "")
|
|
+(define_insn "*movsi_lod"
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (match_operand:SI 1 "zip_memory_operand_p" ""))]
|
|
+ ""
|
|
+ "LOD\t%1,%0"
|
|
+ [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
|
|
+(define_insn "movsi_lod_off" ; used by epilogue code
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
|
|
+ (match_operand:SI 2 "const_int_operand" "N"))))]
|
|
+ ""
|
|
+ "LOD\t%2(%1),%0"
|
|
+ [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
|
|
+(define_expand "mov<mode>_sto" ; Store into memory
|
|
+ [(set (match_operand:ZI 0 "zip_memory_operand_p" "=Q")
|
|
+ (match_operand:ZI 1 "register_operand" "r"))]
|
|
+ "")
|
|
+(define_insn "*movsi_sto"
|
|
+ [(set (match_operand:SI 0 "zip_memory_operand_p" "=Q")
|
|
+ (match_operand:SI 1 "register_operand" "r"))]
|
|
+ ""
|
|
+ "STO\t%1,%0"
|
|
+ [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
|
|
+(define_insn "movsi_sto_off" ; used by prologue code
|
|
+ [(set (mem:SI (plus:SI
|
|
+ (match_operand:SI 0 "register_operand" "r")
|
|
+ (match_operand:SI 1 "const_int_operand" "N")))
|
|
+ (match_operand:SI 2 "register_operand" "r"))]
|
|
+ ""
|
|
+ "STO\t%2,%1(%0)"
|
|
+ [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
|
|
+(define_insn "mov<mode>_ldi" ; Load immediate
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (match_operand:ZI 1 "immediate_operand" "ipU"))]
|
|
+ ""
|
|
+ "LDI %1,%0"
|
|
+ [(set_attr "ccresult" "unchanged")])
|
|
+;
|
|
+;
|
|
+;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;;
|
+;;
|
+;; Load and store multiple values
|
+;; This program is distributed in the hope that it will be useful, but WITHOUT
|
|
+;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
|
+;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
|
+;; for more details.
|
+;;
|
+;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;; License: GPL, v3, as defined and found on www.gnu.org,
|
+;
|
+;; http://www.gnu.org/licenses/gpl.html
|
+; So far, from the code I've seen from GCC's output,
|
|
+; these instructions do not appear to be necessary.
|
|
+;
|
|
+;(define_insn "load_multiple"
|
|
+; for(a=0; a<%2; a++)
|
|
+; LOD a(%1),%0+a
|
|
+;(define_insn "store_multiple"
|
|
+; for(a=0; a<%2; a++)
|
|
+; STO %0+a,a(%1)
|
|
+; pushsi -- Do not define, compiler will work around it nicely w/o our help
|
|
+;
|
|
+;
|
|
+;
|
|
+;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;;
|
+;;
|
+;; Substitution Pattern
|
|
+;;
|
+;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;
|
|
+;
|
|
+(define_subst "cc_substitution"
|
|
+ ; The pattern may not have any match_dup expressions.
|
|
+ [(set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ [(set (match_dup 0) (match_dup 1))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))
|
|
+ ])
|
|
+;
|
|
+(define_subst_attr "cc_subst" "cc_substitution" "_raw" "_clobber")
|
|
+;
|
|
+;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;;
|
+;;
|
+;; General arithmetic instructions
|
|
+;;
|
+;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;; - Immediate integer operand constraints
|
+;
|
+;; 'I' -2^22 ... 2^22-1, or -4194304 .. 4194303 (LDI insn)
|
|
+;; 'x' -2^17 ... 2^17-1, (DI const)
|
|
+;; 'K' 0...2^17-2 (ucmp offset)
|
|
+;; 'M' -2^12 ... 2^12-1, or -4096 ... 4095 (MOV offset)
|
|
+;; 'N' -2^14 ... 2^14-1, or -16384 ... 16383 (OpB offset)
|
|
+;; 'O' -2^17 ... 2^17-1, or -131072 ... 131071 (OpB Immediate)
|
|
+;; 'R' 0...31 (Shift value)
|
|
+;; - Memory constraints
|
|
+;; "Q" Op-B capable references to memory
|
|
+;; "S" References to constant memory
|
|
+;; - Address constraints
|
|
+;; "U" Op-B capable address that references to memory
|
|
+;; "T" Constant memory addresses
|
|
+(define_constraint "x"
|
|
+ "An 17-bit signed immediate such as a CMP:DI instruction can handle"
|
|
+ (and (match_code "const_wide_int")
|
|
+ (match_test "(ival < 0x20000l) && (ival >= -0x20000l)")))
|
|
+(define_constraint "K"
|
|
+ "An 17-bit signed immediate such as a CMP:DI instruction can handle"
|
|
+ (and (match_code "const_int")
|
|
+ (match_test "(ival < 0x20000) && (ival >= -0x20000)")))
|
|
+(define_constraint "M"
|
|
+ "An 13-bit signed immediate such as a MOV instruction can handle"
|
|
+ (and (match_code "const_int")
|
|
+ (match_test "(ival < 0x1000) && (ival >= -0x1000)")))
|
|
+(define_constraint "N"
|
|
+ "An 14-bit signed immediate offset such as an Op-B register offset"
|
|
+ (and (match_code "const_int")
|
|
+ (match_test "(ival < 0x2000) && (ival >= -0x2000)")))
|
|
+(define_constraint "O"
|
|
+ "An 18-bit signed immediate such as an Op-B Immediate can handle"
|
|
+ (and (match_code "const_int")
|
|
+ (match_test "(ival < 0x20000) && (ival >= -0x20000)")))
|
|
+(define_constraint "R"
|
|
+ "Bits that a value may be shifted"
|
|
+ (and (match_code "const_int")
|
|
+ (match_test "(ival < 32) && (ival >= 0)")))
|
|
+;;
|
+;
|
+;
|
+;
|
+;
|
|
+; Our builtin functions, by identifier
|
+;
|
+;
|
+(define_expand "add<mode>3" ; Fastest/best instruction always goes first
|
+(define_constants
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ [(UNSPEC_RTU 1)
|
+ (plus:ZI (match_operand:ZI 1 "register_operand" "0")
|
+ (UNSPEC_HALT 2)
|
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))
|
+ (UNSPEC_IDLE 3)
|
|
+ (UNSPEC_SYSCALL 4)
|
|
+ (UNSPEC_SAVE_CONTEXT 5)
|
|
+ (UNSPEC_RESTORE_CONTEXT 6)
|
|
+ (UNSPEC_BITREV 7)
|
|
+ (UNSPEC_GETUCC 8)
|
|
+ (UNSPEC_GETCC 9)
|
|
+ (UNSPEC_LDILO 10)
|
|
+ ; (UNSPEC_RAW_CALL 11)
|
+ ])
|
+ ])
|
+(define_insn_and_split "add<mode>3_split_reg"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (plus:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))]
|
|
+ ""
|
|
+ "#" ; This code means the instruction *must* be split
|
|
+ "(reload_completed)&&(REG_P(operands[0]))&&(REG_P(operands[1]))&&(REGNO(operands[0])==REGNO(operands[1]))"
|
|
+ [(parallel [(set (match_dup 0) (plus:ZI (match_dup 1) (match_dup 2)))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "predicable" "yes")])
|
|
+(define_insn_and_split "add<mode>3_split_off"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (plus:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))]
|
|
+ ""
|
|
+ "#" ; This code means the instruction *must* be split
|
|
+ "(reload_completed)&&(REG_P(operands[0]))&&(REG_P(operands[1]))&&(REGNO(operands[0])==REGNO(operands[1]))"
|
|
+ [(parallel [(set (match_dup 0) (plus:ZI (match_dup 1)
|
|
+ (plus:ZI (match_dup 2) (match_dup 3))))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "predicable" "yes")])
|
|
+(define_insn "addsi3_reg_clobber"
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (plus:SI (match_operand:SI 1 "register_operand" "0")
|
|
+ (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ "ADD %2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "addsi3_reg_raw"
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (plus:SI (match_operand:SI 1 "register_operand" "0")
|
|
+ (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ ""
|
|
+ "ADD %2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "add<mode>3_off_raw"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (plus:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ ""
|
|
+ "ADD %3+%2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "add<mode>3_off_clobber"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (plus:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ "ADD %3+%2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+;
|
|
+;
|
|
+;
|
|
+(define_expand "sub<mode>3"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))])
|
|
+(define_insn_and_split "sub<mode>3_split_reg"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))]
|
|
+ ""
|
|
+ "#"
|
|
+ "(reload_completed)"
|
|
+ [(parallel [(set (match_dup 0) (minus:ZI (match_dup 1) (match_dup 2)))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "ccresult" "set") (set_attr "predicable" "yes")])
|
|
+(define_insn "sub<mode>3_reg_raw"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ ""
|
|
+ "SUB %2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "sub<mode>3_reg_clobber"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ "SUB %2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn_and_split "sub<mode>3_off_split"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "%r")
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))]
|
|
+ ""
|
|
+ "#"
|
|
+ "(reload_completed)"
|
|
+ [(parallel [(set (match_dup 0) (minus:ZI (match_dup 1)
|
|
+ (plus:ZI (match_dup 2) (match_dup 3))))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "sub<mode>3_off_raw"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "%r")
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ ""
|
|
+ "SUB %3+%2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "sub<mode>3_off_clobber"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "%r")
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ "SUB %3+%2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+;
|
|
+;
|
|
+(define_expand "mul<mode>3"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (mult:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))]
|
|
+ "(ZIP_LONGMPY)")
|
|
+(define_insn_and_split "mul<mode>3_split_reg"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (mult:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))]
|
|
+ "(ZIP_LONGMPY)"
|
|
+ "#"
|
|
+ "(reload_completed)"
|
|
+ [(parallel [(set (match_dup 0) (mult:ZI (match_dup 1) (match_dup 2)))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn_and_split "mul<mode>3_split_off"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (mult:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))]
|
|
+ "(ZIP_LONGMPY)"
|
|
+ "#"
|
|
+ "(reload_completed)"
|
|
+ [(parallel [(set (match_dup 0) (mult:ZI (match_dup 1)
|
|
+ (plus:ZI (match_dup 2) (match_dup 3))))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "mul<mode>3_reg_clobber"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (mult:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ "(ZIP_LONGMPY)"
|
|
+ "MPY\t%2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "mul<mode>3_reg_raw"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (mult:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ "(ZIP_LONGMPY)"
|
|
+ "MPY\t%2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "mul<mode>3_off_raw"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (mult:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ "(ZIP_LONGMPY)"
|
|
+ "MPY\t%3+%2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "mul<mode>3_off_clobber"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (mult:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ "(ZIP_LONGMPY)"
|
|
+ "MPY\t%3+%2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+;
|
|
+;
|
|
+(define_expand "smulsi3_highpart"
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (truncate:SI (ashiftrt:DI (mult:DI
|
|
+ (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
|
|
+ (sign_extend:DI (match_operand:SI 2 "zip_opb_operand_p" "")))
|
|
+ (const_int 32))))]
|
|
+ "((ZIP_LONGMPY)&&(ZIP_HAS_DI))")
|
|
+(define_insn_and_split "smulsi3_highpart_split_reg"
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (truncate:SI (ashiftrt:DI (mult:DI
|
|
+ (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
|
|
+ (sign_extend:DI (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
|
|
+ (const_int 32))))]
|
|
+ "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
|
|
+ "#"
|
|
+ "(reload_completed)"
|
|
+ [(parallel [(set (match_dup 0)
|
|
+ (truncate:SI (ashiftrt:DI
|
|
+ (mult:DI
|
|
+ (sign_extend:DI (match_dup 1))
|
|
+ (sign_extend:DI (match_dup 2)))
|
|
+ (const_int 32))))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn_and_split "smulsi3_highpart_split_off"
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (truncate:SI (ashift:DI (mult:DI
|
|
+ (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
|
|
+ (sign_extend:DI
|
|
+ (plus:SI (match_operand:SI 2 "register_operand" "r")
|
|
+ (match_operand:SI 3 "zip_opb_immv_p" "N"))))
|
|
+ (const_int 32))))]
|
|
+ "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
|
|
+ "#"
|
|
+ "(reload_completed)"
|
|
+ [(parallel [(set (match_dup 0)
|
|
+ (truncate:SI (ashiftrt:DI
|
|
+ (mult:SI
|
|
+ (sign_extend:DI (match_dup 1))
|
|
+ (sign_extend:DI
|
|
+ (plus:SI (match_dup 2) (match_dup 3))))
|
|
+ (const_int 32))))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "smulsi3_highpart_reg_clobber"
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (truncate:SI (ashiftrt:DI
|
|
+ (mult:SI
|
|
+ (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
|
|
+ (sign_extend:DI (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
|
|
+ (const_int 32))))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
|
|
+ "MPYSHI\t%2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "smulsi3_highpart_reg_raw"
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (truncate:SI (ashiftrt:DI
|
|
+ (mult:SI
|
|
+ (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
|
|
+ (sign_extend:DI (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
|
|
+ (const_int 32))))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
|
|
+ "MPYSHI\t%2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "smulsi3_highpart_off_raw"
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (truncate:SI (ashiftrt:DI
|
|
+ (mult:SI
|
|
+ (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
|
|
+ (sign_extend:DI (plus:SI
|
|
+ (match_operand:SI 2 "register_operand" "r")
|
|
+ (match_operand:SI 3 "zip_opb_immv_p" "N"))))
|
|
+ (const_int 32))))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
|
|
+ "MPYSHI\t%3+%2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "smulsi3_highpart_off_clobber"
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (truncate:SI (ashiftrt:DI
|
|
+ (mult:SI
|
|
+ (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
|
|
+ (sign_extend:DI (plus:SI
|
|
+ (match_operand:SI 2 "register_operand" "r")
|
|
+ (match_operand:SI 3 "zip_opb_immv_p" "N"))))
|
|
+ (const_int 32))))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
|
|
+ "MPYSHI\t%3+%2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+;
|
|
+;
|
|
+(define_expand "umulsi3_highpart"
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (truncate:SI (ashiftrt:DI (mult:DI
|
|
+ (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
|
|
+ (zero_extend:DI (match_operand:SI 2 "zip_opb_operand_p" "")))
|
|
+ (const_int 32))))]
|
|
+ "((ZIP_LONGMPY)&&(ZIP_HAS_DI))")
|
|
+(define_insn_and_split "umulsi3_highpart_split_reg"
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (truncate:SI (ashiftrt:DI (mult:DI
|
|
+ (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
|
|
+ (zero_extend:DI (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
|
|
+ (const_int 32))))]
|
|
+ "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
|
|
+ "#"
|
|
+ "(reload_completed)"
|
|
+ [(parallel [(set (match_dup 0)
|
|
+ (truncate:SI (ashiftrt:DI
|
|
+ (mult:SI
|
|
+ (zero_extend:DI (match_dup 1))
|
|
+ (zero_extend:DI (match_dup 2)))
|
|
+ (const_int 32))))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn_and_split "umulsi3_highpart_split_off"
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (truncate:SI (ashiftrt:DI
|
|
+ (mult:DI
|
|
+ (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
|
|
+ (zero_extend:DI
|
|
+ (plus:SI (match_operand:SI 2 "register_operand" "r")
|
|
+ (match_operand:SI 3 "zip_opb_immv_p" "N"))))
|
|
+ (const_int 32))))]
|
|
+ "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
|
|
+ "#"
|
|
+ "(reload_completed)"
|
|
+ [(parallel [(set (match_dup 0)
|
|
+ (truncate:SI (ashiftrt:DI
|
|
+ (mult:DI
|
|
+ (zero_extend:DI (match_dup 1))
|
|
+ (zero_extend:DI
|
|
+ (plus:SI (match_dup 2) (match_dup 3))))
|
|
+ (const_int 32))))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "umulsi3_highpart_reg_clobber"
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (truncate:SI (ashiftrt:DI
|
|
+ (mult:DI
|
|
+ (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
|
|
+ (zero_extend:DI (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
|
|
+ (const_int 32))))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
|
|
+ "MPYSHI\t%2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "umulsi3_highpart_reg_raw"
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (truncate:SI (ashiftrt:DI
|
|
+ (mult:DI
|
|
+ (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
|
|
+ (zero_extend:DI (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
|
|
+ (const_int 32))))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
|
|
+ "MPYSHI\t%2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "umulsi3_highpart_off_raw"
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (truncate:SI (ashiftrt:DI
|
|
+ (mult:DI
|
|
+ (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
|
|
+ (zero_extend:DI (plus:SI
|
|
+ (match_operand:SI 2 "register_operand" "r")
|
|
+ (match_operand:DI 3 "zip_opb_immv_p" "N"))))
|
|
+ (const_int 32))))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
|
|
+ "MPYSHI\t%3+%2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "umulsi3_highpart_off_clobber"
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (truncate:SI (ashiftrt:DI
|
|
+ (mult:DI
|
|
+ (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
|
|
+ (zero_extend:DI (plus:SI
|
|
+ (match_operand:SI 2 "register_operand" "r")
|
|
+ (match_operand:DI 3 "zip_opb_immv_p" "N"))))
|
|
+ (const_int 32))))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
|
|
+ "MPYSHI\t%3+%2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+;
|
|
+;
|
+;
|
+(define_expand "div<mode>3"
|
|
+ [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (div:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])]
|
|
+ "(ZIP_DIVIDE)")
|
|
+(define_insn "div<mode>3_reg"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (div:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ "(ZIP_DIVIDE)"
|
|
+ "DIVS %2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "div<mode>3_off"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (div:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ "(ZIP_DIVIDE)"
|
|
+ "DIVS %3+%2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_expand "udiv<mode>3"
|
|
+ [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (udiv:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])]
|
|
+ "(ZIP_DIVIDE)")
|
|
+(define_insn "udiv<mode>3_reg"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (udiv:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ "(ZIP_DIVIDE)"
|
|
+ "DIVU %2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "udiv<mode>3_off"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (udiv:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ "(ZIP_DIVIDE)"
|
|
+ "DIVU %3+%2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+;;
|
|
+;; modsi3
|
|
+;; umodsi3
|
|
+;;
|
|
+(define_insn "umin<mode>3"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (umin:ZI (match_operand:ZI 1 "register_operand" "%0")
|
|
+ (match_operand:ZI 2 "register_operand" "r")))
|
|
+ (clobber (reg:CC CC_REG))
|
|
+ ]
|
|
+ ""
|
|
+ "CMP %0,%2
|
|
+ MOV.C %2,%0"
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
|
+(define_insn "umax<mode>3"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (umax:ZI (match_operand:ZI 1 "register_operand" "%0")
|
|
+ (match_operand:ZI 2 "register_operand" "r")))
|
|
+ (clobber (reg:CC CC_REG))
|
|
+ ]
|
|
+ ""
|
|
+ "CMP %2,%0
|
|
+ MOV.C %2,%0"
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
|
+(define_insn "smin<mode>3"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (smin:ZI (match_operand:ZI 1 "register_operand" "%0")
|
|
+ (match_operand:ZI 2 "register_operand" "r")))
|
|
+ (clobber (reg:CC CC_REG))
|
|
+ ]
|
|
+ ""
|
|
+ "CMP %2,%0
|
|
+ MOV.GT %2,%0"
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
|
+(define_insn "smax<mode>3"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (smax:ZI (match_operand:ZI 1 "register_operand" "%0")
|
|
+ (match_operand:ZI 2 "register_operand" "r")))
|
|
+ (clobber (reg:CC CC_REG))
|
|
+ ]
|
|
+ ""
|
|
+ "CMP %0,%2
|
|
+ MOV.LT %2,%0"
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
|
+;
|
+;
|
|
+; Registers by name
|
|
+(define_constants
|
|
+ [(RTN_REG 0) ; Return address register
|
|
+ (RTNV_REG 1) ; Subroutine return value register
|
|
+ (AP_REG 10) ; Hopefully never used
|
|
+ (GBL_REG 11) ; Hopefully never used, but just in case ...
|
|
+ (FP_REG 12)
|
|
+ (SP_REG 13)
|
|
+ (CC_REG 14)
|
|
+ (PC_REG 15)
|
|
+ ])
|
+;
|
+;
|
+; AND
|
|
+;
|
+;
|
+;
|
+;
|
+(define_expand "and<mode>3"
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+;;
|
+ (and:ZI (match_operand:ZI 1 "register_operand" "%0")
|
+;; Mode iterator
|
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))])
|
+;;
|
+(define_insn_and_split "and<mode>3_reg_split"
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (and:ZI (match_operand:ZI 1 "register_operand" "%0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))]
|
|
+ ""
|
|
+ "#"
|
|
+ "(reload_completed)"
|
|
+ [(parallel [(set (match_dup 0) (and:ZI (match_dup 1) (match_dup 2)))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "and<mode>3_reg_raw"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (and:ZI (match_operand:ZI 1 "register_operand" "%0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ ""
|
|
+ "AND %2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "and<mode>3_reg_clobber"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (and:ZI (match_operand:ZI 1 "register_operand" "%0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ "AND %2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn_and_split "and<mode>3_off_split"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (and:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))]
|
|
+ ""
|
|
+ "#"
|
|
+ "(reload_completed)"
|
|
+ [(parallel [(set (match_dup 0) (and:ZI (match_dup 1)
|
|
+ (plus:ZI (match_dup 2) (match_dup 3))))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "and<mode>3_off_raw"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (and:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ ""
|
|
+ "AND %3+%2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "and<mode>3_off_clobber"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (and:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ "AND %3+%2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+;
|
+;
|
+;
|
+;
|
|
+(define_mode_iterator ZI [QI HI SI])
|
|
+(define_mode_attr sz [(QI "B") (HI "H") (SI "W")])
|
+;
|
+;
|
+;
|
+;
|
+; iOR
|
|
+;
|
+;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;;
|
|
+;; Predicates
|
|
+;;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;
|
+;
|
+(define_expand "ior<mode>3"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
|
|
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))])
|
|
+(define_insn_and_split "ior<mode>3_reg_split"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))]
|
|
+ ""
|
|
+ "#"
|
|
+ "(reload_completed)"
|
|
+ [(parallel [(set (match_dup 0) (ior:ZI (match_dup 1) (match_dup 2)))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "ior<mode>3_reg_raw"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ ""
|
|
+ "OR %2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "ior<mode>3_reg_clobber"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ "OR %2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn_and_split "ior<mode>3_off_split"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (ior:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))]
|
|
+ ""
|
|
+ "#"
|
|
+ "(reload_completed)"
|
|
+ [(parallel [(set (match_dup 0) (ior:ZI (match_dup 1)
|
|
+ (plus:ZI (match_dup 2) (match_dup 3))))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "ior<mode>3_off_raw"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (ior:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ ""
|
|
+ "OR %3+%2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "ior<mode>3_off_clobber"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (ior:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ "OR %3+%2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+;
|
+;
|
+;
|
+;
|
|
+(define_predicate "zip_const_address_operand_p"
|
|
+ (match_code "symbol_ref,const,label_ref,code_label")
|
|
+{
|
|
+ return zip_const_address_operand(op);
|
|
+})
|
|
+
|
|
+(define_predicate "zip_address_operand_p"
|
|
+ (match_code "reg,plus")
|
|
+{
|
|
+ return zip_pd_opb_operand(op);
|
|
+})
|
|
+
|
|
+(define_predicate "zip_opb_operand_p"
|
|
+ (match_code "reg,plus,const_int,subreg")
|
|
+{
|
|
+ return zip_pd_opb_operand(op);
|
|
+})
|
|
+
|
|
+(define_predicate "zip_opb_immv_p"
|
|
+ (match_code "const_int")
|
|
+{
|
|
+ return (INTVAL(op)<((1<<13)-1))&&(INTVAL(op)>=-((1<<13)));
|
|
+})
|
|
+
|
|
+(define_predicate "zip_opb_single_operand_p"
|
|
+ (match_code "reg,subreg,const_int")
|
|
+{
|
|
+ return zip_pd_opb_operand(op);
|
|
+})
|
|
+
|
|
+(define_predicate "zip_mov_operand_p"
|
|
+ (match_code "reg,plus")
|
|
+{
|
|
+ return zip_pd_mov_operand(op);
|
|
+})
|
|
+
|
|
+(define_predicate "zip_memory_operand_p"
|
|
+ (match_code "mem")
|
|
+{
|
|
+ return zip_pd_opb_operand(XEXP(op,0));
|
|
+})
|
|
+
|
|
+(define_predicate "zip_imm_operand_p"
|
|
+ (match_code "const_int")
|
|
+{
|
|
+ return zip_pd_imm_operand(op);
|
|
+})
|
|
+
|
|
+(define_predicate "zip_mvimm_operand_p"
|
|
+ (match_code "const_int")
|
|
+{
|
|
+ return zip_pd_mvimm_operand(op);
|
|
+})
|
|
+
|
+;
|
+;
|
|
+; zip_movdst_operand_p and zip_movsrc_operand_p are no longer necessary, and
|
|
+; are being deprecated.
|
+;
|
+;
|
+; XOR
|
+;(define_predicate "zip_movdst_operand_p"
|
|
+; (match_code "mem,reg,subreg")
|
|
+;{
|
|
+; if (MEM_P(op)) // Check for valid store address
|
|
+; return zip_pd_opb_operand(XEXP(op,0));
|
|
+; else if ((SUBREG_P(op))&&(REG_P(XEXP(op,0))))
|
|
+; return 1;
|
|
+; else if (REG_P(op))
|
|
+; return register_operand(op, GET_MODE(op));
|
|
+; return 1;
|
|
+;})
|
|
+
|
|
+;(define_predicate "zip_movsrc_operand_p"
|
|
+; (match_code "mem,reg,subreg,const_int,const,symbol_ref,label_ref,code_label")
|
|
+;{
|
|
+; if (MEM_P(op))
|
|
+; return zip_pd_opb_operand(XEXP(op,0));
|
|
+; else if (GET_CODE(op)==PLUS)
|
|
+; return zip_pd_opb_operand(op);
|
|
+; else if ((SUBREG_P(op))&&(REG_P(XEXP(op,0)))) {
|
|
+; //; As far as predicates are concerned, subregs must be valid.
|
|
+; //; The details of them are settled within the constraints.
|
|
+; return 1;
|
|
+; } else if ((REG_P(op))||(SUBREG_P(op)))
|
|
+; return register_operand(op,SImode);
|
|
+; else if (CONST_INT_P(op))
|
|
+; return 1;
|
|
+; return 1;
|
|
+;})
|
|
+
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+(define_expand "xor<mode>3"
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+ [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
|
|
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])]
|
|
+ "")
|
|
+(define_insn_and_split "xor<mode>3_reg_split"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))]
|
|
+ ""
|
|
+ "#"
|
|
+ "(reload_completed)"
|
|
+ [(parallel [(set (match_dup 0) (xor:ZI (match_dup 1) (match_dup 2)))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "xor<mode>3_reg_raw"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ ""
|
|
+ "XOR %2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "xor<mode>3_reg_clobber"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ "XOR %2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn_and_split "xor<mode>3_off_split"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (xor:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))]
|
|
+ ""
|
|
+ "#"
|
|
+ "(reload_completed)"
|
|
+ [(parallel [(set (match_dup 0) (xor:ZI (match_dup 1)
|
|
+ (plus:ZI (match_dup 2) (match_dup 3))))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "xor<mode>3_off_raw"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (xor:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ ""
|
|
+ "XOR %3+%2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "xor<mode>3_off_clobber"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (xor:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ "XOR %3+%2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+;(define_insn "addv<mode>4"
|
|
+ ;[(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ ;(plus:ZI (match_operand:ZI 1 "register_operand" "%r")
|
|
+ ;(match_operand:ZI 2 "general_operand" "rO")))
|
|
+ ;(set (pc) (if_then_else (eq (reg:CC CC_REG) (const_int 0))
|
|
+ ;(label_ref (match_operand 3))
|
|
+ ;(pc)))]
|
|
+ ;""
|
|
+ ;"MOV %1,%0
|
|
+ ;ADD %2,%0
|
|
+ ;BV %3"
|
|
+ ;[(set_attr "predicable" "no") (set_attr "ccresult" "set")])
|
|
+;;(define_insn "subvsi4"
|
|
+;; MOV %1,%0
|
|
+;; SUB %2,%0
|
|
+;; BV %3
|
|
+;;(mulvsi4)
|
|
+;;(define_insn "uaddvsi4"
|
|
+;; ADD %2,%0
|
|
+;; BC %3
|
|
+;;(define_insn "usubvsi4"
|
|
+;; MOV %1,%0
|
|
+;; SUB %2,%0
|
|
+;; BC %3
|
|
+;;
|
+;;
|
+;; (define_insn "umulvsi4"
|
+;; Constraints
|
+;; ... ???)
|
|
+;;
|
+;;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;
|
+;
|
+;
|
+;
|
+; ASR
|
|
+;
|
+;
|
|
+(define_memory_constraint "S"
|
|
+ "Any memory referenced by a constant address, possibly unknown at compile time"
|
|
+ (and (match_code "mem")
|
|
+ (match_test "zip_ct_const_address_operand(XEXP(op,0))")))
|
|
+(define_memory_constraint "Q"
|
|
+ "Any memory addressed suitably for a load or store instruction"
|
|
+ (and (match_code "mem")
|
|
+ (match_test "zip_ct_address_operand(XEXP(op,0))")))
|
|
+(define_address_constraint "U"
|
|
+ "An address suitable for a load or store instruction"
|
|
+ (and (match_code "reg,plus")
|
|
+ (match_test "zip_ct_address_operand(op)")))
|
|
+(define_address_constraint "T"
|
|
+ "Any constant address, to include those made by symbols unknown at compile time"
|
|
+ (and (match_code "label_ref,code_label,symbol_ref,const")
|
|
+ (match_test "zip_ct_const_address_operand(op)")))
|
+;
|
+;
|
+(define_expand "ashr<mode>3"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (ashiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))])
|
|
+(define_insn_and_split "ashr<mode>3_split"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (ashiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))]
|
|
+ ""
|
|
+ "#"
|
|
+ "(reload_completed)"
|
|
+ [(parallel [(set (match_dup 0) (ashiftrt:ZI (match_dup 1) (match_dup 2)))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "ashr<mode>3_raw"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (ashiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ ""
|
|
+ "ASR %2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "ashr<mode>3_clobber"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (ashiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ "ASR %2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+;
|
+;
|
+;
|
+;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;;
|
|
+;; Attributes
|
|
+;;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;
|
+;
|
+; LSL
|
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+(define_expand "ashl<mode>3"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (ashift:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))])
|
|
+(define_insn_and_split "ashl<mode>3_split"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (ashift:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))]
|
|
+ ""
|
|
+ "#"
|
|
+ "(reload_completed)"
|
|
+ [(parallel [(set (match_dup 0) (ashift:ZI (match_dup 1) (match_dup 2)))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "ashl<mode>3_raw"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (ashift:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ ""
|
|
+ "LSL %2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "ashl<mode>3_clobber"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (ashift:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ "LSL %2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+;
|
+;
|
|
+(define_attr "predicable" "no,yes" (const_string "yes"))
|
|
+(define_attr "ccresult" "set,unknown,unchanged,validzn" (const_string "set"))
|
+;
|
+;
|
+;
|
+;
|
+; LSR
|
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+(define_expand "lshr<mode>3"
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+;;
|
+ (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
|
+;; Instructions
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))])
|
+;;
|
+(define_insn_and_split "lshr<mode>3_split"
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))]
|
|
+ ""
|
|
+ "#"
|
|
+ "(reload_completed)"
|
|
+ [(parallel [(set (match_dup 0) (lshiftrt:ZI (match_dup 1) (match_dup 2)))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "lshr<mode>3_raw"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ ""
|
|
+ "LSR %2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "lshr<mode>3_clobber"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ "LSR %2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+;
|
+;
|
+;
|
+;
|
+(define_expand "rotl<mode>3"
|
+;
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+;; Instructions
|
+ (rotate:ZI (match_operand:ZI 1 "register_operand" "0")
|
+;
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))])
|
+; (define_insn
|
+(define_insn_and_split "rotl<mode>3_split"
|
+; optional name
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+; RTL template -- a vector of incomplete RTL expressions describing the
|
+ (rotate:ZI (match_operand:ZI 1 "register_operand" "0")
|
+; semantics of the instruction. It is incomplete because it may
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))]
|
+; contain match_operand, match_operator, and match_dup expressions
|
+ ""
|
+; The condition --- contains a C expression, may be an empty string
|
+ "#"
|
+; output template or output statement--fragment of C code returning a str
|
+ "(reload_completed)"
|
+; Attributes --
|
+ [(parallel [(set (match_dup 0) (rotate:ZI (match_dup 1) (match_dup 2)))
|
+; )
|
+ (clobber (reg:CC CC_REG))])]
|
+;
|
+ ""
|
+; (match_operand:m n predicate constraint)
|
+ [(set_attr "ccresult" "set")])
|
+; Placeholder for operand #n of the instruction
|
+(define_insn "rotl<mode>3_raw"
|
+; Predicate string that is the name of a fucntion w/ 2 arguments:
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+; (expression, machine mode)
|
+ (rotate:ZI (match_operand:ZI 1 "register_operand" "0")
|
+; we can build functions:
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
|
+; "isregister" to describe a register
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
+; "isimmediate" to describe an immediate
|
+ ""
|
+; "offsetreg" to describe a register plus offset
|
+ "ROL %2,%0"
|
+; "anyregister" to describe *ANY* register (uRx or Rx)
|
+ [(set_attr "ccresult" "set")])
|
+; But ... functions "address_operand", "immediate_operand",
|
+(define_insn "rotl<mode>3_clobber"
|
+; "register_operand", "indirect_operand"
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+; "comparison_operatot" and "ordered_comparison_operator"
|
+ (rotate:ZI (match_operand:ZI 1 "register_operand" "0")
|
+; are also available--be aware, they include more comparisons
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
|
+; than Zip CPU can do.
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ "ROL %2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;;
|
|
+;; Move instructions: both
|
|
+;; (arbitrary) from variables to variables, but this gets
|
|
+;; expanded into:
|
|
+;; from registers to registers
|
|
+;; from immediates to registers
|
|
+;;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;
|
+;
|
+; Others: NEG, TEST, POPC, NOT
|
|
+;
|
+;
|
+;
|
+;
|
+(define_insn "neg<mode>2"
|
+(define_expand "mov<mode>"
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ [(set (match_operand:ZI 0 "nonimmediate_operand" "")
|
+ (neg:ZI (match_operand:ZI 1 "register_operand" "r")))
|
+ (match_operand:ZI 1 "general_operand" ""))]
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
+ ""
|
+ "NEG %1,%0"
|
+ {//; Everything except mem=const or mem=mem can be done easily
|
+ [(set_attr "ccresult" "validzn")])
|
+ //; extern void zip_debug_rtx_pfx(const char *, const_rtx);
|
+(define_insn "abs<mode>2"
|
+ //; fprintf(stderr, "ZIP-GEN-MOVE\n");
|
|
+ //; zip_debug_rtx_pfx("FROM: ", operands[1]);
|
|
+ //; zip_debug_rtx_pfx("TO : ", operands[0]);
|
|
+
|
|
+ //; Need to load into a register between memory slots
|
|
+ if ((MEM_P(operands[0]))&&(MEM_P(operands[1]))) {
|
|
+ //; fprintf(stderr, "GEN-MOVSI: MEM -> MEM\n");
|
|
+ if (can_create_pseudo_p()) {
|
|
+ rtx tmp = gen_reg_rtx(GET_MODE(operands[1]));
|
|
+ if (GET_MODE(operands[1])==QImode)
|
|
+ emit_insn(gen_movqi(tmp,operands[1]));
|
|
+ else if (GET_MODE(operands[1])==HImode)
|
|
+ emit_insn(gen_movhi(tmp,operands[1]));
|
|
+ else
|
|
+ emit_insn(gen_movsi(tmp,operands[1]));
|
|
+ operands[1] = tmp;
|
|
+ }
|
|
+ }}
|
|
+ [(set_attr "ccresult" "unchanged")])
|
|
+(define_insn "mov<mode>_raw"
|
|
+ [(set (match_operand:ZI 0 "nonimmediate_operand" "=r,Q,r,r")
|
|
+ (match_operand:ZI 1 "general_operand" "r,r,Q,i"))]
|
|
+ ""
|
|
+ "@
|
|
+ MOV\t%1,%0
|
|
+ S<sz>\t%1,%0
|
|
+ L<sz>\t%1,%0
|
|
+ LDI\t%1,%0"
|
|
+ [(set_attr "ccresult" "unchanged")])
|
|
+(define_insn "movsi_reg_off" ; Register to register move, used by prologue
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (plus:SI (match_operand:SI 1 "register_operand" "r")
|
|
+ (match_operand:SI 2 "zip_mvimm_operand_p" "M")))
|
|
+ ]
|
|
+ ""
|
|
+ "MOV %2(%1),%0"
|
|
+ [(set_attr "ccresult" "unchanged")])
|
|
+(define_insn "mov<mode>_lod" ; Load from memory
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ (abs:ZI (match_operand:ZI 1 "register_operand" "0")))
|
+ (match_operand:ZI 1 "zip_memory_operand_p" "Q"))]
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
+ ""
|
+ "TEST %0
|
+ "L<sz>\t%1,%0"
|
+ NEG.LT %0"
|
+ [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+(define_insn "mov<mode>_lod_off" ; used by epilogue code
|
+(define_insn "popcount<mode>2"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ (popcount:ZI (match_operand:ZI 1 "register_operand" "r")))
|
+ (mem:ZI (plus:SI (match_operand:SI 1 "register_operand" "r")
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
+ (match_operand:SI 2 "zip_opb_immv_p" "N"))))]
|
+ ""
|
+ ""
|
+ "POPC %1,%0"
|
+ "L<sz>\t%2(%1),%0"
|
+ [(set_attr "ccresult" "set")])
|
+ [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
|
+(define_expand "parity<mode>2"
|
+(define_insn "mov<mode>_sto" ; Store into memory
|
+ [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ [(set (match_operand:ZI 0 "zip_memory_operand_p" "=Q")
|
+ (popcount:ZI (match_operand:ZI 1 "register_operand" "r")))
|
+ (match_operand:ZI 1 "register_operand" "r"))]
|
+ (clobber (reg:CC CC_REG))])
|
+ ""
|
+ (parallel [
|
+ "S<sz>\t%1,%0"
|
+ (set (match_dup 0) (and:ZI (match_dup 0) (const_int -2)))
|
+ [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
+(define_insn "mov<mode>_sto_off" ; used by prologue code
|
+ ])
|
+ [(set (mem:ZI (plus:SI
|
+(define_insn "one_cmpl<mode>2"
|
+ (match_operand:SI 0 "register_operand" "r")
|
|
+ (match_operand:SI 1 "zip_opb_immv_p" "N")))
|
|
+ (match_operand:ZI 2 "register_operand" "r"))]
|
|
+ ""
|
|
+ "S<sz>\t%2,%1(%0)"
|
|
+ [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
|
|
+(define_insn "mov<mode>_ldi" ; Load immediate
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ (not:ZI (match_operand:ZI 1 "register_operand" "0")))
|
+ (match_operand:ZI 1 "immediate_operand" "ipU"))]
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ ""
|
+ ""
|
+ "XOR -1,%0"
|
+ "LDI %1,%0"
|
+ [(set_attr "ccresult" "set")])
|
+ [(set_attr "ccresult" "unchanged")])
|
+;
|
|
+;
|
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;
|
+;;
|
+;; General arithmetic instructions -- double words
|
+;; Load and store multiple values
|
+;;
|
+;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;
|
+;
|
|
+; So far, from the code I've seen from GCC's output,
|
|
+; these instructions do not appear to be necessary.
|
+;
|
+;
|
|
+;(define_insn "load_multiple"
|
|
+; for(a=0; a<%2; a++)
|
|
+; LW a(%1),%0+a
|
|
+;(define_insn "store_multiple"
|
|
+; for(a=0; a<%2; a++)
|
|
+; SW %0+a,a(%1)
|
|
+; pushsi -- Do not define, compiler will work around it nicely w/o our help
|
+;
|
+;
|
+(define_expand "movdi3"
|
|
+ [(set (match_operand:DI 0 "nonimmediate_operand" "")
|
|
+ (match_operand:DI 1 "general_operand" ""))]
|
|
+ "(ZIP_HAS_DI)")
|
|
+(define_insn "movdi_lod"
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
|
+ (mem:DI (match_operand:SI 1 "zip_opb_operand_p" "")))]
|
|
+ "(ZIP_HAS_DI)"
|
|
+ {
|
|
+ if (REG_P(operands[1]))
|
|
+ return "LOD\t(%1),%H0\n\tLOD\t1(%1),%L0";
|
|
+ else if (GET_CODE(operands[1])==PLUS) {
|
|
+ if ((REG_P(XEXP(operands[1],0)))
|
|
+ &&(CONST_INT_P(XEXP(operands[1],1)))) {
|
|
+ static char buf[64];
|
|
+ sprintf(buf,
|
|
+ "LOD\t%ld(%%1),%%H0\n\tLOD\t%ld(%%1),%%L0",
|
|
+ (long)INTVAL(XEXP(operands[1],1)),
|
|
+ (long)INTVAL(XEXP(operands[1],1)+1));
|
|
+ return buf;
|
|
+ }
|
|
+ } return "BREAK";
|
|
+ }
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
|
+(define_insn "movdi_sto"
|
|
+ [(set (mem:DI (match_operand:SI 0 "zip_opb_operand_p" ""))
|
|
+ (match_operand:DI 1 "register_operand" "r"))]
|
|
+ "(ZIP_HAS_DI)"
|
|
+ {
|
|
+ if (REG_P(operands[0]))
|
|
+ return "STO\t%H0,(%1)\n\tSTO\t%L0,1(%1)";
|
|
+ else if (GET_CODE(operands[0])==PLUS) {
|
|
+ if ((REG_P(XEXP(operands[0],0)))
|
|
+ &&(CONST_INT_P(XEXP(operands[0],1)))) {
|
|
+ static char buf[64];
|
|
+ sprintf(buf,
|
|
+ "STO\t%%H0,%ld(%%1)\n\tSTO\t%%L0,%ld(%%1)",
|
|
+ (long)INTVAL(XEXP(operands[0],1)),
|
|
+ (long)INTVAL(XEXP(operands[0],1)+1));
|
|
+ return buf;
|
|
+ }
|
|
+ } return "BREAK";
|
|
+ }
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
|
+(define_insn "movdi_ldi"
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
|
+ (match_operand:DI 1 "immediate_operand" "i"))]
|
|
+ "(ZIP_HAS_DI)"
|
|
+ "LDI\t%H1,%H0\n\tLDI\t%L1,%L0"
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
|
+;
|
+;
|
+;
|
+;
|
+; ADD
|
|
+;
|
+;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;;
|
|
+;; Substitution Pattern
|
|
+;;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;
|
+;
|
+(define_insn "adddi3" ; Fastest/best instruction always goes first
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
|
+ (plus:DI (match_operand:DI 1 "register_operand" "0")
|
|
+ (match_operand:DI 2 "register_operand" "r")))
|
|
+ (clobber (reg:CC CC_REG))
|
|
+ ]
|
|
+ "(ZIP_HAS_DI)"
|
|
+ "ADD %L2,%L0\n\tADD.C\t1,%H0\n\tADD\t%H2,%H0"
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
|
+;
|
+;
|
|
+(define_subst "cc_substitution"
|
|
+ ; The pattern may not have any match_dup expressions.
|
|
+ [(set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ [(set (match_dup 0) (match_dup 1))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))
|
|
+ ])
|
+;
|
+;
|
|
+(define_subst_attr "cc_subst" "cc_substitution" "_raw" "_clobber")
|
+;
|
+;
|
+; SUB
|
|
+;
|
+;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;;
|
|
+;; Mode conversions
|
|
+;;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;
|
+;
|
+(define_insn "subdi3"
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
|
+ (minus:DI (match_operand:DI 1 "register_operand" "0")
|
|
+ (match_operand:DI 2 "register_operand" "r")))
|
|
+ (clobber (reg:CC CC_REG))
|
|
+ ]
|
|
+ "(ZIP_HAS_DI)"
|
|
+ "SUB %L2,%L0\n\tSUB.C\t1,%H0\n\tSUB\t%H2,%H0"
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
|
+;
|
+;
|
|
+(define_insn "zero_extendqisi2"
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (zero_extend:SI
|
|
+ (match_operand:QI 1 "register_operand" "0")))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ "AND\t255,%0 ; zero_extendqisi2 ... reg"
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
|
|
+
|
|
+(define_insn "zero_extendqisi2_raw"
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (zero_extend:SI
|
|
+ (match_operand:QI 1 "register_operand" "0")))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ ""
|
|
+ "AND\t255,%0 ; zero_extendqisi2 ... raw/set CC"
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
|
|
+
|
|
+(define_insn "zero_extendqisi2_mem"
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (zero_extend:SI
|
|
+ (match_operand:QI 1 "memory_operand" "Q")))]
|
|
+ ""
|
|
+ "LB\t%1,%0\t; Zero-Extend:QI"
|
|
+ [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
|
+;
|
+;
|
+;
|
+;
|
+; AND
|
|
+;
|
+;
|
+;
|
+;
|
+(define_insn "anddi3"
|
+(define_insn "zero_extendhisi2"
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
+ (and:DI (match_operand:DI 1 "register_operand" "%0")
|
+ (zero_extend:SI
|
+ (match_operand:DI 2 "register_operand" "r")))
|
+ (match_operand:HI 1 "register_operand" "0")))
|
+ (clobber (reg:CC CC_REG))
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ "AND\t65535,%0 ; zero_extendhisi2 ... reg"
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
|
|
+(define_insn "zero_extendhisi2_raw"
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (zero_extend:SI
|
|
+ (match_operand:HI 1 "register_operand" "0")))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ ""
|
|
+ "AND\t65535,%0 ; zero_extendhisi2 ... reg"
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
|
|
+(define_insn "zero_extendhisi2_mem"
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (zero_extend:SI
|
|
+ (match_operand:HI 1 "memory_operand" "Q")))
|
+ ]
|
+ ]
|
+ "(ZIP_HAS_DI)"
|
+ ""
|
+ "AND %L2,%L0\n\tAND\t%H2,%H0"
|
+ "LH\t%1,%0\t; Zero-Extend:HI"
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+ [(set_attr "predicable" "yes") (set_attr "ccresult" "set")])
|
+;
|
|
+;
|
+;
|
+;
|
+;
|
+; iOR
|
|
+;
|
+;
|
+;
|
+;
|
+(define_insn "iordi3"
|
+(define_insn "extendqisi2"
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
+ (ior:DI (match_operand:DI 1 "register_operand" "%0")
|
+ (sign_extend:SI
|
+ (match_operand:DI 2 "register_operand" "r")))
|
+ (match_operand:QI 1 "register_operand" "0")))
|
+ (clobber (reg:CC CC_REG))
|
+ (clobber (reg:CC CC_REG))]
|
+ ]
|
+ ""
|
+ "(ZIP_HAS_DI)"
|
+ "SEXTB\t%0\t; SEXTB"
|
+ "OR %L2,%L0\n\tOR\t%H2,%H0"
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
|
+(define_insn "extendhisi2"
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (sign_extend:SI
|
|
+ (match_operand:HI 1 "register_operand" "0")))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ "SEXTH\t%0\t; SEXTH"
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+;
|
+;
|
+;
|
+;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;;
|
|
+;; General arithmetic instructions
|
|
+;;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;
|
+;
|
+; XOR
|
|
+;
|
+;
|
+;
|
+;
|
+(define_insn "xordi3"
|
+;;
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
+;; modsi3
|
+ (xor:DI (match_operand:DI 1 "register_operand" "%0")
|
+;; umodsi3
|
+ (match_operand:DI 2 "register_operand" "r")))
|
+;;
|
|
+(define_insn "uminsi3"
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (umin:SI (match_operand:SI 1 "register_operand" "%0")
|
|
+ (match_operand:SI 2 "register_operand" "r")))
|
+ (clobber (reg:CC CC_REG))
|
+ (clobber (reg:CC CC_REG))
|
+ ]
|
+ ]
|
+ "(ZIP_HAS_DI)"
|
+ ""
|
+ "XOR %L2,%L0\n\tXOR\t%H2,%H0"
|
+ "CMP %0,%2
|
|
+ MOV.C %2,%0"
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+;
|
+(define_insn "umaxsi3"
|
+;
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
+;
|
+ (umax:SI (match_operand:SI 1 "register_operand" "%0")
|
+; NEG
|
+ (match_operand:SI 2 "register_operand" "r")))
|
+;
|
|
+;
|
|
+(define_insn "negdi2"
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
|
+ (neg:DI (match_operand:DI 1 "register_operand" "0")))
|
|
+ (clobber (reg:CC CC_REG))
|
+ (clobber (reg:CC CC_REG))
|
+ ]
|
+ ]
|
+ "(ZIP_HAS_DI)"
|
+ ""
|
+ "XOR -1,%L0\n\tXOR\t-1,%H0\n\tADD\t1,%L0\n\tADD.C\t1,%H0"
|
+ "CMP %2,%0
|
|
+ MOV.C %2,%0"
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+;
|
+(define_insn "sminsi3"
|
+;
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
+;
|
+ (smin:SI (match_operand:SI 1 "register_operand" "%0")
|
+; ABS
|
+ (match_operand:SI 2 "register_operand" "r")))
|
+;
|
|
+;
|
|
+(define_insn "absdi2"
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
|
+ (abs:DI (match_operand:DI 1 "register_operand" "0")))
|
|
+ (clobber (match_scratch:SI 2 "=r"))
|
|
+ (clobber (reg:CC CC_REG))
|
+ (clobber (reg:CC CC_REG))
|
+ ]
|
+ ]
|
+ "(ZIP_HAS_DI)"
|
+ ""
|
+ "CLR %2
|
+ "CMP %2,%0
|
+ TEST %H0 ; Problem, we can't tell conditions
|
+ MOV.GE %2,%0"
|
+ LDILO.LT 1,%2
|
|
+ XOR.LT -1,%L0
|
|
+ XOR.LT -1,%H0
|
|
+ ADD %2,%L0
|
|
+ ADD.C 1,%H0"
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+;
|
+(define_insn "smaxsi3"
|
+;
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
+; NOT
|
+ (smax:SI (match_operand:SI 1 "register_operand" "%0")
|
+;
|
+ (match_operand:SI 2 "register_operand" "r")))
|
+;
|
|
+(define_insn "one_cmpldi2"
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
|
+ (not:DI (match_operand:DI 1 "register_operand" "0")))
|
|
+ (clobber (reg:CC CC_REG))
|
+ (clobber (reg:CC CC_REG))
|
+ ]
|
+ ]
|
+ "(ZIP_HAS_DI)"
|
+ ""
|
+ "XOR -1,%L0\n\tXOR\t-1,%H0"
|
+ "CMP %2,%0
|
|
+ MOV.LT %2,%0"
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+;
|
+;
|
+;
|
+;
|
+; Unsigned min/max
|
+; AND
|
|
+; iOR
|
|
+; XOR
|
+;
|
+;
|
+;
|
+;
|
+(define_insn "umindi3"
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
|
+ (umin:DI (match_operand:DI 1 "register_operand" "%0")
|
|
+ (match_operand:DI 2 "register_operand" "r")))
|
|
+ (clobber (reg:CC CC_REG))
|
|
+ ]
|
|
+ "(ZIP_HAS_DI)"
|
|
+ "CMP %H0,%H2
|
|
+ CMP.Z %L0,%L2
|
|
+ MOV.C %H2,%H0
|
|
+ MOV.C %L2,%L0"
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
|
+(define_insn "umaxdi3"
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
|
+ (umax:DI (match_operand:DI 1 "register_operand" "%0")
|
|
+ (match_operand:DI 2 "register_operand" "r")))
|
|
+ (clobber (reg:CC CC_REG))
|
|
+ ]
|
|
+ "(ZIP_HAS_DI)"
|
|
+ "CMP %H2,%H0
|
|
+ CMP.Z %L2,%L0
|
|
+ MOV.C %H2,%H0
|
|
+ MOV.C %L2,%L0"
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
|
+;
|
+;
|
|
+;(define_insn "addvsi4"
|
|
+ ;[(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ ;(plus:SI (match_operand:SI 1 "register_operand" "%r")
|
|
+ ;(match_operand:SI 2 "general_operand" "rO")))
|
|
+ ;(set (pc) (if_then_else (eq (reg:CC CC_REG) (const_int 0))
|
|
+ ;(label_ref (match_operand 3))
|
|
+ ;(pc)))]
|
|
+ ;""
|
|
+ ;"MOV %1,%0
|
|
+ ;ADD %2,%0
|
|
+ ;BV %3"
|
|
+ ;[(set_attr "predicable" "no") (set_attr "ccresult" "set")])
|
|
+;;(define_insn "subvsi4"
|
|
+;; MOV %1,%0
|
|
+;; SUB %2,%0
|
|
+;; BV %3
|
|
+;;(mulvsi4)
|
|
+;;(define_insn "uaddvsi4"
|
|
+;; ADD %2,%0
|
|
+;; BC %3
|
|
+;;(define_insn "usubvsi4"
|
|
+;; MOV %1,%0
|
|
+;; SUB %2,%0
|
|
+;; BC %3
|
|
+;;
|
|
+;; (define_insn "umulvsi4"
|
|
+;; ... ???)
|
|
+;;
|
+;
|
+;
|
+; POP
|
+;
|
|
+; ASR
|
|
+; LSL
|
|
+; LSR
|
+;
|
+;
|
+;
|
+;
|
+(define_insn "popcountdi2"
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (popcount:SI (match_operand:DI 1 "register_operand" "r")))
|
|
+ (clobber (match_scratch:SI 2 "=r"))
|
|
+ (clobber (reg:CC CC_REG))
|
|
+ ]
|
|
+ "(ZIP_HAS_DI)"
|
|
+ "POPC %L1,%0
|
|
+ POPC %H1,%2
|
|
+ ADD %2,%0"
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
|
|
+;
|
+;
|
+;
|
+;
|
+; PARITY
|
+;
|
|
+; Others: NEG, TEST, POPC, NOT
|
+;
|
+;
|
+;
|
+;
|
+(define_expand "paritydi2"
|
+(define_insn "negsi2"
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
+ (popcount (match_operand:DI 1 "register_operand" "r")))
|
+ (neg:SI (match_operand:SI 1 "register_operand" "r")))
|
+ (set (match_dup 0) (and:SI (match_dup 0) (const_int -2)))
|
+ (clobber (reg:CC CC_REG))]
|
+ ])
|
+ ""
|
+;(define_insn "extendsidi2"
|
+ "NEG %1,%0" ;//; = MOV -1(%1),%0, XOR -1,%0
|
+; [(set (match_operand:DI 0 "register_operand" "=r")
|
+ [(set_attr "ccresult" "validzn")])
|
+; (sign_extend:DI (match_operand:SI 0 "register_operand" "r")))]
|
+(define_insn "abssi2"
|
+; "(ZIP_HAS_DI)"
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
+; "TEST\t%1\nMOV\t%1,%L0\nCLR\t%L1\nLDI.LT\t-1,%L1"
|
+ (abs:SI (match_operand:SI 1 "register_operand" "0")))
|
+; [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+ (clobber (reg:CC CC_REG))]
|
+;(define_insn "mulsidi3"
|
+ ""
|
+; [(set (match_operand:DI 0 "register_operand" "=r")
|
+ "TEST\t%0\n\tNEG.LT\t%0"
|
+; (mult:SI (match_operand:SI 1 "register_operand" "%r")
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+; (match_operand:SI 2 "register_operand" "r")))
|
+(define_insn_and_split "one_cmplsi2"
|
+; (clobber (match_scratch:SI 3 "=r"))]
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
+; ; "(R0 != R1)&&(R0 != R2)&&(R0!=R3)&&(R1!=R2)&&(R1=R3)&&(R2!=R3)"
|
+ (not:SI (match_operand:SI 1 "register_operand" "0")))
|
+; "(ZIP_HAS_DI)"
|
+ (clobber (reg:CC CC_REG))]
|
+; "MOV %1,%L0
|
+ ""
|
+; MPYS %2,%L0 ; L0 = R2 * R1
|
+ "#"
|
+; MOV %1,%3 ; R3 = R1
|
+ ""
|
+; ROL 16,%3 ; R3 = (R1 <<< 16)
|
+ [(parallel [(set (match_dup 0) (xor:SI (match_dup 1) (const_int -1)))
|
+; MPYS %2,%3 ; R3 = (R1 <<< 16) * R2
|
+ (clobber (reg:CC CC_REG))])]
|
+; ROL 16,%3 ; R3 = upper bits of (R1<<<16)*R2
|
+ ""
|
+; AND 0x0ffff,%3
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+; ADD %3,%L0 ; L0 = L0 + R3 = L0 + (R1>>16)*R2
|
+;
|
+; MOV %2,%3
|
|
+; ROL 16,%3
|
|
+; MPYS %1,%3
|
|
+; ROL 16,%3
|
|
+; AND 0x0ffff,%3
|
|
+; ADD %3,%0"
|
|
+; [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
|
+
|
|
+;
|
+;
|
+; Still missing DI instructions for smin:DI, smax:DI, movdicc, adddicc,
|
|
+; mult:di, div:di, divu:di
|
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;
|
+;;
|
| Line 8921... |
Line 8888... |
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+(define_expand "cstore<mode>4" ; Store 0 or 1 in %0 based on cmp between %2&%3
|
|
+ [(set (reg:CC CC_REG) (compare:CC (match_operand:ZI 2 "register_operand" "r")
|
|
+ (match_operand:ZI 3 "zip_opb_operand_p" "rO")))
|
|
+ (set (match_operand:ZI 0 "register_operand" "=r") (if_then_else:ZI
|
|
+ (match_operator 1 "ordered_comparison_operator"
|
|
+ [(reg:CC CC_REG) (const_int 0)])
|
|
+ (const_int 1) (const_int 0)))]
|
|
+ ""
|
|
+ )
|
|
+(define_insn "cstoredi4" ; Store 0 or 1 in %0 based on cmp between %2&%3
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (if_then_else:SI (match_operator 1 "ordered_comparison_operator"
|
|
+ [(match_operand:DI 2 "register_operand" "r")
|
|
+ (match_operand:DI 3 "register_operand" "r")])
|
|
+ (const_int 1) (const_int 0)))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ "(ZIP_HAS_DI)"
|
|
+ {
|
|
+ switch(GET_CODE(operands[1])) {
|
|
+ case EQ: return "CLR\t%0\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.Z\t1,%0\n";
|
|
+ case NE: return "CLR\t%0\n\tCMP\t%H3,%H2\n\tCMP.NZ\t%L3,%L2\n\tLDILO.NZ\t1,%0\n";
|
|
+ case LTU: return "CLR\t%0\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.C\t1,%0\n";
|
|
+ case LEU:
|
|
+ if (ZIP_NEW_CONDITION_CODE)
|
|
+ return "CLR\t%0\n\tCMP\t%H2,%H3\n\tCMP.Z\t%L2,%L3\n\tLDILO.NC\t1,%0\n";
|
|
+ else
|
|
+ return "CLR\t%0\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.C\t1,%0\n\tLDILO.Z\t1,%0\n";
|
|
+ case GTU: return "CLR\t%0\n\tCMP\t%H2,%H3\n\tCMP.Z\t%L2,%L3\n\tLDILO.C\t1,%0\n";
|
|
+ case GEU:
|
|
+ if (ZIP_NEW_CONDITION_CODE)
|
|
+ return "CLR\t%0\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.NC\t1,%0\n";
|
|
+ else
|
|
+ return "CLR\t%0\n\tCMP\t%H2,%H3\n\tCMP.Z\t%L2,%L3\n\tLDILO.C\t1,%0\n\tLDILO.Z\t1,%0\n";
|
|
+ default:
|
|
+ gcc_unreachable();
|
|
+ }
|
|
+ }
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;
|
+;;
|
| Line 8973... |
Line 8902... |
+;
|
+;
|
+;
|
+;
|
+;; This will only work so well, since the direction of the compare is
|
+;; This will only work so well, since the direction of the compare is
|
+;; important in unsigned compares.
|
+;; important in unsigned compares.
|
+;;
|
+;;
|
+(define_expand "cmp<mode>"
|
+(define_expand "cmpsi"
|
+ [(set (reg:CC CC_REG) (compare:CC
|
+ [(set (reg:CC CC_REG) (compare:CC
|
+ (match_operand:ZI 0 "register_operand" "r")
|
+ (match_operand:SI 0 "register_operand" "r")
|
+ (match_operand:ZI 1 "nonmemory_operand" "")))]
|
+ (match_operand:SI 1 "nonmemory_operand" "")))]
|
+ ""
|
+ ""
|
+ {
|
+ {
|
+ if (!zip_opb_operand_p(operands[1],SImode)) {
|
+ if (!zip_opb_operand_p(operands[1],SImode)) {
|
+ if (can_create_pseudo_p()) {
|
+ if (can_create_pseudo_p()) {
|
+ //; fprintf(stderr, "Generating pseudo register for compare\n");
|
+ //; fprintf(stderr, "Generating pseudo register for compare\n");
|
| Line 8988... |
Line 8917... |
+ emit_insn(gen_movsi(tmp,operands[1]));
|
+ emit_insn(gen_movsi(tmp,operands[1]));
|
+ operands[1] = tmp;
|
+ operands[1] = tmp;
|
+ } else FAIL;
|
+ } else FAIL;
|
+ }
|
+ }
|
+ })
|
+ })
|
+(define_insn "cmp<mode>_reg"
|
+(define_insn "cmpsi_reg"
|
+ [(set (reg:CC CC_REG) (compare:CC
|
+ [(set (reg:CC CC_REG) (compare:CC
|
+ (match_operand:ZI 0 "register_operand" "r")
|
+ (match_operand:SI 0 "register_operand" "r")
|
+ (match_operand:ZI 1 "zip_opb_single_operand_p" "rO")))]
|
+ (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))]
|
+ ""
|
+ ""
|
+ "CMP\t%1,%0"
|
+ "CMP\t%1,%0"
|
+ [(set_attr "ccresult" "set")])
|
+ [(set_attr "ccresult" "set")])
|
+(define_insn "cmp<mode>_off"
|
+(define_insn "cmpsi_off"
|
+ [(set (reg:CC CC_REG) (compare:CC
|
+ [(set (reg:CC CC_REG) (compare:CC
|
+ (match_operand:ZI 0 "register_operand" "r")
|
+ (match_operand:SI 0 "register_operand" "r")
|
+ (plus:ZI (match_operand:ZI 1 "register_operand" "r")
|
+ (plus:SI (match_operand:SI 1 "register_operand" "r")
|
+ (match_operand 2 "zip_opb_immv_p" "N"))))]
|
+ (match_operand 2 "zip_opb_immv_p" "N"))))]
|
+ ""
|
+ ""
|
+ "CMP\t%2+%1,%0"
|
+ "CMP\t%2+%1,%0"
|
+ [(set_attr "ccresult" "set")])
|
+ [(set_attr "ccresult" "set")])
|
+(define_insn "test<mode>"
|
+(define_insn "testsi"
|
+ [(set (reg:CC CC_REG) (compare:CC (and:ZI (match_operand:ZI 0 "register_operand" "r")
|
+ [(set (reg:CC CC_REG) (compare:CC (and:SI (match_operand:SI 0 "register_operand" "r")
|
+ (match_operand:ZI 1 "zip_opb_single_operand_p" "rO"))
|
+ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))
|
+ (const_int 0)))]
|
+ (const_int 0)))]
|
+ ""
|
+ ""
|
+ "TEST %1,%0"
|
+ "TEST %1,%0"
|
+ [(set_attr "ccresult" "set")])
|
+ [(set_attr "ccresult" "set")])
|
+(define_insn "test<mode>_off"
|
+(define_insn "testsi_off"
|
+ [(set (reg:CC CC_REG) (compare:CC
|
+ [(set (reg:CC CC_REG) (compare:CC
|
+ (and:ZI (match_operand:ZI 0 "register_operand" "r")
|
+ (and:SI (match_operand:SI 0 "register_operand" "r")
|
+ (plus:ZI
|
+ (plus:SI
|
+ (match_operand:ZI 1 "register_operand" "r")
|
+ (match_operand:SI 1 "register_operand" "r")
|
+ (match_operand:ZI 2 "zip_opb_immv_p" "N")))
|
+ (match_operand:SI 2 "zip_opb_immv_p" "N")))
|
+ (const_int 0)))]
|
+ (const_int 0)))]
|
+ ""
|
+ ""
|
+ "TEST %2+%1,%0"
|
+ "TEST %2+%1,%0"
|
+ [(set_attr "ccresult" "set")])
|
+ [(set_attr "ccresult" "set")])
|
+(define_insn "nop"
|
+(define_insn "nop"
|
| Line 9041... |
Line 8970... |
+; other conditions then these. That is, (cond_exec ...) is not as well
|
+; other conditions then these. That is, (cond_exec ...) is not as well
|
+; recognized as (if_then_else ...). So we have to duplicate things to support
|
+; recognized as (if_then_else ...). So we have to duplicate things to support
|
+; both methods.
|
+; both methods.
|
+;
|
+;
|
+(define_cond_exec
|
+(define_cond_exec
|
+ [(ne (reg:CC CC_REG) (const_int 0))]
|
+ [(eq (reg:CC CC_REG) (const_int 0))] "" "[Z]")
|
+ ""
|
|
+ "(NZ)"
|
|
+ [(set_attr "conditional" "yes")])
|
|
+(define_cond_exec
|
|
+ [(lt (reg:CC CC_REG) (const_int 0))]
|
|
+ ""
|
|
+ "(LT)"
|
|
+ [(set_attr "conditional" "yes")])
|
|
+(define_cond_exec
|
+(define_cond_exec
|
+ [(eq (reg:CC CC_REG) (const_int 0))]
|
+ [(ne (reg:CC CC_REG) (const_int 0))] "" "[NZ]")
|
+ ""
|
|
+ "(Z)"
|
|
+ [(set_attr "conditional" "yes")])
|
|
+(define_cond_exec
|
+(define_cond_exec
|
+ [(gt (reg:CC CC_REG) (const_int 0))]
|
+ [(lt (reg:CC CC_REG) (const_int 0))] "" "[LT]")
|
+ ""
|
|
+ "(GT)"
|
|
+ [(set_attr "conditional" "yes")])
|
|
+(define_cond_exec
|
+(define_cond_exec
|
+ [(geu (reg:CC CC_REG) (const_int 0))]
|
+ [(ge (reg:CC CC_REG) (const_int 0))] "" "[GE]")
|
+ "(ZIP_NEW_CONDITION_CODE)"
|
|
+ "(NC)"
|
|
+ [(set_attr "conditional" "yes")])
|
|
+(define_cond_exec
|
+(define_cond_exec
|
+ [(ge (reg:CC CC_REG) (const_int 0))]
|
+ [(ltu (reg:CC CC_REG) (const_int 0))] "" "[C]")
|
+ "(!ZIP_NEW_CONDITION_CODE)"
|
|
+ "(GE)"
|
|
+ [(set_attr "conditional" "yes")])
|
|
+(define_cond_exec
|
+(define_cond_exec
|
+ [(ltu (reg:CC CC_REG) (const_int 0))]
|
+ [(geu (reg:CC CC_REG) (const_int 0))] "" "[NC]")
|
+ ""
|
|
+ "(C)"
|
|
+ [(set_attr "conditional" "yes")])
|
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;
|
+;;
|
| Line 9088... |
Line 8994... |
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;
|
+;
|
+; // Look for #define HAVE_conditional_move to understand how these might be
|
+; // Look for #define HAVE_conditional_move to understand how these might be
|
+; // used.
|
+; // used.
|
+;
|
+;
|
+(define_insn "set_zero_or_one<mode>"
|
+; set_zero_or_one_si
|
+ [(set (match_operand:ZI 0 "register_operand" "=r") (if_then_else:ZI
|
+; movsicc
|
+ (match_operator 1 "ordered_comparison_operator"
|
+(define_expand "movsicc"
|
+ [(reg:CC CC_REG) (const_int 0)])
|
+ [(set (match_operand:SI 0 "nonimmediate_operand" "")
|
+ (const_int 1) (const_int 0)))]
|
+ (if_then_else:SI (match_operand 1 "comparison_operator")
|
+ ""
|
+ (match_operand:SI 2 "general_operand" "")
|
+ { return (zip_set_zero_or_one(operands[1], operands[0]));
|
+ (match_operand:SI 3 "general_operand" "")))]
|
+ }
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
|
+(define_expand "mov<mode>cc"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (if_then_else:ZI (match_operand 1 "comparison_operator")
|
|
+ (match_operand:ZI 2 "general_operand" "rio")
|
|
+ (match_operand:ZI 3 "nonmemory_operand" "rio")))]
|
|
+ ""
|
+ ""
|
+ {
|
+ {
|
+ if (zip_expand_movsicc(operands[0], operands[1], operands[2], operands[3]))
|
+ //; extern void zip_debug_rtx_pfx(const char *, const_rtx);
|
+ DONE;
|
+ //; fprintf(stderr, "MOVSICC\n");
|
+ else
|
+ //; zip_debug_rtx_pfx("- DST: ", operands[0]);
|
+ FAIL;
|
+ //; zip_debug_rtx_pfx("- CMP: ", operands[1]);
|
|
+ //; zip_debug_rtx_pfx("- NEW: ", operands[2]);
|
|
+ //; zip_debug_rtx_pfx("- DEF: ", operands[3]);
|
|
+
|
|
+ if (!REG_P(operands[2]))
|
|
+ operands[2] = force_reg(SImode, operands[2]);
|
|
+
|
|
+ if ((!REG_P(operands[3]))||(REGNO(operands[0]) != REGNO(operands[3])))
|
|
+ emit_insn(gen_movsi(operands[0], operands[3]));
|
|
+ operands[3] = operands[0];
|
|
+
|
|
+
|
|
+ rtx_code ccode = GET_CODE(operands[1]);
|
|
+ rtx cmpop0 = copy_rtx(XEXP(operands[1], 0));
|
|
+ rtx cmpop1 = copy_rtx(XEXP(operands[1], 1));
|
|
+
|
|
+ zip_canonicalize_comparison((int *)&ccode, &cmpop0, &cmpop1, true);
|
|
+ emit_insn(gen_cmpsi(cmpop0, cmpop1));
|
|
+
|
|
+ operands[1] = gen_rtx_fmt_ee(ccode, VOIDmode,
|
|
+ gen_rtx_REG(CCmode, 14), const0_rtx);
|
+ })
|
+ })
|
+(define_insn_and_split "movsicc_bare"
|
+;
|
|
+;
|
|
+;
|
|
+(define_expand "addsicc"
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
+ (if_then_else:SI (match_operator 1 "ordered_comparison_operator"
|
+ (if_then_else:SI (match_operand 1 "comparison_operator")
|
+ [(reg:CC CC_REG) (const_int 0)])
|
+ (plus:SI (match_operand:SI 2 "register_operand" "0")
|
+ (match_operand:SI 2 "general_operand" "rio")
|
+ (match_operand:SI 3 "zip_opb_single_operand_p" "rO"))
|
+ (match_operand:SI 3 "register_operand" "0")))]
|
+ (match_dup 2)))]
|
+ "(zip_supported_condition(GET_CODE(operands[1])))"
|
+ ""
|
+ "#"
|
+ {
|
+ "(reload_completed)"
|
+ //; extern void zip_debug_rtx_pfx(const char *, const_rtx);
|
+ [(cond_exec (match_operator 1 "ordered_comparison_operator"
|
+ //; fprintf(stderr, "ADDSICC\n");
|
+ [(reg:CC CC_REG) (const_int 0)])
|
+ //; zip_debug_rtx_pfx("- DST: ", operands[0]);
|
+ (set (match_dup 0) (match_dup 2)))]
|
+ //; zip_debug_rtx_pfx("- CMP: ", operands[1]);
|
+ "" [(set_attr "predicable" "no")])
|
+ //; zip_debug_rtx_pfx("- OLD: ", operands[2]);
|
|
+ //; zip_debug_rtx_pfx("- INC: ", operands[3]);
|
|
+
|
|
+ if (!REG_P(operands[2]))
|
|
+ operands[2] = force_reg(SImode, operands[2]);
|
|
+ if (REGNO(operands[0]) != REGNO(operands[2]))
|
|
+ emit_insn(gen_movsi(operands[0], operands[2]));
|
|
+ operands[2] = operands[0];
|
|
+
|
|
+ rtx_code ccode = GET_CODE(operands[1]);
|
|
+ rtx cmpop0 = copy_rtx(XEXP(operands[1], 0));
|
|
+ rtx cmpop1 = copy_rtx(XEXP(operands[1], 1));
|
|
+
|
|
+ zip_canonicalize_comparison((int *)&ccode, &cmpop0, &cmpop1, true);
|
|
+ emit_insn(gen_cmpsi(cmpop0, cmpop1));
|
|
+
|
|
+ operands[1] = gen_rtx_fmt_ee(ccode, VOIDmode,
|
|
+ gen_rtx_REG(CCmode, 14), const0_rtx);
|
|
+ }
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
+;
|
+;
|
+;
|
+;
|
+; Dies when trying to do reloads for "ADD.NZ R6,R7,R9"
|
|
+;
|
+;
|
+;(define_insn "add<mode>cc"
|
+(define_expand "notsicc"
|
+; [(set (match_operand:ZI 0 "register_operand" "=r,r")
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
+; (if_then_else:ZI (match_operator 1 "ordered_comparison_operator"
|
+ (if_then_else:SI (match_operand 1 "comparison_operator")
|
+; [(reg:CC CC_REG) (const_int 0)])
|
+ (xor:SI (match_operand:SI 2 "register_operand" "0")
|
+; (plus:ZI (match_operand:ZI 2 "register_operand" "0,r")
|
+ (const_int -1))
|
+; (match_operand:ZI 3 "nonmemory_operand" "rO,M"))
|
+ (match_dup 2)))]
|
+; (match_operand:ZI 4 "register_operand" "0,0")))]
|
+ ""
|
+; ""
|
+ {
|
+; {
|
+ extern void zip_debug_rtx_pfx(const char *, const_rtx);
|
+; return zip_addsicc(operands[0], operands[1], operands[2], operands[3]);
|
+ //; fprintf(stderr, "NOTSICC\n");
|
+; }
|
+ //; zip_debug_rtx_pfx("- DST: ", operands[0]);
|
+; [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
+ //; zip_debug_rtx_pfx("- CMP: ", operands[1]);
|
|
+ //; zip_debug_rtx_pfx("- NOT: ", operands[2]);
|
|
+ //; zip_debug_rtx_pfx("- OLD: ", operands[3]);
|
|
+
|
|
+ if (!REG_P(operands[2]))
|
|
+ operands[2] = force_reg(SImode, operands[2]);
|
|
+ if (REGNO(operands[0]) != REGNO(operands[2]))
|
|
+ emit_insn(gen_movsi(operands[0], operands[2]));
|
|
+
|
|
+ rtx_code ccode = GET_CODE(operands[1]);
|
|
+ rtx cmpop0 = copy_rtx(XEXP(operands[1], 0));
|
|
+ rtx cmpop1 = copy_rtx(XEXP(operands[1], 1));
|
|
+
|
|
+ zip_canonicalize_comparison((int *)&ccode,&cmpop0,&cmpop1,true);
|
|
+ emit_insn(gen_cmpsi(cmpop0, cmpop1));
|
|
+
|
|
+ operands[1] = gen_rtx_fmt_ee(ccode, VOIDmode,
|
|
+ gen_rtx_REG(CCmode, 14), const0_rtx);
|
|
+ }
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
|
+;
|
+;
|
+;
|
|
+(define_expand "negsicc"
|
|
+ [(set (match_operand:SI 0 "register_operand" "+r")
|
|
+ (if_then_else:SI (match_operand 1 "comparison_operator")
|
|
+ (neg:SI (match_operand:SI 2 "register_operand" "0"))
|
|
+ (match_operand:SI 3 "register_operand" "0")))]
|
|
+ ""
|
|
+ {
|
|
+ //; extern void zip_debug_rtx_pfx(const char *, const_rtx);
|
|
+ //; fprintf(stderr, "NEGSICC\n");
|
|
+ //; zip_debug_rtx_pfx("- DST: ", operands[0]);
|
|
+ //; zip_debug_rtx_pfx("- CMP: ", operands[1]);
|
|
+ //; zip_debug_rtx_pfx("- NOT: ", operands[2]);
|
|
+
|
|
+ if (!REG_P(operands[2]))
|
|
+ operands[2] = force_reg(SImode, operands[2]);
|
|
+ if (REGNO(operands[0]) != REGNO(operands[3]))
|
|
+ emit_insn(gen_movsi(operands[0], operands[3]));
|
|
+
|
|
+ rtx_code ccode = GET_CODE(operands[1]);
|
|
+ rtx cmpop0 = copy_rtx(XEXP(operands[1], 0));
|
|
+ rtx cmpop1 = copy_rtx(XEXP(operands[1], 1));
|
|
+
|
|
+ zip_canonicalize_comparison((int *)&ccode,&cmpop0,&cmpop1,true);
|
|
+ emit_insn(gen_cmpsi(cmpop0, cmpop1));
|
|
+
|
|
+ operands[1] = gen_rtx_fmt_ee(ccode, VOIDmode,
|
|
+ gen_rtx_REG(CCmode, 14), const0_rtx);
|
+
|
+
|
|
+ if (REGNO(operands[0]) != REGNO(operands[2]))
|
|
+ emit_insn(gen_movsicc(operands[0], operands[1], operands[2], operands[0]));
|
|
+ }
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
|
+;
|
|
+;
|
|
+(define_expand "cstoresi4"
|
|
+ [(set (reg:CC CC_REG) (compare:CC (match_operand:SI 2 "register_operand" "r")
|
|
+ (match_operand:SI 3 "zip_opb_operand_p" "rO")))
|
|
+ (set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (if_then_else:SI
|
|
+ (match_operator 1 "ordered_comparison_operator"
|
|
+ [(reg:CC CC_REG) (const_int 0)])
|
|
+ (const_int 1) (const_int 0)))]
|
|
+ ""
|
|
+ {
|
|
+ //; extern void zip_debug_rtx_pfx(const char *, const_rtx);
|
|
+ //; fprintf(stderr, "CSTORESI4\n");
|
|
+ //; zip_debug_rtx_pfx("- DST: ", operands[0]);
|
|
+ //; zip_debug_rtx_pfx("- TST: ", operands[1]);
|
|
+ //; zip_debug_rtx_pfx("- A : ", operands[2]);
|
|
+ //; zip_debug_rtx_pfx("- -B: ", operands[3]);
|
|
+
|
|
+ rtx_code ccode = GET_CODE(operands[1]);
|
|
+
|
|
+ zip_canonicalize_comparison((int *)&ccode,&operands[2],&operands[3],true);
|
|
+ emit_insn(gen_cmpsi(operands[2], operands[3]));
|
|
+ emit_insn(gen_movsi(operands[0], const0_rtx));
|
|
+ switch(ccode) {
|
|
+ case EQ:
|
|
+ emit_insn(gen_cmov_eq(operands[0], const1_rtx));
|
|
+ break;
|
|
+ case NE:
|
|
+ emit_insn(gen_cmov_ne(operands[0], const1_rtx));
|
|
+ break;
|
|
+ case LT:
|
|
+ emit_insn(gen_cmov_lt(operands[0], const1_rtx));
|
|
+ break;
|
|
+ case GE:
|
|
+ emit_insn(gen_cmov_ge(operands[0], const1_rtx));
|
|
+ break;
|
|
+ case LTU:
|
|
+ emit_insn(gen_cmov_ltu(operands[0], const1_rtx));
|
|
+ break;
|
|
+ case GEU:
|
|
+ emit_insn(gen_cmov_geu(operands[0], const1_rtx));
|
|
+ break;
|
|
+ default:
|
|
+ FAIL;
|
|
+ } DONE;
|
|
+ }
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
+;
|
+;
|
+;
|
+;
|
+; While an interesting approach, the following suffers from problems when the
|
|
+; move amount is constant. At anything less than four, moves should not require
|
|
+; the movmemSI instruction. At anything greater, if constant, the initial tests
|
|
+; are not required and should result in a hardcoded result. Practically,
|
|
+; though, this should really be a define_expand instruction, calling on the
|
|
+; RTX's of all the respective subinstructions found below. Or, perhaps, it is
|
|
+; better as a subroutine?
|
|
+;
|
|
+;(define_insn "movmemSI"
|
|
+; [(parallel [(set (mem:BLK (match_operand 0 "register_operand" "+r"));Dst
|
|
+; (mem:BLK (match_operand 1 "register_operand" "+r")));Src
|
|
+; (use (match_operand:SI 2 "register_operand" "+r"))]); Length
|
|
+; (match_operand 3 "" "") ;Alignment
|
|
+; (clobber (match_scratch:SI 4 "=r"))
|
|
+; (clobber (match_scratch:SI 5 "=r"))
|
|
+; (clobber (match_scratch:SI 6 "=r"))
|
|
+; (clobber (match_scratch:SI 7 "=r"))]
|
|
+; ""
|
|
+; "TEST\t1,%2
|
|
+; LOD.NZ\t%1,%4
|
|
+; STO.NZ\t%4,%0
|
|
+; ADD.NZ\t1,%0
|
|
+; ADD.NZ\t1,%1
|
|
+; TEST\t2,%2
|
|
+; LOD.NZ\t%1,%4
|
|
+; LOD.NZ\t1(%1),%5
|
|
+; STO.NZ\t%4,(%0)
|
|
+; STO.NZ\t%4,1(%0)
|
|
+; ADD.NZ\t2,%0
|
|
+; ADD.NZ\t2,%1
|
|
+; AND\t-4,%2
|
|
+; BZ\t.Lskp%=\n.Ltop%=:
|
|
+; LOD\t(%1),%4
|
|
+; LOD\t1(%1),%5
|
|
+; LOD\t2(%1,%6
|
|
+; LOD\t3(%1),%7
|
|
+; STO\t%4,(%1)
|
|
+; STO\t%5,1(%1)
|
|
+; STO\t%6,2(%1)
|
|
+; STO\t%7,3(%1)
|
|
+; SUB\t4,%2
|
|
+; BZ\t%.Lskp%=
|
|
+; BRA\t.Ltop%=\n.Lskp%=:"
|
|
+; [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
|
+;(define_insn "setmemsi"
|
|
+; [(parallel
|
|
+; [(set (mem:BLK
|
|
+; (match_operand 0 "register_operand" "+r")); Destination
|
|
+; (match_operand:SI 2 "register_operand" "r")) ; Source
|
|
+; (use (match_operand:SI 1 "register_operand" "+r"))]) ; Length
|
|
+; (match_operand 3 "" "")]
|
|
+; ""
|
|
+; "TEST\t1,%1
|
|
+; STO.NZ\t%2,(%0)
|
|
+; ADD.NZ\t1,%0
|
|
+; TEST\t2,%1
|
|
+; STO.NZ\t%2,(%0)
|
|
+; STO.NZ\t%2,1(%0)
|
|
+; ADD.NZ\t2,%0
|
|
+; AND\t-4,%1
|
|
+; BZ\t.Lskp%=\n.Ltop%=:\n
|
|
+; STO\t%2,(%0)
|
|
+; STO\t%2,1(%0)
|
|
+; STO\t%2,2(%0)
|
|
+; STO\t%2,3(%0)
|
|
+; SUB\t%4,%0
|
|
+; BZ\t.Lskp%=
|
|
+; BRA\t.Ltop%=\n.Lskp%=:"
|
|
+; [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
|
+;;
|
|
+;
|
+;
|
+;
|
+;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;
|
+;;
|
+;; Control flow instructions
|
+;; Control flow instructions
|
| Line 9224... |
Line 9193... |
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+(define_expand "jump"
|
+(define_expand "jump"
|
+ [(set (pc)
|
+ [(set (pc)
|
+ (label_ref (match_operand 0 "" "")))]); // Was general-op, "mro"
|
+ (label_ref (match_operand 0 "" "")))])
|
+(define_insn "jump_const"
|
+(define_insn "jump_const"
|
+ [(set (pc)
|
+ [(set (pc)
|
+ (match_operand:SI 0 "zip_const_address_operand_p" ""))]
|
+ (match_operand:SI 0 "zip_const_address_operand_p" ""))]
|
+ ""
|
+ ""
|
+ "BRA %0"
|
+ "BRA %0"
|
| Line 9262... |
Line 9231... |
+ "JMP %0"
|
+ "JMP %0"
|
+ [(set_attr "ccresult" "unchanged")])
|
+ [(set_attr "ccresult" "unchanged")])
|
+(define_insn "indirect_jump_mem"
|
+(define_insn "indirect_jump_mem"
|
+ [(set (pc) (match_operand:SI 0 "zip_memory_operand_p" "o"))]
|
+ [(set (pc) (match_operand:SI 0 "zip_memory_operand_p" "o"))]
|
+ ""
|
+ ""
|
+ "LOD %0,PC"
|
+ "LW %0,PC"
|
+ [(set_attr "ccresult" "unchanged")])
|
+ [(set_attr "ccresult" "unchanged")])
|
+(define_insn "indirect_jump_off"
|
+(define_insn "indirect_jump_off"
|
+ [(set (pc)
|
+ [(set (pc)
|
+ (plus:SI (match_operand:SI 0 "register_operand" "r")
|
+ (plus:SI (match_operand:SI 0 "register_operand" "r")
|
+ (match_operand:SI 1 "const_int_operand" "M")))]
|
+ (match_operand:SI 1 "const_int_operand" "M")))]
|
| Line 9279... |
Line 9248... |
+;; Op 1&2 the operands of the compare instruction
|
+;; Op 1&2 the operands of the compare instruction
|
+;; Op 3 is the jump label
|
+;; Op 3 is the jump label
|
+;;
|
+;;
|
+;;
|
+;;
|
+;;
|
+;;
|
+(define_expand "cbranch<mode>4"
|
+(define_expand "cbranchsi4"
|
+ [(set (reg:CC CC_REG) (compare:CC (match_operand:ZI 1 "register_operand" "r")
|
+ [(set (reg:CC CC_REG) (compare:CC (match_operand:SI 1 "register_operand" "r")
|
+ (match_operand:ZI 2 "zip_opb_operand_p" "rO")))
|
+ (match_operand:SI 2 "zip_opb_operand_p" "rO")))
|
+ (set (pc) (if_then_else (match_operator 0 "ordered_comparison_operator"
|
+ (set (pc) (if_then_else (match_operator 0 "ordered_comparison_operator"
|
+ [(reg:CC CC_REG) (const_int 0)])
|
+ [(reg:CC CC_REG) (const_int 0)])
|
+ (label_ref (match_operand 3 "" ""))
|
+ (label_ref (match_operand 3 "" ""))
|
+ (pc)))]
|
+ (pc)))]
|
+ ""
|
+ ""
|
+ {
|
+ {
|
+ if (true) {
|
+ if (true) {
|
+ extern void zip_debug_rtx_pfx(const char *, const_rtx);
|
+ //; extern void zip_debug_rtx_pfx(const char *, const_rtx);
|
+ //; Two branches give us no end of difficulty when implementing.
|
+ //; Two branches give us no end of difficulty when implementing.
|
+ //; Let's check for these two branch codes, and swap the
|
+ //; Let's check for these two branch codes, and swap the
|
+ //; comparison to simplify them.
|
+ //; comparison to simplify them.
|
+ //; fprintf(stderr, "CBRANCH\n");
|
+ //; fprintf(stderr, "CBRANCH\n");
|
+ //; zip_debug_rtx_pfx("- CMP: ", operands[0]);
|
+ //; zip_debug_rtx_pfx("- CMP: ", operands[0]);
|
+ //; zip_debug_rtx_pfx("- A : ", operands[1]);
|
+ //; zip_debug_rtx_pfx("- A : ", operands[1]);
|
+ //; zip_debug_rtx_pfx("- B : ", operands[2]);
|
+ //; zip_debug_rtx_pfx("- B : ", operands[2]);
|
+ //; zip_debug_rtx_pfx("- JMP: ", operands[3]);
|
+ //; zip_debug_rtx_pfx("- JMP: ", operands[3]);
|
+ //; Can we do better if we reverse some compares?
|
+ //; Can we do better if we reverse some compares?
|
+ if ((GET_CODE(operands[0])==GTU)&&(REG_P(operands[2]))) {
|
+ //;
|
+ //; fprintf(stderr, "CBRANCH:(GTU,?,REG,?)\n");
|
+ //; We have GE, LT, LTU, and GEU conditions
|
|
+ //; Figure out how to create the other conditions from
|
|
+ //; these.
|
|
+ if (GET_CODE(operands[0])==GTU) {
|
|
+ if (REG_P(operands[2])) {
|
|
+ //; Reverse the comparison
|
+ emit_insn(gen_cmpsi(operands[2], operands[1]));
|
+ emit_insn(gen_cmpsi(operands[2], operands[1]));
|
+ emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
|
+ emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
|
+ DONE;
|
+ DONE;
|
+ } else if((GET_CODE(operands[0])==GEU)&&(REG_P(operands[2]))) {
|
+ } else if ((CONST_INT_P(operands[2]))
|
+ //; fprintf(stderr, "CBRANCH:(GEU,?,REG,?)\n");
|
+ &&(INTVAL(operands[2])>-(1<<17)+2)) {
|
+ if (ZIP_NEW_CONDITION_CODE) {
|
+ //; A > B
|
+ emit_insn(gen_cmpsi(operands[1], operands[2]));
|
+ //; A >= B+1
|
|
+ //; Add one to the integer constant,
|
|
+ //; And use a GEU comparison
|
|
+ emit_insn(gen_cmpsi(operands[1],
|
|
+ GEN_INT(INTVAL(operands[2])+1)));
|
+ emit_jump_insn(gen_cbranch_jmp_geu(operands[3]));
|
+ emit_jump_insn(gen_cbranch_jmp_geu(operands[3]));
|
+ } else {
|
+ DONE;
|
+ emit_insn(gen_cmpsi_off(operands[2], operands[1],
|
+ } else if ((CONST_INT_P(operands[2]))
|
+ GEN_INT(1)));
|
+ &&(can_create_pseudo_p())) {
|
|
+ rtx tmp = gen_reg_rtx(GET_MODE(operands[1]));
|
|
+ emit_insn(gen_movsi(tmp,operands[2]));
|
|
+ emit_insn(gen_cmpsi(tmp,operands[1]));
|
+ emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
|
+ emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
|
+ }
|
+
|
+ DONE;
|
+ DONE;
|
+ } else if ((GET_CODE(operands[0])==LE)&&(REG_P(operands[2]))) {
|
+
|
+ //; fprintf(stderr, "CBRANCH:(LE,?,REG,?)\n");
|
|
+ //; Swap operands, turn into a GTE compare
|
|
+ if (ZIP_NEW_CONDITION_CODE) {
|
|
+ emit_insn(gen_cmpsi_off(operands[1], operands[2],
|
|
+ GEN_INT(1)));
|
|
+ emit_jump_insn(gen_cbranch_jmp_lt(operands[3]));
|
|
+ } else {
|
|
+ emit_insn(gen_cmpsi(operands[2], operands[1]));
|
|
+ emit_jump_insn(gen_cbranch_jmp_ge(operands[3]));
|
|
+ }
|
+ }
|
|
+ } else if (GET_CODE(operands[0]) == LEU) {
|
|
+ if (REG_P(operands[2])) {
|
|
+ //; Reverse the comparison
|
|
+ emit_insn(gen_cmpsi(operands[2],operands[1]));
|
|
+ emit_jump_insn(gen_cbranch_jmp_geu(operands[3]));
|
+ DONE;
|
+ DONE;
|
+ } // ; Otherwise ... just handle the branch normally
|
+ } else if ((CONST_INT_P(operands[2]))
|
+
|
|
+ //; Except ... we can do better for some instructions, such as
|
|
+ //; LE. While we could exchange CMP Rx,Ry into -1(Rx),Ry, it
|
|
+ //; would be difficult to explain to users why MIN_INT didn't
|
|
+ //; compare properly. Hence we only adjust constant integers.
|
|
+ //;
|
|
+ if (GET_CODE(operands[0])==LE) {
|
|
+ if ((CONST_INT_P(operands[2]))
|
|
+ &&(INTVAL(operands[2])<(1<<17)-2)) {
|
+ &&(INTVAL(operands[2])<(1<<17)-2)) {
|
+ //; fprintf(stderr, "CBRANCH:(LE,?,#,?)\n");
|
+ //; A <= B
|
|
+ //; A < B+1
|
|
+ //; Add one to the integer constant,
|
|
+ //; And use a GTU comparison
|
+ emit_insn(gen_cmpsi(operands[1],
|
+ emit_insn(gen_cmpsi(operands[1],
|
+ GEN_INT(INTVAL(operands[2])+1)));
|
+ GEN_INT(INTVAL(operands[2])+1)));
|
+ emit_jump_insn(gen_cbranch_jmp_lt(operands[3]));
|
+ emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
|
+ DONE;
|
|
+ //; Now for the controversial ones--where we add one
|
|
+ //; when it may or may not be permissable. For now, we
|
|
+ //; just do it anyway and postpone the philosophical
|
|
+ //; discussion for later.
|
|
+ } else if (REG_P(operands[2])) {
|
|
+ emit_insn(gen_cmpsi_off(operands[1],
|
|
+ operands[2],GEN_INT(1)));
|
|
+ emit_jump_insn(gen_cbranch_jmp_lt(operands[3]));
|
|
+ DONE;
|
+ DONE;
|
+ } else if ((GET_CODE(operands[2])==PLUS)
|
+ } else if ((CONST_INT_P(operands[2]))
|
+ &&(REG_P(XEXP(operands[2],0)))
|
+ &&(can_create_pseudo_p())) {
|
+ &&(CONST_INT_P(XEXP(operands[2],1)))
|
+ rtx tmp = gen_reg_rtx(GET_MODE(operands[1]));
|
+ &&(INTVAL(XEXP(operands[2],1))<((1<<13)-2))) {
|
+ emit_insn(gen_movsi(tmp,operands[2]));
|
+ emit_insn(gen_cmpsi_off(operands[1],
|
+ emit_insn(gen_cmpsi(tmp,operands[1]));
|
+ XEXP(operands[2],0),
|
+ emit_jump_insn(gen_cbranch_jmp_geu(operands[3]));
|
+ GEN_INT(INTVAL(XEXP(operands[2],1))+1)));
|
|
+ emit_jump_insn(gen_cbranch_jmp_lt(operands[3]));
|
|
+ DONE;
|
+ DONE;
|
|
+
|
+ }
|
+ }
|
+#if (ZIP_NEW_CONDITION_CODE != 0)
|
+ } else if (GET_CODE(operands[0]) == LE) {
|
+ } else if (GET_CODE(operands[0])==GE) {
|
+ if (REG_P(operands[2])) {
|
+ if ((CONST_INT_P(operands[2]))
|
+ //; Reverse the comparison
|
|
+ emit_insn(gen_cmpsi(operands[2],operands[1]));
|
|
+ emit_jump_insn(gen_cbranch_jmp_gte(operands[3]));
|
|
+ DONE;
|
|
+ } else if ((CONST_INT_P(operands[2]))
|
+ &&(INTVAL(operands[2])<(1<<17)-2)) {
|
+ &&(INTVAL(operands[2])<(1<<17)-2)) {
|
+ //; fprintf(stderr, "CBRANCH:(LE,?,#,?)\n");
|
+ //; A <= B
|
|
+ //; A < B+1
|
|
+ //; Add one to the integer constant,
|
|
+ //; And use a GTU comparison
|
+ emit_insn(gen_cmpsi(operands[1],
|
+ emit_insn(gen_cmpsi(operands[1],
|
+ GEN_INT(INTVAL(operands[2])+1)));
|
+ GEN_INT(INTVAL(operands[2])+1)));
|
+ emit_jump_insn(gen_cbranch_jmp_gt(operands[3]));
|
+ emit_jump_insn(gen_cbranch_jmp_lt(operands[3]));
|
+ DONE;
|
|
+ //; Now for the controversial ones--where we add one
|
|
+ //; when it may or may not be permissable. For now, we
|
|
+ //; just do it anyway and postpone the philosophical
|
|
+ //; discussion for later.
|
|
+ } else if (REG_P(operands[2])) {
|
|
+ emit_insn(gen_cmpsi_off(operands[1],
|
|
+ operands[2],GEN_INT(1)));
|
|
+ emit_jump_insn(gen_cbranch_jmp_gt(operands[3]));
|
|
+ DONE;
|
+ DONE;
|
+ } else if ((GET_CODE(operands[2])==PLUS)
|
+ } else if ((CONST_INT_P(operands[2]))
|
+ &&(REG_P(XEXP(operands[2],0)))
|
+ &&(can_create_pseudo_p())) {
|
+ &&(CONST_INT_P(XEXP(operands[2],1)))
|
+ rtx tmp = gen_reg_rtx(GET_MODE(operands[1]));
|
+ &&(INTVAL(XEXP(operands[2],1))<((1<<13)-2))) {
|
+ emit_insn(gen_movsi(tmp,operands[2]));
|
+ emit_insn(gen_cmpsi_off(operands[1],
|
+ emit_insn(gen_cmpsi(tmp,operands[1]));
|
+ XEXP(operands[2],0),
|
+ emit_jump_insn(gen_cbranch_jmp_gte(operands[3]));
|
+ GEN_INT(INTVAL(XEXP(operands[2],1))+1)));
|
|
+ emit_jump_insn(gen_cbranch_jmp_gt(operands[3]));
|
|
+ DONE;
|
+ DONE;
|
|
+
|
+ }
|
+ }
|
+#endif
|
+ } else if (GET_CODE(operands[0]) == GT) {
|
+ } else if (GET_CODE(operands[0])==LEU) {
|
+ if (REG_P(operands[2])) {
|
+#if (ZIP_NEW_CONDITION_CODE != 0)
|
+ //; Reverse the comparison
|
+ emit_insn(gen_cmpsi(operands[1], operands[2]));
|
+ emit_insn(gen_cmpsi(operands[2],operands[1]));
|
+ emit_jump_insn(gen_cbranch_jmp_geu(operands[3]));
|
+ emit_jump_insn(gen_cbranch_jmp_lt(operands[3]));
|
+#else
|
+ DONE;
|
+ if ((CONST_INT_P(operands[2]))
|
+ } else if ((CONST_INT_P(operands[2]))
|
+ &&(INTVAL(operands[2])<(1<<17)-2)) {
|
+ &&(INTVAL(operands[2])<(1<<17)-2)) {
|
+ //; fprintf(stderr, "CBRANCH:(LEU,?,#,?)\n");
|
+ //; A > B
|
|
+ //; A >= B+1
|
|
+ //; Add one to the integer constant,
|
|
+ //; And use a GTU comparison
|
+ emit_insn(gen_cmpsi(operands[1],
|
+ emit_insn(gen_cmpsi(operands[1],
|
+ GEN_INT(INTVAL(operands[2])+1)));
|
+ GEN_INT(INTVAL(operands[2])+1)));
|
+ emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
|
+ emit_jump_insn(gen_cbranch_jmp_gte(operands[3]));
|
+ DONE;
|
|
+ //; Now for the controversial ones--this time having
|
|
+ //; to do with unsigned compares.
|
|
+ } else if (REG_P(operands[2])) {
|
|
+ emit_insn(gen_cmpsi_off(operands[1],
|
|
+ operands[2],GEN_INT(1)));
|
|
+ emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
|
|
+ DONE;
|
+ DONE;
|
+ } else if ((GET_CODE(operands[2])==PLUS)
|
+ } else if ((CONST_INT_P(operands[2]))
|
+ &&(REG_P(XEXP(operands[2],0)))
|
+ &&(can_create_pseudo_p())) {
|
+ &&(CONST_INT_P(XEXP(operands[2],1)))
|
+ rtx tmp = gen_reg_rtx(GET_MODE(operands[1]));
|
+ &&(INTVAL(XEXP(operands[2],1))<((1<<13)-2))) {
|
+ emit_insn(gen_movsi(tmp,operands[2]));
|
+ emit_insn(gen_cmpsi_off(operands[1],
|
+ emit_insn(gen_cmpsi(tmp,operands[1]));
|
+ XEXP(operands[2],0),
|
+ emit_jump_insn(gen_cbranch_jmp_lt(operands[3]));
|
+ GEN_INT(INTVAL(XEXP(operands[2],1))+1)));
|
+
|
+ emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
|
|
+ DONE;
|
+ DONE;
|
+ }
|
+ }
|
+#endif
|
+ }
|
+ }}
|
+ }})
|
+ })
|
|
+(define_insn "cbranch_jmp_eq"
|
+(define_insn "cbranch_jmp_eq"
|
+ [(set (pc) (if_then_else (eq (reg:CC CC_REG) (const_int 0))
|
+ [(set (pc) (if_then_else (eq (reg:CC CC_REG) (const_int 0))
|
+ (label_ref (match_operand 0 "" ""))
|
+ (label_ref (match_operand 0 "" ""))
|
+ (pc)))]
|
+ (pc)))]
|
+ ""
|
+ ""
|
+ "BZ\t%0"
|
+ "BZ\t%0"
|
+ [(set_attr "predicable" "no")
|
+ [(set_attr "predicable" "no")
|
+ (set_attr "conditional" "yes")
|
|
+ (set_attr "ccresult" "unchanged")])
|
+ (set_attr "ccresult" "unchanged")])
|
+(define_insn "cbranch_jmp_neq"
|
+(define_insn "cbranch_jmp_neq"
|
+ [(set (pc) (if_then_else (ne (reg:CC CC_REG) (const_int 0))
|
+ [(set (pc) (if_then_else (ne (reg:CC CC_REG) (const_int 0))
|
+ (label_ref (match_operand 0 "" ""))
|
+ (label_ref (match_operand 0 "" ""))
|
+ (pc)))]
|
+ (pc)))]
|
+ ""
|
+ ""
|
+ "BNZ\t%0"
|
+ "BNZ\t%0"
|
+ [(set_attr "predicable" "no")
|
+ [(set_attr "predicable" "no")
|
+ (set_attr "conditional" "yes")
|
|
+ (set_attr "ccresult" "unchanged")])
|
+ (set_attr "ccresult" "unchanged")])
|
+(define_insn "cbranch_jmp_lt"
|
+(define_insn "cbranch_jmp_lt"
|
+ [(set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))
|
+ [(set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))
|
+ (label_ref (match_operand 0 "" ""))
|
+ (label_ref (match_operand 0 "" ""))
|
+ (pc)))]
|
+ (pc)))]
|
+ ""
|
+ ""
|
+ "BLT\t%0"
|
+ "BLT\t%0"
|
+ [(set_attr "predicable" "no")
|
+ [(set_attr "predicable" "no")
|
+ (set_attr "conditional" "yes")
|
|
+ (set_attr "ccresult" "unchanged")])
|
+ (set_attr "ccresult" "unchanged")])
|
+(define_insn "cbranch_jmp_le"
|
+(define_insn "cbranch_jmp_le"
|
+ [(set (pc) (if_then_else (le (reg:CC CC_REG) (const_int 0))
|
+ [(set (pc) (if_then_else (le (reg:CC CC_REG) (const_int 0))
|
+ (label_ref (match_operand 0 "" ""))
|
+ (label_ref (match_operand 0 "" ""))
|
+ (pc)))]
|
+ (pc)))]
|
+ ""
|
+ ""
|
+ "BLT\t%0
|
+ "BLT\t%0\n\tBZ\t%0"
|
+ BZ\t%0"
|
|
+ [(set_attr "predicable" "no")
|
+ [(set_attr "predicable" "no")
|
+ (set_attr "conditional" "yes")
|
|
+ (set_attr "ccresult" "unchanged")])
|
+ (set_attr "ccresult" "unchanged")])
|
+(define_insn "cbranch_jmp_gt"
|
+(define_insn "cbranch_jmp_gt"
|
+ [(set (pc) (if_then_else (gt (reg:CC CC_REG) (const_int 0))
|
+ [(set (pc) (if_then_else (gt (reg:CC CC_REG) (const_int 0))
|
+ (label_ref (match_operand 0 "" ""))
|
+ (label_ref (match_operand 0 "" ""))
|
+ (pc)))]
|
+ (pc)))]
|
+ ""
|
+ ""
|
+ "BGT\t%0"
|
+ "BZ\t.Lgt%=\n\tBGE\t%0\n\t.Lgt%=:"
|
+ [(set_attr "predicable" "no")
|
|
+ (set_attr "conditional" "yes")
|
|
+ (set_attr "ccresult" "unchanged")])
|
|
+(define_expand "cbranch_jmp_ge"
|
|
+ [(set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))
|
|
+ (label_ref (match_operand 0 "" ""))
|
|
+ (pc)))])
|
|
+(define_insn "cbranch_jmp_ge_newcc"
|
|
+ [(set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))
|
|
+ (label_ref (match_operand 0 "" ""))
|
|
+ (pc)))]
|
|
+ "(ZIP_NEW_CONDITION_CODE)"
|
|
+ "BGT\t%0\n\tBZ\t%0"
|
|
+ [(set_attr "predicable" "no")
|
+ [(set_attr "predicable" "no")
|
+ (set_attr "conditional" "yes")
|
|
+ (set_attr "ccresult" "unchanged")])
|
+ (set_attr "ccresult" "unchanged")])
|
+(define_insn "cbranch_jmp_ge_oldcc"
|
+(define_insn "cbranch_jmp_gte"
|
+ [(set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))
|
+ [(set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))
|
+ (label_ref (match_operand 0 "" ""))
|
+ (label_ref (match_operand 0 "" ""))
|
+ (pc)))]
|
+ (pc)))]
|
+ "(!ZIP_NEW_CONDITION_CODE)"
|
+ ""
|
+ "BGE\t%0"
|
+ "BGE\t%0"
|
+ [(set_attr "predicable" "no")
|
+ [(set_attr "predicable" "no")
|
+ (set_attr "conditional" "yes")
|
|
+ (set_attr "ccresult" "unchanged")])
|
+ (set_attr "ccresult" "unchanged")])
|
+(define_insn "cbranch_jmp_ltu"
|
+(define_insn "cbranch_jmp_ltu"
|
+ [(set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
|
+ [(set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
|
+ (label_ref (match_operand 0 "" ""))
|
+ (label_ref (match_operand 0 "" ""))
|
+ (pc)))]
|
+ (pc)))]
|
+ ""
|
+ ""
|
+ "BC\t%0"
|
+ "BC\t%0"
|
+ [(set_attr "predicable" "no")
|
+ [(set_attr "predicable" "no")
|
+ (set_attr "conditional" "yes")
|
|
+ (set_attr "ccresult" "unchanged")])
|
+ (set_attr "ccresult" "unchanged")])
|
+(define_expand "cbranch_jmp_gtu"
|
+(define_insn "cbranch_jmp_gtu"
|
+ [(set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))
|
|
+ (label_ref (match_operand 0 "" ""))
|
|
+ (pc)))])
|
|
+(define_insn "cbranch_jmp_gtu_newcc"
|
|
+ [(set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))
|
+ [(set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))
|
+ (label_ref (match_operand 0 "" ""))
|
+ (label_ref (match_operand 0 "" ""))
|
+ (pc)))]
|
+ (pc)))]
|
+ "(ZIP_NEW_CONDITION_CODE)"
|
+ ""
|
+ ;// We could flip the condition code, and then be able to jump.
|
+ ;// We could flip the condition code, and then be able to jump.
|
+ ;// The problem is that doing this adjusts the condition code, and
|
+ ;// The problem is that doing this adjusts the condition code, and
|
+ ;// we aren't allowed to do that here.
|
+ ;// we aren't allowed to do that here.
|
+ ;//
|
+ ;//
|
+ ;// The problem here is the equals. What do you do if A=B? Our new
|
+ ;// The problem here is the equals. What do you do if A=B? Our new
|
+ ;// condition tests for A>=B, not A>B. So ... how do you get rid of
|
+ ;// condition tests for A>=B, not A>B. So ... how do you get rid of
|
+ ;// the equals? We do so here by branching around. (sigh)
|
+ ;// the equals? We do so here by branching around. (sigh)
|
+ "BZ\t.Lgtu%=\n\tBNC\t%0\n.Lgtu%=:"
|
+ "BZ\t.Lgtu%=\n\tBNC\t%0\n.Lgtu%=:"
|
+ [(set_attr "predicable" "no")
|
+ [(set_attr "predicable" "no")
|
+ (set_attr "conditional" "yes")
|
|
+ (set_attr "ccresult" "unknown")])
|
|
+(define_insn "cbranch_jmp_gtu_oldcc"
|
|
+ [(set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))
|
|
+ (label_ref (match_operand 0 "" ""))
|
|
+ (pc)))]
|
|
+ "(!ZIP_NEW_CONDITION_CODE)"
|
|
+ ;// We could flip the condition code, and then be able to jump.
|
|
+ ;// The problem is that doing this adjusts the condition code, and
|
|
+ ;// we aren't allowed to do that here.
|
|
+ ;//
|
|
+ ;// With the old condition code, things are worse. Sure, we still need
|
|
+ ;// to branch around, but it's worse 'cause we are always branching
|
|
+ ;// around the conditional branch. With the new condition code, we
|
|
+ ;// only branch around on part of the unsupported condition.
|
|
+ "BC\t.Lgtu%=\n\tBZ\t.Lgtu%=\n\tBRA\t%0\n.Lgtu%=:"
|
|
+ [(set_attr "predicable" "no")
|
|
+ (set_attr "conditional" "yes")
|
|
+ (set_attr "ccresult" "unknown")])
|
+ (set_attr "ccresult" "unknown")])
|
+(define_insn "cbranch_jmp_leu"
|
+(define_insn "cbranch_jmp_leu"
|
+ [(set (pc) (if_then_else (leu (reg:CC CC_REG) (const_int 0))
|
+ [(set (pc) (if_then_else (leu (reg:CC CC_REG) (const_int 0))
|
+ (label_ref (match_operand 0 "" ""))
|
+ (label_ref (match_operand 0 "" ""))
|
+ (pc)))]
|
+ (pc)))]
|
+ "" ; Need to check for both LTU (i.e. C) and Z
|
+ "" ; Need to check for both LTU (i.e. C) and Z
|
+ "BC\t%0
|
+ "BC\t%0
|
+ BZ\t%0"
|
+ BZ\t%0"
|
+ [(set_attr "predicable" "no")
|
+ [(set_attr "predicable" "no")
|
+ (set_attr "conditional" "yes")
|
|
+ (set_attr "ccresult" "unchanged")])
|
+ (set_attr "ccresult" "unchanged")])
|
+(define_expand "cbranch_jmp_geu"
|
+(define_insn "cbranch_jmp_geu"
|
+ [(set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
|
|
+ (label_ref (match_operand 0 "" ""))
|
|
+ (pc)))])
|
|
+(define_insn "cbranch_jmp_geu_newcc"
|
|
+ [(set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
|
+ [(set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
|
+ (label_ref (match_operand 0 "" ""))
|
+ (label_ref (match_operand 0 "" ""))
|
+ (pc)))]
|
+ (pc)))]
|
+ "(ZIP_NEW_CONDITION_CODE)"
|
+ ""
|
+ "BNC\t%0"
|
+ "BNC\t%0"
|
+ [(set_attr "predicable" "no")
|
+ [(set_attr "predicable" "no")
|
+ (set_attr "conditional" "yes")
|
|
+ (set_attr "ccresult" "unchanged")])
|
|
+(define_insn "cbranch_jmp_geu_oldcc"
|
|
+ [(set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
|
|
+ (label_ref (match_operand 0 "" ""))
|
|
+ (pc)))]
|
|
+ "(!ZIP_NEW_CONDITION_CODE)"
|
|
+ "BC\t.Lgeu%=\n\tBRA\t%0\n.Lgeu%=:"
|
|
+ [(set_attr "predicable" "no")
|
|
+ (set_attr "conditional" "yes")
|
|
+ (set_attr "ccresult" "unchanged")])
|
+ (set_attr "ccresult" "unchanged")])
|
+(define_insn "cbranchdi4"
|
|
+ [(set (pc) (if_then_else
|
|
+ (match_operator 0 "ordered_comparison_operator"
|
|
+ [(match_operand:DI 1 "register_operand" "r")
|
|
+ (match_operand:DI 2 "register_operand" "r")])
|
|
+ (label_ref (match_operand 3 "" ""))
|
|
+ (pc)))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ "(ZIP_HAS_DI)"
|
|
+ {
|
|
+ switch(GET_CODE(operands[0])) {
|
|
+ case EQ:
|
|
+ return "CMP\t%H2,%H1\n\tCMP.Z\t%L2,%L1\n\tBZ\t%3";
|
|
+ case NE:
|
|
+ return "CMP\t%H2,%H1\n\tCMP.NZ\t%L2,%L1\n\tBNZ\t%3";
|
|
+ case LE:
|
|
+ if (ZIP_NEW_CONDITION_CODE)
|
|
+ return "CMP\t%H2,%H1\n\tBLT\t%3\n\tBNZ\t.Ldi%=\n\tCMP\t%L1,%L2\n\tBNC\t%3\n.Ldi%=:";
|
|
+ else
|
|
+ return "CMP\t%H2,%H1\n\tBLT\t%3\n\tBNZ\t.Ldi%=\n\tCMP\t%L2,%L1\n\tBC\t%3\n\tBZ\t%3\n.Ldi%=";
|
|
+ case GT:
|
|
+ return "CMP\t%H1,%H2\n\tBLT\t%3\n\tBNZ\t.Ldi%=\n\tCMP\t%L1,%L2\n\tBC\t%3\n.Ldi%=:";
|
|
+ case LT:
|
|
+ return "CMP\t%H2,%H1\n\tBLT\t%3\n\tBNZ\t.Ldi%=\n\tCMP\t%L2,%L1\n\tBC\t%3\n.Ldi%=:";
|
|
+ case GE:
|
|
+ if (ZIP_NEW_CONDITION_CODE)
|
|
+ return "CMP\t%H1,%H2\n\tBLT\t%3\n\tBNZ\t.Ldi%=\n\tCMP\t%L2,%L1\n\tBNC\t%3\n.Ldi%=:";
|
|
+ else
|
|
+ return "CMP\t%H1,%H2\n\tBLT\t%3\n\tBNZ\t.Ldi%=\n\tCMP\t%L1,%L2\n\tBC\t%3\nBZ\t%3\n.Ldi%=:";
|
|
+ case LTU:
|
|
+ return "CMP\t%H2,%H1\n\tCMP.Z\t%L2,%L1\n\tBC\t%3\n";
|
|
+ case LEU:
|
|
+ if (ZIP_NEW_CONDITION_CODE)
|
|
+ return "CMP\t%H1,%H2\n\tBC\t.Ldi%=\n\tCMP\t%L1,%L2\n\tBNC\t%3\n.Ldi%=:";
|
|
+ else
|
|
+ return "CMP\t%H2,%H1\n\tCMP.Z\t%L2,%L1\n\tBC\t%3\n\tBZ\t%3";
|
|
+ case GTU:
|
|
+ return "CMP\t%H1,%H2\n\tBC\t%3\nBNZ\t%.Ldi%=\nCMP\t%L1,%L2\n\tBC\t%3\n.Ldi%=:";
|
|
+ case GEU:
|
|
+ if (ZIP_NEW_CONDITION_CODE)
|
|
+ return "CMP\t%H2,%H1\n\tCMP.Z\t%L2,%L1\n\tBNC\t%3";
|
|
+ else
|
|
+ return "CMP\t%H1,%H2\n\tCMP.Z\t%L1,%L2\n\tBC\t%3\nBZ\t%3";
|
|
+ default:
|
|
+ gcc_unreachable();
|
|
+ }
|
|
+ }
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
|
+;
|
|
+;
|
+;
|
+;
|
+;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;
|
+;;
|
+;; Looping constructs
|
+;; Looping constructs
|
| Line 9628... |
Line 9474... |
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+(define_insn "decrement_and_branch_until_zero"
|
+(define_insn "decrement_and_branch_until_zero"
|
+ [(set (pc)
|
+ [(set (pc) (if_then_else
|
+ (if_then_else
|
+ (ge (plus:SI (match_operand:SI 0 "register_operand" "+r,Q")
|
+ (ge (plus:SI (match_operand:SI 0 "register_operand" "+r")
|
|
+ (const_int -1)) (const_int 0))
|
+ (const_int -1)) (const_int 0))
|
+ (label_ref (match_operand 1 "" ""))
|
+ (label_ref (match_operand 1 "" ""))
|
+ (pc)))
|
+ (pc)))
|
+ (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))
|
+ (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))
|
+ ;(set (reg:CC CC_REG)
|
+ ;(set (reg:CC CC_REG)
|
+ ;(compare:CC (minus:SI (match_dup 0) (const_int 1))
|
+ ;(compare:CC (minus:SI (match_dup 0) (const_int 1))
|
+ ;(const_int 0)))
|
+ ;(const_int 0)))
|
|
+ (clobber (match_scratch:SI 2 "=r,r"))
|
+ (clobber (reg:CC CC_REG))]
|
+ (clobber (reg:CC CC_REG))]
|
+ ""
|
+ ""
|
+ "ADD\t-1,%0\n\tBLT\t.Ldec%=\n\tBRA\t%1\n.Ldec%=:"
|
+ {
|
|
+ if (MEM_P(operands[0])) {
|
|
+ //; We could also go searching for dead regs if
|
|
+ //; necessary
|
|
+ return "LW %0,%2"
|
|
+ "\t; decrement_and_branch_until_zero(MEM)\n"
|
|
+ "\tADD\t-1,%2\t\n"
|
|
+ "\tSW %2,%0\n"
|
|
+ "\tBLT\t.Ldec%=\n"
|
|
+ "\tBRA\t%1\n"
|
|
+ ".Ldec%=:";
|
|
+ }
|
|
+ return "ADD\t-1,%0\t; decrement_and_branch_until_zero (REG)\n"
|
|
+ "\tBLT\t.Ldec%=\n"
|
|
+ "\tBRA\t%1\n"
|
|
+ ".Ldec%=:";
|
|
+ }
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+;
|
+;
|
+;
|
+;
|
+(define_insn "doloop_end"
|
+; Requires TARGET_CAN_USE_DOLOOP_P to be set appropriately in order to use
|
+ [(set (pc)
|
+;
|
+ (if_then_else
|
+;
|
+ (ne (plus:SI (match_operand:SI 0 "register_operand" "+r")
|
+;(define_insn "doloop_end"
|
+ (const_int -1)) (const_int 0))
|
+ ;[(set (pc)
|
+ (label_ref (match_operand 1 "" ""))
|
+ ;(if_then_else
|
+ (pc)))
|
+ ;(ne (plus:SI (match_operand:SI 0 "register_operand" "+r")
|
+ (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))
|
+ ;;(const_int -1)) (const_int 0))
|
+ ; (set (reg:CC CC_REG)
|
+ ;(label_ref (match_operand 1 "" ""))
|
+ ; (compare:CC (minus:SI (match_dup 0) (const_int 1))
|
+ ;(pc)))
|
+ ; (const_int 0)))
|
+ ;(set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))
|
+ (clobber (reg:CC CC_REG))]
|
+ ;; (set (reg:CC CC_REG)
|
+ "(reload_completed)"
|
+ ;; (compare:CC (minus:SI (match_dup 0) (const_int 1))
|
+ "ADD\t-1,%0\n\tBZ\t.Lloop%=\n\tBRA\t%1\n.Lloop%=:"
|
+ ;; (const_int 0)))
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+ ;(clobber (reg:CC CC_REG))]
|
|
+ ;"(reload_completed)"
|
|
+ ;"ADD\t-1,%0\t; doloop_end\n\tBZ\t.Lloop%=\n\tBRA\t%1\n.Lloop%=:"
|
|
+ ;[(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+;
|
+;
|
+; Since we have a doloop_end, we must also have a doloop_begin. Since the
|
+; Since we have a doloop_end, we must also have a doloop_begin. Since the
|
+; ZipCPU has no special begin looping instruction, we'll simply define this
|
+; ZipCPU has no special begin looping instruction, we'll simply define this
|
+; as a null instruction.
|
+; as a null instruction.
|
+(define_expand "doloop_begin" [(const_int 0)] "(0)")
|
+;
|
|
+; (define_expand "doloop_begin" [(const_int 0)] "(0)")
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
| Line 9701... |
Line 9567... |
+ [(call (match_operand 0 "" "")
|
+ [(call (match_operand 0 "" "")
|
+ (match_operand 1 "" ""))]
|
+ (match_operand 1 "" ""))]
|
+ ""
|
+ ""
|
+ {
|
+ {
|
+ if (MEM_P(operands[0])) {
|
+ if (MEM_P(operands[0])) {
|
+ // This should always be the case
|
+ ;// extern void zip_debug_rtx(const_rtx);
|
|
+ ;//
|
|
+ ;// fprintf(stderr, "CALL: ");
|
|
+ ;// zip_debug_rtx(operands[0]);
|
|
+ ;//
|
|
+ ;//
|
|
+ ;// This should always be the case
|
+ rtx addr = XEXP(operands[0],0);
|
+ rtx addr = XEXP(operands[0],0);
|
+ if (zip_const_address_operand_p(addr, SImode)) {
|
+ if (zip_const_address_operand_p(addr, SImode)) {
|
+ //; fprintf(stderr, "Generating gen_void_call_const()\n");
|
+ //; fprintf(stderr, "Generating gen_void_call_const()\n");
|
+ emit_call_insn(gen_void_call_const(addr,
|
+ emit_call_insn(gen_void_call_const(addr,
|
+ operands[1]));
|
+ operands[1]));
|
+ } else if ((MEM_P(addr))&&(zip_address_operand(
|
+ } else if ((MEM_P(addr))&&(zip_address_operand(
|
+ XEXP(addr,0)))) {
|
+ XEXP(addr,0)))) {
|
|
+ fprintf(stderr, "ERR: ZIP.MD::CALL INDIRECT\n");
|
+ emit_call_insn(gen_void_call_mem(XEXP(addr,0),
|
+ emit_call_insn(gen_void_call_mem(XEXP(addr,0),
|
+ operands[1]));
|
+ operands[1]));
|
|
+ gcc_assert(0);
|
+ } else {
|
+ } else {
|
+ emit_call_insn(gen_void_call_var(addr,
|
+ emit_call_insn(gen_void_call_var(operands[0],
|
+ operands[1]));
|
+ operands[1]));
|
+ }
|
+ }
|
+ DONE;
|
+ DONE;
|
+ }
|
+ } else FAIL;
|
+ })
|
+ })
|
+;
|
+;
|
+(define_expand "sibcall"
|
+(define_expand "sibcall"
|
+ [(call (mem:SI (match_operand 0 "zip_const_address_operand_p" ""))
|
+ [(call (mem:SI (match_operand 0 "zip_const_address_operand_p" ""))
|
+ (match_operand 1 "" ""))
|
+ (match_operand 1 "" ""))
|
| Line 9728... |
Line 9602... |
+ (use (reg:SI RTN_REG))
|
+ (use (reg:SI RTN_REG))
|
+ (simple_return)]
|
+ (simple_return)]
|
+ ""
|
+ ""
|
+ {
|
+ {
|
+ if (MEM_P(operands[0])) {
|
+ if (MEM_P(operands[0])) {
|
+ // This should always be the case
|
+ ;// extern void zip_debug_rtx(const_rtx);
|
|
+ ;//
|
|
+ ;// fprintf(stderr, "CALL: ");
|
|
+ ;// zip_debug_rtx(operands[0]);
|
|
+ ;//
|
|
+ ;//
|
|
+ ;// This should always be the case
|
+ rtx addr = XEXP(operands[0],0);
|
+ rtx addr = XEXP(operands[0],0);
|
+ if (zip_const_address_operand_p(addr, SImode)) {
|
+ if (zip_const_address_operand_p(addr, SImode)) {
|
+ //; fprintf(stderr, "Generating gen_void_call_const()\n");
|
+ //; fprintf(stderr, "Generating gen_void_call_const()\n");
|
+ emit_call_insn(gen_void_sibcall_const(addr,
|
+ emit_call_insn(gen_void_sibcall_const(addr,
|
+ operands[1]));
|
+ operands[1]));
|
+ } else if ((MEM_P(addr))&&(zip_address_operand(
|
+ } else if ((MEM_P(addr))&&(zip_address_operand(
|
+ XEXP(addr,0)))) {
|
+ XEXP(addr,0)))) {
|
|
+ fprintf(stderr, "ERR: ZIP.MD::SIBCALL INDIRECT\n");
|
+ emit_call_insn(gen_void_sibcall_mem(XEXP(addr,0),
|
+ emit_call_insn(gen_void_sibcall_mem(XEXP(addr,0),
|
+ operands[1]));
|
+ operands[1]));
|
|
+ gcc_assert(0);
|
+ } else {
|
+ } else {
|
+ emit_call_insn(gen_void_sibcall_var(addr,
|
+ emit_call_insn(gen_void_sibcall_var(operands[0],
|
+ operands[1]));
|
+ operands[1]));
|
+ }
|
+ }
|
+ DONE;
|
+ DONE;
|
+ }
|
+ } else FAIL;
|
+ }) ; "BAR\t%0\n"
|
+ }) ; "BAR\t%0\n"
|
+;
|
+;
|
+(define_insn "void_sibcall_const"
|
+(define_insn "void_sibcall_const"
|
+ [(call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p" ""))
|
+ [(call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p" ""))
|
+ (match_operand 1 "const_int_operand" "n"))
|
+ (match_operand 1 "const_int_operand" "n"))
|
| Line 9762... |
Line 9644... |
+ (match_operand 1 "const_int_operand" "n"))
|
+ (match_operand 1 "const_int_operand" "n"))
|
+ (use (reg:SI RTN_REG))
|
+ (use (reg:SI RTN_REG))
|
+ (clobber (reg:CC CC_REG))
|
+ (clobber (reg:CC CC_REG))
|
+ (simple_return)]
|
+ (simple_return)]
|
+ ""
|
+ ""
|
+ "LOD\t%0,PC"
|
+ "LW\t%0,PC"
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+;
|
+;
|
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
|
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
|
+(define_insn "void_sibcall_var"
|
+(define_insn "void_sibcall_var"
|
+ [(call (mem:SI (match_operand:SI 0 "zip_address_operand_p" ""))
|
+ [(call (match_operand:SI 0 "zip_memory_operand_p" "")
|
+ (match_operand 1 "const_int_operand" "n"))
|
+ (match_operand 1 "const_int_operand" "n"))
|
+ (use (reg:SI RTN_REG))
|
+ (use (reg:SI RTN_REG))
|
+ (clobber (reg:CC CC_REG))
|
+ (clobber (reg:CC CC_REG))
|
+ (simple_return)]
|
+ (simple_return)]
|
+ ""
|
+ ""
|
| Line 9788... |
Line 9670... |
+ (clobber (reg:CC CC_REG))
|
+ (clobber (reg:CC CC_REG))
|
+ (simple_return)]
|
+ (simple_return)]
|
+ ""
|
+ ""
|
+ {
|
+ {
|
+ if (MEM_P(operands[1])) {
|
+ if (MEM_P(operands[1])) {
|
|
+ ;// extern void zip_debug_rtx(const_rtx);
|
|
+ ;//
|
|
+ ;// fprintf(stderr, "SIBCALL/V: ");
|
|
+ ;// zip_debug_rtx(operands[1]);
|
|
+ ;//
|
|
+ ;//
|
|
+ ;// This should always be the case
|
+ rtx addr = XEXP(operands[1],0);
|
+ rtx addr = XEXP(operands[1],0);
|
+ if (zip_const_address_operand_p(addr, SImode)) {
|
+ if (zip_const_address_operand_p(addr, SImode)) {
|
+ emit_call_insn(gen_reg_sibcall_const(addr, operands[2]));
|
+ emit_call_insn(gen_reg_sibcall_const(operands[0], addr, operands[2]));
|
+ } else if ((MEM_P(addr))&&(zip_address_operand(XEXP(addr,0)))) {
|
+ } else if ((MEM_P(addr))&&(zip_address_operand(XEXP(addr,0)))) {
|
+ emit_call_insn(gen_reg_sibcall_mem(XEXP(addr,0), operands[2]));
|
+ fprintf(stderr, "ERR: ZIP.MD::SIBCALL-VALUE() INDIRECT\n");
|
|
+ emit_call_insn(gen_reg_sibcall_mem(operands[0], XEXP(addr,0), operands[2]));
|
|
+ gcc_assert(0);
|
+ } else {
|
+ } else {
|
+ //; fprintf(stderr, "ZIP.MD::CALL-VALUE() INDIRECT\n");
|
+ emit_call_insn(gen_reg_sibcall_var(operands[0], operands[1], operands[2]));
|
+ emit_call_insn(gen_reg_sibcall_var(addr, operands[2]));
|
|
+ }
|
+ }
|
+ DONE;
|
+ DONE;
|
+ }
|
+ } else FAIL;
|
+ })
|
+ })
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
| Line 9825... |
Line 9715... |
+ [(call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p" ""))
|
+ [(call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p" ""))
|
+ (match_operand 1 "const_int_operand" "n"))
|
+ (match_operand 1 "const_int_operand" "n"))
|
+ (clobber (reg:SI RTN_REG))
|
+ (clobber (reg:SI RTN_REG))
|
+ (clobber (reg:CC CC_REG))]
|
+ (clobber (reg:CC CC_REG))]
|
+ ""
|
+ ""
|
+ "MOV .Lcall%=(PC),R0\;BRA\t%0\n.Lcall%=:"
|
+ "JSR\t%0"
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+(define_insn "void_call_mem"
|
+(define_insn "void_call_mem"
|
+ [(call (mem:SI (match_operand:SI 0 "zip_memory_operand_p" "Q"))
|
+ [(call (mem:SI (match_operand:SI 0 "zip_memory_operand_p" "Q"))
|
+ (match_operand 1 "const_int_operand" "n"))
|
+ (match_operand 1 "const_int_operand" "n"))
|
+ (clobber (reg:SI RTN_REG))
|
+ (clobber (reg:SI RTN_REG))
|
+ (clobber (reg:CC CC_REG))]
|
+ (clobber (reg:CC CC_REG))]
|
+ ""
|
+ ""
|
+ "MOV .Lcall%=(PC),R0\;LOD\t%0,PC\n.Lcall%=:"
|
+ "MOV .Lcall%=(PC),R0\;LW\t%0,PC\n.Lcall%=:"
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+;
|
+;
|
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
|
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
|
+(define_insn "void_call_var"
|
+(define_insn "void_call_var"
|
+ [(call (mem:SI (match_operand:SI 0 "zip_address_operand_p" ""))
|
+ [(call (match_operand:SI 0 "zip_memory_operand_p" "")
|
+ (match_operand 1 "const_int_operand" "n"))
|
+ (match_operand 1 "const_int_operand" "n"))
|
+ (clobber (reg:SI RTN_REG))
|
+ (clobber (reg:SI RTN_REG))
|
+ (clobber (reg:CC CC_REG))]
|
+ (clobber (reg:CC CC_REG))]
|
+ ""
|
+ ""
|
+ "MOV .Lcall%=(PC),R0\;JMP\t%0\n.Lcall%=:"
|
+ {
|
|
+ if (REG_P(operands[0]))
|
|
+ return "JSR\t(%0)";
|
|
+ else
|
|
+ return "JSR\t%0";
|
|
+ }
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+;
|
+;
|
+;
|
+;
|
+(define_expand "call_value"
|
+(define_expand "call_value"
|
+ [(parallel [(set (reg:SI RTNV_REG)
|
+ [(parallel [(set (match_operand 0 "register_operand")
|
+ (call (match_operand:SI 1 "" "")
|
+ (call (match_operand:SI 1 "" "")
|
+ (match_operand 2 "const_int_operand" "n")))
|
+ (match_operand 2 "const_int_operand" "n")))
|
+ (set (match_operand:SI 0 "register_operand" "=r") (reg:SI RTNV_REG))
|
+ (clobber (reg:SI RTN_REG))
|
+ (clobber (reg:CC CC_REG))])]
|
+ (clobber (reg:CC CC_REG))])]
|
+ ""
|
+ ""
|
+ {
|
+ {
|
+ //; extern void zip_debug_rtx(const_rtx);
|
|
+ //; fprintf(stderr, "ZIP.MD::CALL-VALUE()\n");
|
|
+ //; zip_debug_rtx(operands[1]);
|
|
+ if (MEM_P(operands[1])) {
|
+ if (MEM_P(operands[1])) {
|
+ //; fprintf(stderr, "ZIP.MD::CALL-VALUE() MEM_P\n");
|
+ ;// extern void zip_debug_rtx(const_rtx);
|
+ //; zip_debug_rtx(operands[1]);
|
+ ;//
|
|
+ ;// fprintf(stderr, "CALL/V: ");
|
|
+ ;// zip_debug_rtx(operands[1]);
|
|
+ ;//
|
|
+ ;//
|
+ //; This should always be the case
|
+ //; This should always be the case
|
+ rtx addr = XEXP(operands[1],0);
|
+ rtx addr = XEXP(operands[1],0);
|
+ if (zip_const_address_operand_p(addr, SImode)) {
|
+ if (zip_const_address_operand_p(addr, SImode)) {
|
+ //; fprintf(stderr, "Generating gen_reg_call_const()\n");
|
+ //; fprintf(stderr, "Generating gen_reg_call_const()\n");
|
+ emit_call_insn(gen_reg_call_const(addr, operands[2]));
|
+ emit_call_insn(gen_reg_call_const(operands[0], addr, operands[2]));
|
+ } else if ((MEM_P(addr))&&(zip_address_operand(XEXP(addr,0)))) {
|
+ } else if ((MEM_P(addr))&&(zip_address_operand(XEXP(addr,0)))) {
|
+ //; fprintf(stderr, "ZIP.MD::CALL-VALUE() INDIRECT\n");
|
+ fprintf(stderr, "ERR: ZIP.MD::CALL-VALUE() INDIRECT\n");
|
+ emit_call_insn(gen_reg_call_mem(XEXP(addr,0), operands[2]));
|
+ emit_call_insn(gen_reg_call_mem(operands[0], XEXP(addr,0), operands[2]));
|
|
+ gcc_assert(0);
|
+ } else {
|
+ } else {
|
+ //; fprintf(stderr, "ZIP.MD::CALL-VALUE() INDIRECT\n");
|
+ //; fprintf(stderr, "ZIP.MD::CALL-VALUE() INDIRECT\n");
|
+ emit_call_insn(gen_reg_call_var(addr, operands[2]));
|
+ emit_call_insn(gen_reg_call_var(operands[0], operands[1], operands[2]));
|
+ }
|
+ }
|
+ DONE;
|
+ DONE;
|
+ }
|
+ } else FAIL;
|
+ })
|
+ })
|
+(define_insn "reg_call_const"
|
+(define_insn "reg_call_const"
|
+ [(set (reg:SI RTNV_REG)
|
+ [(set (match_operand 0 "register_operand" "")
|
+ (call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p" ""))
|
+ (call (mem:SI (match_operand:SI 1 "zip_const_address_operand_p" ""))
|
+ (match_operand 1 "const_int_operand" "n")))
|
+ (match_operand 2 "const_int_operand" "n")))
|
+ (clobber (reg:SI RTN_REG))
|
+ (clobber (reg:SI RTN_REG))
|
+ (clobber (reg:CC CC_REG))]
|
+ (clobber (reg:CC CC_REG))]
|
+ ""
|
+ ""
|
+ "MOV .Lcall%=(PC),R0\;BRA\t%0\n.Lcall%=:"
|
+ "JSR\t%1"
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+(define_insn "reg_call_mem"
|
+(define_insn "reg_call_mem"
|
+ [(set (reg:SI RTNV_REG)
|
+ [(set (match_operand 0 "register_operand" "")
|
+ (call (mem:SI (match_operand:SI 0 "zip_memory_operand_p" "Q"))
|
+ (call (mem:SI (match_operand:SI 1 "zip_memory_operand_p" "Q"))
|
+ (match_operand 1 "const_int_operand" "n")))
|
+ (match_operand 2 "const_int_operand" "n")))
|
+ (clobber (reg:SI RTN_REG))
|
+ (clobber (reg:SI RTN_REG))
|
+ (clobber (reg:CC CC_REG))]
|
+ (clobber (reg:CC CC_REG))]
|
+ ""
|
+ ""
|
+ "MOV .Lcall%=(PC),R0\n\tLOD\t%0,PC\n.Lcall%=:"
|
+ "MOV .Lcall%=(PC),R0\t; CALL MEM (untested)\n\tLW\t%1,PC\n.Lcall%=:"
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+;
|
+;
|
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
|
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
|
+(define_insn "reg_call_var"
|
+(define_insn "reg_call_var"
|
+ [(set (reg:SI RTNV_REG)
|
+ [(set (match_operand 0 "register_operand" "")
|
+ (call (mem:SI (match_operand:SI 0 "zip_address_operand_p" ""))
|
+ (call (match_operand:SI 1 "zip_memory_operand_p" "")
|
+ (match_operand 1 "const_int_operand" "n")))
|
+ (match_operand 2 "const_int_operand" "n")))
|
+ (clobber (reg:SI RTN_REG))
|
+ (clobber (reg:SI RTN_REG))
|
+ (clobber (reg:CC CC_REG))]
|
+ (clobber (reg:CC CC_REG))]
|
+ ""
|
+ ""
|
+ "MOV .Lcall%=(PC),R0\n\tJMP\t%0\n.Lcall%=:"
|
+ {
|
|
+ ;// extern void zip_debug_rtx(const_rtx);
|
|
+
|
|
+ ;// fprintf(stderr, "CALL-V/REG: ");
|
|
+ ;// zip_debug_rtx(operands[0]);
|
|
+
|
|
+ if (REG_P(operands[1]))
|
|
+ return "JSR\t(%1)";
|
|
+ else
|
|
+ return "JSR\t%1";
|
|
+ }
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+(define_insn "reg_sibcall_const"
|
+(define_insn "reg_sibcall_const"
|
+ [(set (reg:SI RTNV_REG)
|
+ [(set (match_operand 0 "register_operand" "")
|
+ (call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p" ""))
|
+ (call (mem:SI (match_operand:SI 1 "zip_const_address_operand_p" ""))
|
+ (match_operand 1 "const_int_operand" "n")))
|
+ (match_operand 2 "const_int_operand" "n")))
|
+ (use (reg:SI RTN_REG))
|
+ (use (reg:SI RTN_REG))
|
+ (clobber (reg:CC CC_REG))
|
+ (clobber (reg:CC CC_REG))
|
+ (simple_return)]
|
+ (simple_return)]
|
+ ""
|
+ ""
|
+ "BRA\t%0"
|
+ "BRA\t%1"
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+(define_insn "reg_sibcall_mem"
|
+(define_insn "reg_sibcall_mem"
|
+ [(set (reg:SI RTNV_REG)
|
+ [(set (match_operand 0 "register_operand" "")
|
+ (call (mem:SI (match_operand:SI 0 "zip_memory_operand_p" "Q"))
|
+ (call (mem:SI (match_operand:SI 1 "zip_memory_operand_p" "Q"))
|
+ (match_operand 1 "const_int_operand" "n")))
|
+ (match_operand 2 "const_int_operand" "n")))
|
+ (use (reg:SI RTN_REG))
|
+ (use (reg:SI RTN_REG))
|
+ (clobber (reg:CC CC_REG))
|
+ (clobber (reg:CC CC_REG))
|
+ (simple_return)]
|
+ (simple_return)]
|
+ ""
|
+ ""
|
+ "LOD\t%0,PC"
|
+ "LW\t%1,PC"
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+;
|
+;
|
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
|
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
|
+(define_insn "reg_sibcall_var"
|
+(define_insn "reg_sibcall_var"
|
+ [(set (reg:SI RTNV_REG)
|
+ [(set (match_operand 0 "register_operand" "")
|
+ (call (mem:SI (match_operand:SI 0 "zip_address_operand_p" ""))
|
+ (call (match_operand:SI 1 "zip_memory_operand_p" "")
|
+ (match_operand 1 "const_int_operand" "n")))
|
+ (match_operand 2 "const_int_operand" "n")))
|
+ (use (reg:SI RTN_REG))
|
+ (use (reg:SI RTN_REG))
|
+ (clobber (reg:CC CC_REG))
|
+ (clobber (reg:CC CC_REG))
|
+ (simple_return)]
|
+ (simple_return)]
|
+ ""
|
+ ""
|
+ "JMP\t%0"
|
+ {
|
|
+ if (REG_P(operands[1]))
|
|
+ return "JMP\t(%1); REG_SIBCALL_VAR";
|
|
+ else
|
|
+ return "JMP\t%1";
|
|
+ }
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
| Line 9996... |
Line 9908... |
+ [(set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))
|
+ [(set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))
|
+ (return) (pc)))]
|
+ (return) (pc)))]
|
+ "zip_use_return_insn()"
|
+ "zip_use_return_insn()"
|
+ "RETN.LT"
|
+ "RETN.LT"
|
+ [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
|
+ [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
|
+(define_insn "return_if_gt"
|
|
+ [(set (pc) (if_then_else (gt (reg:CC CC_REG) (const_int 0))
|
|
+ (return) (pc)))]
|
|
+ "zip_use_return_insn()"
|
|
+ "RETN.GT"
|
|
+ [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
|
|
+;(define_insn "return_if_gte"
|
|
+ ;[(set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))
|
|
+ ;(return) (pc)))]
|
|
+ ;"((ZIP_NEW_CONDITION_CODE)&&(zip_use_return_insn()))"
|
|
+ ;"RETN.GT\n\tRETN.Z"
|
|
+ ;[(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
|
|
+(define_insn "return_if_gte"
|
+(define_insn "return_if_gte"
|
+ [(set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))
|
+ [(set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))
|
+ (return) (pc)))]
|
+ (return) (pc)))]
|
+ "((!ZIP_NEW_CONDITION_CODE)&&(zip_use_return_insn()))"
|
+ "(zip_use_return_insn())"
|
+ "RETN.GTE"
|
+ "RETN.GTE"
|
+ [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
|
+ [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
|
+(define_insn "return_if_ltu"
|
+(define_insn "return_if_ltu"
|
+ [(set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
|
+ [(set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
|
+ (return) (pc)))]
|
+ (return) (pc)))]
|
| Line 10023... |
Line 9923... |
+ "RETN.C"
|
+ "RETN.C"
|
+ [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
|
+ [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
|
+(define_insn "return_if_geu"
|
+(define_insn "return_if_geu"
|
+ [(set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
|
+ [(set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
|
+ (return) (pc)))]
|
+ (return) (pc)))]
|
+ "((ZIP_NEW_CONDITION_CODE)&&(zip_use_return_insn()))"
|
+ "(zip_use_return_insn())"
|
+ "RETN.NC"
|
+ "RETN.NC"
|
+ [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
|
+ [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
| Line 10087... |
Line 9987... |
+ "(!ZIP_USER)"
|
+ "(!ZIP_USER)"
|
+ "MOV\tuR0,%1
|
+ "MOV\tuR0,%1
|
+ MOV\tuR1,%2
|
+ MOV\tuR1,%2
|
+ MOV\tuR2,%3
|
+ MOV\tuR2,%3
|
+ MOV\tuR3,%4
|
+ MOV\tuR3,%4
|
+ STO\t%1,%0
|
+ SW\t%1,%0
|
+ STO\t%2,1(%0)
|
+ SW\t%2,4(%0)
|
+ STO\t%3,2(%0)
|
+ SW\t%3,8(%0)
|
+ STO\t%4,3(%0)
|
+ SW\t%4,12(%0)
|
+ MOV\tuR4,%1
|
+ MOV\tuR4,%1
|
+ MOV\tuR5,%2
|
+ MOV\tuR5,%2
|
+ MOV\tuR6,%3
|
+ MOV\tuR6,%3
|
+ MOV\tuR7,%4
|
+ MOV\tuR7,%4
|
+ STO\t%1,4(%0)
|
+ SW\t%1,16(%0)
|
+ STO\t%2,5(%0)
|
+ SW\t%2,20(%0)
|
+ STO\t%3,6(%0)
|
+ SW\t%3,24(%0)
|
+ STO\t%4,7(%0)
|
+ SW\t%4,28(%0)
|
+ MOV\tuR8,%1
|
+ MOV\tuR8,%1
|
+ MOV\tuR9,%2
|
+ MOV\tuR9,%2
|
+ MOV\tuR10,%3
|
+ MOV\tuR10,%3
|
+ MOV\tuR11,%4
|
+ MOV\tuR11,%4
|
+ STO\t%1,8(%0)
|
+ SW\t%1,32(%0)
|
+ STO\t%2,9(%0)
|
+ SW\t%2,36(%0)
|
+ STO\t%3,10(%0)
|
+ SW\t%3,40(%0)
|
+ STO\t%4,11(%0)
|
+ SW\t%4,44(%0)
|
+ MOV\tuR12,%1
|
+ MOV\tuR12,%1
|
+ MOV\tuSP,%2
|
+ MOV\tuSP,%2
|
+ MOV\tuCC,%3
|
+ MOV\tuCC,%3
|
+ MOV\tuPC,%4
|
+ MOV\tuPC,%4
|
+ STO\t%1,12(%0)
|
+ SW\t%1,48(%0)
|
+ STO\t%2,13(%0)
|
+ SW\t%2,52(%0)
|
+ STO\t%3,14(%0)
|
+ SW\t%3,56(%0)
|
+ STO\t%4,15(%0)"
|
+ SW\t%4,60(%0)"
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
+;
|
+;
|
+; See the comment above about why operand 0, %0, *must* be a "+r" operand,
|
+; See the comment above about why operand 0, %0, *must* be a "+r" operand,
|
+; even though we don't really read (or change) its value throughout this
|
+; even though we don't really read (or change) its value throughout this
|
+; operation.
|
+; operation.
|
| Line 10129... |
Line 10029... |
+ (clobber (match_scratch:SI 1 "=r"))
|
+ (clobber (match_scratch:SI 1 "=r"))
|
+ (clobber (match_scratch:SI 2 "=r"))
|
+ (clobber (match_scratch:SI 2 "=r"))
|
+ (clobber (match_scratch:SI 3 "=r"))
|
+ (clobber (match_scratch:SI 3 "=r"))
|
+ (clobber (match_scratch:SI 4 "=r"))]
|
+ (clobber (match_scratch:SI 4 "=r"))]
|
+ "(!ZIP_USER)"
|
+ "(!ZIP_USER)"
|
+ "LOD\t0(%0),%1
|
+ "LW\t0(%0),%1
|
+ LOD\t1(%0),%2
|
+ LW\t4(%0),%2
|
+ LOD\t2(%0),%3
|
+ LW\t8(%0),%3
|
+ LOD\t3(%0),%4
|
+ LW\t12(%0),%4
|
+ MOV\t%1,uR0
|
+ MOV\t%1,uR0
|
+ MOV\t%2,uR1
|
+ MOV\t%2,uR1
|
+ MOV\t%3,uR2
|
+ MOV\t%3,uR2
|
+ MOV\t%4,uR3
|
+ MOV\t%4,uR3
|
+ LOD\t4(%0),%1
|
+ LW\t16(%0),%1
|
+ LOD\t5(%0),%2
|
+ LW\t20(%0),%2
|
+ LOD\t6(%0),%3
|
+ LW\t24(%0),%3
|
+ LOD\t7(%0),%4
|
+ LW\t28(%0),%4
|
+ MOV\t%1,uR4
|
+ MOV\t%1,uR4
|
+ MOV\t%2,uR5
|
+ MOV\t%2,uR5
|
+ MOV\t%3,uR6
|
+ MOV\t%3,uR6
|
+ MOV\t%4,uR7
|
+ MOV\t%4,uR7
|
+ LOD\t8(%0),%1
|
+ LW\t32(%0),%1
|
+ LOD\t9(%0),%2
|
+ LW\t36(%0),%2
|
+ LOD\t10(%0),%3
|
+ LW\t40(%0),%3
|
+ LOD\t11(%0),%4
|
+ LW\t44(%0),%4
|
+ MOV\t%1,uR8
|
+ MOV\t%1,uR8
|
+ MOV\t%2,uR9
|
+ MOV\t%2,uR9
|
+ MOV\t%3,uR10
|
+ MOV\t%3,uR10
|
+ MOV\t%4,uR11
|
+ MOV\t%4,uR11
|
+ LOD\t12(%0),%1
|
+ LW\t48(%0),%1
|
+ LOD\t13(%0),%2
|
+ LW\t52(%0),%2
|
+ LOD\t14(%0),%3
|
+ LW\t56(%0),%3
|
+ LOD\t15(%0),%4
|
+ LW\t60(%0),%4
|
+ MOV\t%1,uR12
|
+ MOV\t%1,uR12
|
+ MOV\t%2,uSP
|
+ MOV\t%2,uSP
|
+ MOV\t%3,uCC
|
+ MOV\t%3,uCC
|
+ MOV\t%4,uPC"
|
+ MOV\t%4,uPC"
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
| Line 10185... |
Line 10085... |
+ [(set_attr "ccresult" "unchanged")])
|
+ [(set_attr "ccresult" "unchanged")])
|
+(define_insn "zip_cc_sto"
|
+(define_insn "zip_cc_sto"
|
+ [(set (mem:SI (match_operand:SI 0 "register_operand" "r"))
|
+ [(set (mem:SI (match_operand:SI 0 "register_operand" "r"))
|
+ (unspec_volatile:SI [(reg:SI CC_REG)] UNSPEC_GETCC))]
|
+ (unspec_volatile:SI [(reg:SI CC_REG)] UNSPEC_GETCC))]
|
+ ""
|
+ ""
|
+ "STO\tCC,(%0)"
|
+ "SW\tCC,(%0)"
|
+ [(set_attr "ccresult" "unchanged")])
|
+ [(set_attr "ccresult" "unchanged")])
|
+(define_insn "zip_cc_sto_off"
|
+(define_insn "zip_cc_sto_off"
|
+ [(set (mem:SI (plus:SI
|
+ [(set (mem:SI (plus:SI
|
+ (match_operand:SI 0 "register_operand" "r")
|
+ (match_operand:SI 0 "register_operand" "r")
|
+ (match_operand:SI 1 "const_int_operand" "N")))
|
+ (match_operand:SI 1 "const_int_operand" "N")))
|
+ (unspec_volatile:SI [(reg:SI CC_REG)] UNSPEC_GETCC))]
|
+ (unspec_volatile:SI [(reg:SI CC_REG)] UNSPEC_GETCC))]
|
+ ""
|
+ ""
|
+ "STO\tCC,%1(%0)"
|
+ "SW\tCC,%1(%0)"
|
+ [(set_attr "ccresult" "unchanged")])
|
+ [(set_attr "ccresult" "unchanged")])
|
+(define_insn "ldilo"
|
+(define_insn "ldilo"
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
+ (unspec:SI [(match_operand:SI 1 "immediate_operand" "")] UNSPEC_LDILO))]
|
+ (unspec:SI [(match_operand:SI 1 "immediate_operand" "")] UNSPEC_LDILO))]
|
+ ""
|
+ ""
|
| Line 10236... |
Line 10136... |
+ [(trap_if (const_int 1) (const_int 0))]
|
+ [(trap_if (const_int 1) (const_int 0))]
|
+ ""
|
+ ""
|
+ "BREAK"
|
+ "BREAK"
|
+ [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
|
+ [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
|
+;
|
+;
|
+(define_expand "ctrap<mode>4"
|
+(define_expand "ctrapsi4"
|
+ [(set (reg:CC CC_REG) (compare:CC
|
+ [(set (reg:CC CC_REG) (compare:CC
|
+ (match_operand:ZI 1 "register_operand" "r")
|
+ (match_operand:SI 1 "register_operand" "r")
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
+ (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
|
+ (trap_if (match_operator 0 "ordered_comparison_operator"
|
+ (trap_if (match_operator 0 "ordered_comparison_operator"
|
+ [(reg:CC CC_REG) (const_int 0)])
|
+ [(reg:CC CC_REG) (const_int 0)])
|
+ (match_operand 3 "const_int_operand" "O"))]
|
+ (match_operand 3 "const_int_operand" "O"))]
|
+ ""
|
+ ""
|
+ )
|
+ )
|
| Line 10256... |
Line 10156... |
+ [(set_attr "predicable" "no")])
|
+ [(set_attr "predicable" "no")])
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
|
+(include "zip-di.md")
|
|
+(include "zip-ops.md")
|
+(include "zip-float.md")
|
+(include "zip-float.md")
|
+(include "zip-sync.md")
|
+(include "zip-sync.md")
|
+(include "zip-peephole.md")
|
+(include "zip-peephole.md")
|
+;
|
+;
|
+;
|
+;
|
| Line 10303... |
Line 10205... |
+; MOV %ID,R0
|
+; MOV %ID,R0
|
+; CLR CC
|
+; CLR CC
|
+; cmove ... the conditional move, created from a
|
+; cmove ... the conditional move, created from a
|
+; (set (match_op 0 "" "r") (if_then_else (condition) (a) (reg X))))
|
+; (set (match_op 0 "" "r") (if_then_else (condition) (a) (reg X))))
|
+; pattern
|
+; pattern
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-modes.def gcc-5.3.0-zip/gcc/config/zip/zip-modes.def
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip-modes.def gcc-6.2.0-zip/gcc/config/zip/zip-modes.def
|
--- gcc-5.3.0-original/gcc/config/zip/zip-modes.def 1969-12-31 19:00:00.000000000 -0500
|
--- gcc-6.2.0/gcc/config/zip/zip-modes.def 1969-12-31 19:00:00.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/config/zip/zip-modes.def 2016-03-08 12:10:21.982586940 -0500
|
+++ gcc-6.2.0-zip/gcc/config/zip/zip-modes.def 2017-01-10 12:46:54.791966242 -0500
|
@@ -0,0 +1,23 @@
|
@@ -0,0 +1 @@
|
+/*
|
+#define BITS_PER_UNIT 8
|
+ * Commends in C-long comment form
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip-peephole.md gcc-6.2.0-zip/gcc/config/zip/zip-peephole.md
|
+ * class
|
--- gcc-6.2.0/gcc/config/zip/zip-peephole.md 1969-12-31 19:00:00.000000000 -0500
|
+ * Mode = "SI"
|
+++ gcc-6.2.0-zip/gcc/config/zip/zip-peephole.md 2017-03-01 15:46:02.440221158 -0500
|
+ * PRECISION, BYTESIZE, COUNT ??
|
@@ -0,0 +1,768 @@
|
+ * FORMAT
|
|
+ * EXPR
|
|
+ *
|
|
+ * The manual says I need to define BITS_PER_UNIT here.
|
|
+ */
|
|
+// INT_MODE(QI, 1);
|
|
+// INT_MODE(HI, 1);
|
|
+// INT_MODE(SI, 1);
|
|
+// INT_MODE(DI, 2);
|
|
+
|
|
+// FLOAT_MODE(SF, 1, ieee_single_format);
|
|
+// FLOAT_MODE(DF, 2, ieee_single_format);
|
|
+
|
|
+// We cannot override machmodes.def from here. Thus, even though our QI,
|
|
+// HI, and SI modes are all 1-byte, we cant set them that way here. The
|
|
+// change needed to be made in machmodes.def. Hence, here is a target
|
|
+// configuration change--in machmodes.def--that properly belonged in the
|
|
+// config directory.
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-peephole.md gcc-5.3.0-zip/gcc/config/zip/zip-peephole.md
|
|
--- gcc-5.3.0-original/gcc/config/zip/zip-peephole.md 1969-12-31 19:00:00.000000000 -0500
|
|
+++ gcc-5.3.0-zip/gcc/config/zip/zip-peephole.md 2016-11-09 12:12:15.750820248 -0500
|
|
@@ -0,0 +1,617 @@
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;
|
+;;
|
+;; Filename: zip-peephole.md
|
+;; Filename: zip-peephole.md
|
+;;
|
+;;
|
+;; Project: Zip CPU -- a small, lightweight, RISC CPU soft core
|
+;; Project: Zip CPU -- a small, lightweight, RISC CPU soft core
|
| Line 10350... |
Line 10230... |
+;; Creator: Dan Gisselquist, Ph.D.
|
+;; Creator: Dan Gisselquist, Ph.D.
|
+;; Gisselquist Technology, LLC
|
+;; Gisselquist Technology, LLC
|
+;;
|
+;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;
|
+;;
|
+;; Copyright (C) 2015, Gisselquist Technology, LLC
|
+;; Copyright (C) 2015,2017, Gisselquist Technology, LLC
|
+;;
|
+;;
|
+;; This program is free software (firmware): you can redistribute it and/or
|
+;; This program is free software (firmware): you can redistribute it and/or
|
+;; modify it under the terms of the GNU General Public License as published
|
+;; modify it under the terms of the GNU General Public License as published
|
+;; by the Free Software Foundation, either version 3 of the License, or (at
|
+;; by the Free Software Foundation, either version 3 of the License, or (at
|
+;; your option) any later version.
|
+;; your option) any later version.
|
| Line 10872... |
Line 10752... |
+; TEST #/Rz,Rx
|
+; TEST #/Rz,Rx
|
+;
|
+;
|
+(define_peephole2
|
+(define_peephole2
|
+ [(set (match_operand:SI 0 "register_operand")
|
+ [(set (match_operand:SI 0 "register_operand")
|
+ (match_operand:SI 1 "register_operand"))
|
+ (match_operand:SI 1 "register_operand"))
|
+ (parallel [(set (match_dup 0)
|
+ (parallel [(set (match_operand:SI 3 "register_operand")
|
+ (and:SI (match_dup 0)
|
+ (and:SI (match_dup 0)
|
+ (match_operand:SI 2 "zip_opb_single_operand_p")))
|
+ (match_operand:SI 2 "zip_opb_single_operand_p")))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
+ ]
|
+ ]
|
+ "((1)||(ZIP_PEEPHOLE))&&(peep2_regno_dead_p(2, REGNO(operands[0])))"
|
+ "((1)||(ZIP_PEEPHOLE))&&(peep2_regno_dead_p(2, REGNO(operands[0])))&&(peep2_regno_dead_p(2, REGNO(operands[3])))"
|
+ [(set (reg:CC CC_REG) (compare:CC (and:ZI (match_dup 1) (match_dup 2))
|
+ [(set (reg:CC CC_REG) (compare:CC (and:SI (match_dup 1) (match_dup 2))
|
+ (const_int 0)))])
|
+ (const_int 0)))])
|
+;
|
+;
|
|
+;
|
|
+; Match:
|
|
+; LB OpB,Rx
|
|
+; AND 255,Rx (in form of zero_extend)
|
|
+; Transform to:
|
|
+; LB OpB,Rx
|
|
+;
|
|
+;
|
|
+(define_peephole2
|
|
+ [(set (match_operand:QI 0 "register_operand")
|
|
+ (match_operand:QI 1 "memory_operand"))
|
|
+ (parallel [(set (match_operand:SI 2 "register_operand")
|
|
+ (zero_extend:SI (match_dup 0)))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ "((1)||(ZIP_PEEPHOLE))"
|
|
+ [(parallel [(set (match_dup 2) (zero_extend:SI (match_dup 1)))
|
|
+ (clobber (reg:CC CC_REG))])])
|
|
+;
|
|
+;
|
|
+;
|
|
+; Match:
|
|
+; LW OpB,Rx
|
|
+; AND 65535,Rx
|
|
+; Transform to:
|
|
+; LW OpB,Rx
|
|
+;
|
|
+;
|
|
+(define_peephole2
|
|
+ [(set (match_operand:HI 0 "register_operand")
|
|
+ (match_operand:HI 1 "memory_operand"))
|
|
+ (parallel [(set (match_operand:SI 2 "register_operand")
|
|
+ (zero_extend:SI (match_dup 0)))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ "((1)||(ZIP_PEEPHOLE))
|
|
+ &&(REG_P(operands[0]))
|
|
+ &&(REG_P(operands[2]))
|
|
+ &&(REGNO(operands[0])==REGNO(operands[2]))"
|
|
+ [(parallel [(set (match_dup 2) (zero_extend:SI (match_dup 1)))
|
|
+ (clobber (reg:CC CC_REG))])])
|
|
+;
|
|
+;
|
|
+;
|
|
+; Match:
|
|
+; LDI 0,Rx
|
|
+; LDI.y #,Rx
|
|
+; Add Rx,Ry
|
|
+; Transform to:
|
|
+; Add.y #,Ry
|
|
+;
|
|
+;
|
|
+(define_peephole2
|
|
+ [(set (match_operand:SI 0 "register_operand") (const_int 0))
|
|
+ (set (match_dup 0)
|
|
+ (if_then_else:SI
|
|
+ (match_operator 1 "ordered_comparison_operator"
|
|
+ [(reg:CC CC_REG) (const_int 0)])
|
|
+ (match_operand:SI 2 "zip_opb_single_operand_p") (match_dup 0)))
|
|
+ (parallel [
|
|
+ (set (match_operand:SI 3 "register_operand")
|
|
+ (plus:SI (match_dup 3) (match_dup 0)))
|
|
+ (clobber (reg:CC CC_REG))
|
|
+ ])]
|
|
+ "((1)||(ZIP_PEEPHOLE))
|
|
+ &&(peep2_regno_dead_p(3, REGNO(operands[0])))"
|
|
+ [(set (match_dup 3)
|
|
+ (if_then_else:SI
|
|
+ (match_op_dup 1 [(reg:CC CC_REG) (const_int 0)])
|
|
+ (plus:SI (match_dup 3) (match_dup 2))
|
|
+ (match_dup 3)))])
|
|
+;
|
|
+;
|
|
+; Match:
|
|
+; LDI 0,Rx
|
|
+; LDI.y #,Rx
|
|
+; XOR Rx,Rc
|
|
+; Transform to:
|
|
+; XOR.y #,Ry
|
|
+;
|
|
+;
|
|
+(define_peephole2
|
|
+ [(set (match_operand:SI 0 "register_operand") (const_int 0))
|
|
+ (set (match_dup 0)
|
|
+ (if_then_else:SI
|
|
+ (match_operator 1 "ordered_comparison_operator"
|
|
+ [(reg:CC CC_REG) (const_int 0)])
|
|
+ (match_operand:SI 2 "zip_opb_single_operand_p") (match_dup 0)))
|
|
+ (parallel [
|
|
+ (set (match_operand:SI 3 "register_operand")
|
|
+ (xor:SI (match_dup 3) (match_dup 0)))
|
|
+ (clobber (reg:CC CC_REG))
|
|
+ ])]
|
|
+ "((1)||(ZIP_PEEPHOLE))
|
|
+ &&(peep2_regno_dead_p(3, REGNO(operands[0])))"
|
|
+ [(set (match_dup 3)
|
|
+ (if_then_else:SI
|
|
+ (match_op_dup 1 [(reg:CC CC_REG) (const_int 0)])
|
|
+ (xor:SI (match_dup 3) (match_dup 2))
|
|
+ (match_dup 3)))])
|
|
+;
|
|
+;
|
|
+;
|
|
+;
|
|
+;
|
|
+; Match:
|
|
+; LDI 0,Rx
|
|
+; LDI.y #,Rx
|
|
+; OR Rx,Rc
|
|
+; Transform to:
|
|
+; OR.y #,Ry
|
|
+;
|
|
+;
|
|
+;
|
|
+(define_peephole2
|
|
+ [(set (match_operand:SI 0 "register_operand") (const_int 0))
|
|
+ (set (match_dup 0)
|
|
+ (if_then_else:SI (match_operator 1 "ordered_comparison_operator"
|
|
+ [(reg:CC CC_REG) (const_int 0)])
|
|
+ (match_operand:SI 2 "zip_opb_single_operand_p") (match_dup 0)))
|
|
+ (parallel [(set (match_operand:SI 3 "register_operand")
|
|
+ (ior:SI (match_dup 3) (match_dup 0)))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ "((1)||(ZIP_PEEPHOLE))
|
|
+ &&(peep2_regno_dead_p(3, REGNO(operands[0])))"
|
|
+ [(set (match_dup 3)
|
|
+ (if_then_else:SI
|
|
+ (match_op_dup 1 [(reg:CC CC_REG) (const_int 0)])
|
|
+ (ior:SI (match_dup 3) (match_dup 2))
|
|
+ (match_dup 3)))])
|
|
+;
|
|
+;
|
|
+;
|
|
+; Match:
|
|
+; AND 255,Rx
|
|
+; SB OpB,Rx
|
|
+; (AND Rx is DEAD)
|
|
+; Transform to:
|
|
+; SB OpB,Rx
|
|
+;
|
|
+;
|
|
+;(define_peephole2
|
|
+ ;[(set (match_operand:SI 2 "register_operand")
|
|
+ ;(zero_extend:SI (match_operand:SI 0)))
|
|
+ ;[(set (match_operand:QI 0 "memory_operand")
|
|
+ ;(match_operand:QI 1 "memory_operand"))
|
|
+ ;"((1)||(ZIP_PEEPHOLE))"
|
|
+ ;[(set (match_dup 2) (zero_extend:SI (match_dup 1)))])
|
|
+;
|
|
+;
|
|
+;
|
|
+;
|
|
+;
|
+; Match:
|
+; Match:
|
+; (call ...
|
+; (call ...
|
+; (set (pc) (label))
|
+; (set (pc) (label))
|
+; or (in asm)
|
+; or (in asm)
|
+; MOV .Lcallx(PC),R0
|
+; MOV .Lcallx(PC),R0
|
| Line 10951... |
Line 10982... |
+;
|
+;
|
+; STILL MISSING:
|
+; STILL MISSING:
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-protos.h gcc-5.3.0-zip/gcc/config/zip/zip-protos.h
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip-protos.h gcc-6.2.0-zip/gcc/config/zip/zip-protos.h
|
--- gcc-5.3.0-original/gcc/config/zip/zip-protos.h 1969-12-31 19:00:00.000000000 -0500
|
--- gcc-6.2.0/gcc/config/zip/zip-protos.h 1969-12-31 19:00:00.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/config/zip/zip-protos.h 2016-11-10 08:13:53.322577755 -0500
|
+++ gcc-6.2.0-zip/gcc/config/zip/zip-protos.h 2017-02-17 16:45:53.264117439 -0500
|
@@ -0,0 +1,80 @@
|
@@ -0,0 +1,82 @@
|
+////////////////////////////////////////////////////////////////////////////////
|
+////////////////////////////////////////////////////////////////////////////////
|
+//
|
+//
|
+// Filename: zip-protos.h
|
+// Filename: zip-protos.h
|
+//
|
+//
|
+// Project: Zip CPU backend for the GNU Compiler Collection
|
+// Project: Zip CPU backend for the GNU Compiler Collection
|
| Line 10997... |
Line 11028... |
+
|
+
|
+extern int zip_supported_condition(int c);
|
+extern int zip_supported_condition(int c);
|
+extern void zip_expand_prologue(void);
|
+extern void zip_expand_prologue(void);
|
+extern void zip_expand_epilogue(void);
|
+extern void zip_expand_epilogue(void);
|
+extern void zip_sibcall_epilogue(void);
|
+extern void zip_sibcall_epilogue(void);
|
|
+extern int zip_expand_movdi(rtx,rtx);
|
+extern int zip_expand_movsicc(rtx,rtx,rtx,rtx);
|
+extern int zip_expand_movsicc(rtx,rtx,rtx,rtx);
|
+extern int zip_initial_elimination_offset(int, int);
|
+extern int zip_initial_elimination_offset(int, int);
|
+extern void zip_print_operand(FILE *, rtx, int);
|
+extern void zip_print_operand(FILE *, rtx, int);
|
+extern void zip_print_operand_address(FILE *, rtx);
|
+extern void zip_print_operand_address(FILE *, rtx);
|
+extern enum reg_class zip_reg_class(int);
|
+extern enum reg_class zip_reg_class(int);
|
| Line 11025... |
Line 11057... |
+extern int zip_pd_imm_operand(rtx op);
|
+extern int zip_pd_imm_operand(rtx op);
|
+extern int zip_pd_mvimm_operand(rtx op);
|
+extern int zip_pd_mvimm_operand(rtx op);
|
+extern int zip_ct_const_address_operand(rtx op);
|
+extern int zip_ct_const_address_operand(rtx op);
|
+extern int zip_pd_const_address_operand(rtx op);
|
+extern int zip_pd_const_address_operand(rtx op);
|
+extern const char *zip_movsicc(rtx, rtx, rtx, rtx);
|
+extern const char *zip_movsicc(rtx, rtx, rtx, rtx);
|
+extern const char *zip_addsicc(rtx, rtx, rtx, rtx);
|
+extern const char *zip_addqics(rtx, rtx, rtx, rtx);
|
|
+extern const char *zip_cbranchdi(rtx, rtx, rtx, rtx);
|
+
|
+
|
+extern void zip_ifcvt_machdep_init(struct ce_if_block *ceinfo);
|
+extern void zip_ifcvt_machdep_init(struct ce_if_block *ceinfo);
|
+extern void zip_ifcvt_modify_cancel(struct ce_if_block *ceinfo);
|
+extern void zip_ifcvt_modify_cancel(struct ce_if_block *ceinfo);
|
+extern void zip_ifcvt_modify_final(struct ce_if_block *ceinfo);
|
+extern void zip_ifcvt_modify_final(struct ce_if_block *ceinfo);
|
+extern void zip_ifcvt_modify_tests(struct ce_if_block *ceinfo, rtx *true_expr, rtx *false_expr);
|
+extern void zip_ifcvt_modify_tests(struct ce_if_block *ceinfo, rtx *true_expr, rtx *false_expr);
|
+extern void zip_ifcvt_modify_insn(struct ce_if_block *ceinfo, rtx pattern, rtx_insn *insn);
|
+extern void zip_ifcvt_modify_insn(struct ce_if_block *ceinfo, rtx pattern, rtx_insn *insn);
|
+
|
+
|
+#endif
|
+#endif
|
+
|
+
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-sync.md gcc-5.3.0-zip/gcc/config/zip/zip-sync.md
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip-sync.md gcc-6.2.0-zip/gcc/config/zip/zip-sync.md
|
--- gcc-5.3.0-original/gcc/config/zip/zip-sync.md 1969-12-31 19:00:00.000000000 -0500
|
--- gcc-6.2.0/gcc/config/zip/zip-sync.md 1969-12-31 19:00:00.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/config/zip/zip-sync.md 2016-11-10 06:58:36.795045234 -0500
|
+++ gcc-6.2.0-zip/gcc/config/zip/zip-sync.md 2017-02-22 18:03:26.740198685 -0500
|
@@ -0,0 +1,303 @@
|
@@ -0,0 +1,415 @@
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;
|
+;;
|
+;; Filename: zip-sync.md
|
+;; Filename: zip-sync.md
|
+;;
|
+;;
|
+;; Project: Zip CPU -- a small, lightweight, RISC CPU soft core
|
+;; Project: Zip CPU -- a small, lightweight, RISC CPU soft core
|
| Line 11054... |
Line 11087... |
+;; Creator: Dan Gisselquist, Ph.D.
|
+;; Creator: Dan Gisselquist, Ph.D.
|
+;; Gisselquist Technology, LLC
|
+;; Gisselquist Technology, LLC
|
+;;
|
+;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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+;;
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+;;
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+;; Copyright (C) 2015, Gisselquist Technology, LLC
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+;; Copyright (C) 2015,2017, Gisselquist Technology, LLC
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+;;
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+;;
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+;; This program is free software (firmware): you can redistribute it and/or
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+;; This program is free software (firmware): you can redistribute it and/or
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+;; modify it under the terms of the GNU General Public License as published
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+;; modify it under the terms of the GNU General Public License as published
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+;; by the Free Software Foundation, either version 3 of the License, or (at
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+;; by the Free Software Foundation, either version 3 of the License, or (at
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+;; your option) any later version.
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+;; your option) any later version.
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| Line 11087... |
Line 11120... |
+;
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+;
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+;
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+;
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+; First, the basic atomic_ operators, add, sub, ior, and, and xor
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+; First, the basic atomic_ operators, add, sub, ior, and, and xor
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+;
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+;
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+(define_insn "atomic_addsi"
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+(define_insn "atomic_addsi"
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+ [(set (match_operand:SI 0 "zip_memory_operand_p" "+Q")
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+ [(set (match_operand:SI 0 "memory_operand" "+Q")
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+ (plus:SI (match_dup 0)
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+ (plus:SI (match_dup 0)
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+ (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
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+ (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
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+ (const (match_operand 2 "" "")) ; Memory model used
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+ (match_operand 2 "const_int_operand" "") ; Memory model used
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+ (clobber (match_scratch:SI 3 "=r")) ; Scratch register
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+ (clobber (match_scratch:SI 3 "=r")) ; Scratch register
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+ (clobber (reg:CC CC_REG))]
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+ (clobber (reg:CC CC_REG))]
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+ "(ZIP_ATOMIC)"
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+ "(ZIP_ATOMIC)"
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+ "LOCK\n\tLOD %0,%3\n\tADD %1,%3\n\tSTO %3,%0\n"
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+ "LOCK\n\tLW %0,%3\n\tADD %1,%3\n\tSW %3,%0"
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+ [(set_attr "predicable" "no")])
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+ [(set_attr "predicable" "no")])
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+(define_insn "atomic_subsi"
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+(define_insn "atomic_subsi"
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+ [(set (match_operand:SI 0 "zip_memory_operand_p" "+Q")
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+ [(set (match_operand:SI 0 "memory_operand" "+Q")
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+ (minus:SI (match_dup 0)
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+ (minus:SI (match_dup 0)
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+ (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
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+ (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
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+ (const (match_operand 2 "" "")) ; Memory model used
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+ (match_operand 2 "const_int_operand" "") ; Memory model used
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+ (clobber (match_scratch:SI 3 "=r")) ; Scratch register
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+ (clobber (match_scratch:SI 3 "=r")) ; Scratch register
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+ (clobber (reg:CC CC_REG))]
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+ (clobber (reg:CC CC_REG))]
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+ "(ZIP_ATOMIC)"
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+ "(ZIP_ATOMIC)"
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+ "LOCK\n\tLOD %0,%3\n\tSUB %1,%3\n\tSTO %3,%0\n"
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+ "LOCK\n\tLW %0,%3\n\tSUB %1,%3\n\tSW %3,%0"
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+ [(set_attr "predicable" "no")])
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+ [(set_attr "predicable" "no")])
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+(define_insn "atomic_iorsi"
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+(define_insn "atomic_iorsi"
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+ [(set (match_operand:SI 0 "zip_memory_operand_p" "+Q")
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+ [(set (match_operand:SI 0 "memory_operand" "+Q")
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+ (ior:SI (match_dup 0)
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+ (ior:SI (match_dup 0)
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+ (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
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+ (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
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+ (const (match_operand 2 "" "")) ; Memory model used
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+ (match_operand 2 "const_int_operand" "") ; Memory model used
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+ (clobber (match_scratch:SI 3 "=r")) ; Scratch register
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+ (clobber (match_scratch:SI 3 "=r")) ; Scratch register
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+ (clobber (reg:CC CC_REG))]
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+ (clobber (reg:CC CC_REG))]
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+ "(ZIP_ATOMIC)"
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+ "(ZIP_ATOMIC)"
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+ "LOCK\n\tLOD %0,%3\n\tOR %1,%3\n\tSTO %3,%0\n"
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+ "LOCK\n\tLW %0,%3\n\tOR %1,%3\n\tSW %3,%0"
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+ [(set_attr "predicable" "no")])
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+ [(set_attr "predicable" "no")])
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+(define_insn "atomic_andsi"
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+(define_expand "atomic_andsi"
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+ [(set (match_operand:SI 0 "zip_memory_operand_p" "+Q")
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+ [(match_operand:SI 0 "memory_operand" "+Q")
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+ (match_operand:SI 1 "zip_opb_single_operand_p" "rO")
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+ (match_operand 2 "" "") ; Memory model used
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+ (clobber (reg:CC CC_REG))]
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+ "(ZIP_ATOMIC)"
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+ {
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+ emit_insn(gen_reissue_atomic_andsi(operands[0], operands[1]));
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+ DONE;
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+ })
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+(define_insn "reissue_atomic_andsi"
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+ [(set (match_operand:SI 0 "memory_operand" "+Q")
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+ (and:SI (match_dup 0)
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+ (and:SI (match_dup 0)
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+ (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
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+ (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
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+ (const (match_operand 2 "" "")) ; Memory model used
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+ (clobber (match_scratch:SI 2 "=r")) ; Scratch register
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+ (clobber (match_scratch:SI 3 "=r")) ; Scratch register
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+ (clobber (reg:CC CC_REG))]
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+ (clobber (reg:CC CC_REG))]
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+ "(ZIP_ATOMIC)"
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+ "(ZIP_ATOMIC)"
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+ "LOCK\n\tLOD %0,%3\n\tAND %1,%3\n\tSTO %3,%0\n"
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+ "LOCK\n\tLW %0,%2\n\tAND %1,%2\n\tSW %2,%0"
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+ [(set_attr "predicable" "no")])
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+ [(set_attr "predicable" "no")])
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+(define_insn "atomic_xorsi"
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+(define_expand "atomic_xorsi"
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+ [(set (match_operand:SI 0 "zip_memory_operand_p" "+Q")
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+ [(match_operand:SI 0 "memory_operand" "+Q")
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+ (match_operand:SI 1 "zip_opb_single_operand_p" "rO")
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+ (match_operand 2 "" "") ; Memory model used
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+ (clobber (reg:CC CC_REG))]
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+ "(ZIP_ATOMIC)"
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+ {
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+ emit_insn(gen_reissue_atomic_xorsi(operands[0], operands[1]));
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+ DONE;
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+ })
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+(define_insn "reissue_atomic_xorsi"
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+ [(set (match_operand:SI 0 "memory_operand" "+Q")
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+ (xor:SI (match_dup 0)
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+ (xor:SI (match_dup 0)
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+ (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
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+ (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
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+ (const (match_operand 2 "" "")) ; Memory model used
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+ (clobber (match_scratch:SI 2 "=r")) ; Scratch register
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+ (clobber (match_scratch:SI 3 "=r")) ; Scratch register
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+ (clobber (reg:CC CC_REG))]
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+ (clobber (reg:CC CC_REG))]
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+ "(ZIP_ATOMIC)"
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+ "(ZIP_ATOMIC)"
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+ "LOCK\n\tLOD %0,%3\n\tXOR %1,%3\n\tSTO %3,%0\n"
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+ "LOCK\n\tLW %0,%2\n\tXOR %1,%2\n\tSW %2,%0"
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+ [(set_attr "predicable" "no")])
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+ [(set_attr "predicable" "no")])
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+;
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+;
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+;
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+;
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+; Given how the ZipCPU is put together, all LODs and STOs are atomic. Hence,
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+; Given how the ZipCPU is put together, all SI LODs and STOs are atomic. DI
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+; we just expand these operators so that they can be used by the other already
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+; loads and stores need the LOCK command, to keep from breaking within them.
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+; existent LOD/STO RTL operators.
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+; Further, GCC expects that anything <= the word size can use a normal load
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+; or store instruction. Hence we don't need anything but the DI load and
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+; stores.
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+;
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+;
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+(define_expand "atomic_loadsi"
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+(define_insn "atomic_loaddi"
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+ [(set (match_operand:SI 0 "register_operand" "=r")
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+ [(set (match_operand:DI 0 "register_operand" "=r")
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+ (match_operand:SI 1 "zip_memory_operand_p" "Q"))])
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+ (match_operand:DI 1 "memory_operand" "Q"))
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+(define_expand "atomic_loaddi"
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+ (match_operand 2 "const_int_operand" "")]
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+ [(set (match_operand:SI 0 "register_operand" "=r")
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+ "(ZIP_HAS_DI)&&(ZIP_ATOMIC)"
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+ (match_operand:SI 1 "zip_memory_operand_p" "Q"))])
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+ "LOCK\n\tLW %1,%H0\t; Atomic Load:DI\n\tLW 4+%1,%L0"
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+(define_expand "atomic_storesi"
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+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
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+ [(set (match_operand:SI 0 "zip_memory_operand_p" "=Q")
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+;
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+ (match_operand:DI 1 "register_operand" "r"))])
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+(define_insn "atomic_storedi"
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+(define_expand "atomic_storedi"
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+ [(set (match_operand:DI 0 "memory_operand" "=Q")
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+ [(set (match_operand:SI 0 "zip_memory_operand_p" "=Q")
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+ (match_operand:DI 1 "register_operand" "r"))
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+ (match_operand:DI 1 "register_operand" "r"))])
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+ (match_operand 2 "const_int_operand" "")]
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+ "(ZIP_HAS_DI)&&(ZIP_ATOMIC)"
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+ "LOCK\n\tSW %H1,%0\t; Atomic Store:DI\n\tSW %L1,4+%0"
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+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
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+;
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+;
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+;
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+;
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+;
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+;
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+;
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+;
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+(define_insn "atomic_exchangesi"
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+(define_insn "atomic_exchangesi"
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+ [(set (match_operand:SI 0 "register_operand" "=r")
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+ [(set (match_operand:SI 0 "register_operand" "=r")
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+ (match_operand:SI 1 "zip_memory_operand_p" "+Q"))
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+ (match_operand:SI 1 "memory_operand" "+Q"))
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+ (set (match_dup 1) (match_operand:SI 2 "register_operand" "r"))
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+ (set (match_dup 1) (match_operand:SI 2 "register_operand" "r"))
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+ ; (match_operand 3 "" "") ; Memory model used
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+ (match_operand 3 "const_int_operand" "")]
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+ ]
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+ "(ZIP_ATOMIC)"
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+ "(ZIP_ATOMIC)"
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+ "LOCK\n\tLOD %1,%0\n\tSTO %2,%1\n"
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+ "LOCK\n\tLW %1,%0\n\tSW %2,%1"
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+ [(set_attr "predicable" "no")])
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+ [(set_attr "predicable" "no")])
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+;
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+;
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+;
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+;
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+;
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+;
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+; Here's another set of the atomic operators, this time those that leave their
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+; Here's another set of the atomic operators, this time those that leave their
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+; result in operand zero.
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+; result in operand zero.
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+;
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+;
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+(define_insn "atomic_add_fetchsi"
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+(define_expand "atomic_add_fetchsi"
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+ [(match_operand:SI 0 "register_operand" "=r")
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+ (match_operand:SI 1 "memory_operand" "+Q")
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+ (match_operand:SI 2 "zip_opb_single_operand_p" "rO")
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+ (match_operand 3 "const_int_operand" "") ;// Memory model used
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+ (clobber (reg:CC CC_REG))]
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+ "(ZIP_ATOMIC)"
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+ {
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+ emit_insn(gen_reissue_atomic_add_fetchsi(operands[0],
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+ operands[1], operands[2]));
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+ DONE;
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+ })
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+(define_insn "reissue_atomic_add_fetchsi"
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+ [(set (match_operand:SI 0 "register_operand" "=r")
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+ [(set (match_operand:SI 0 "register_operand" "=r")
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+ (plus:SI (match_operand:SI 1 "zip_memory_operand_p" "+Q")
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+ (plus:SI (match_operand:SI 1 "memory_operand" "+Q")
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+ (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
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+ (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
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+ (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))
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+ (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))
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+ ; (match_operand 3 "" "") ; Memory model used
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+ (clobber (reg:CC CC_REG))]
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+ (clobber (reg:CC CC_REG))]
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+ "(ZIP_ATOMIC)"
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+ "(ZIP_ATOMIC)"
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+ "LOCK\n\tLOD %1,%0\n\tADD %2,%0\n\tSTO %0,%1\n"
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+ "LOCK\n\tLW %1,%0\n\tADD %2,%0\n\tSW %0,%1"
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+ [(set_attr "predicable" "no")])
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+ [(set_attr "predicable" "no")])
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+(define_insn "atomic_sub_fetchsi"
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+(define_expand "atomic_sub_fetchsi"
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+ [(match_operand:SI 0 "register_operand" "=r")
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+ (match_operand:SI 1 "memory_operand" "+Q")
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+ (match_operand:SI 2 "zip_opb_single_operand_p" "rO")
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+ (match_operand 3 "const_int_operand" "")
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+ (clobber (reg:CC CC_REG))]
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+ "(ZIP_ATOMIC)"
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+ {
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+ emit_insn(gen_reissue_atomic_sub_fetchsi(
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+ operands[0], operands[1], operands[2]));
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+ DONE;
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+ })
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+(define_insn "reissue_atomic_sub_fetchsi"
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+ [(set (match_operand:SI 0 "register_operand" "=r")
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+ [(set (match_operand:SI 0 "register_operand" "=r")
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+ (minus:SI (match_operand:SI 1 "zip_memory_operand_p" "+Q")
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+ (minus:SI (match_operand:SI 1 "memory_operand" "+Q")
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+ (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
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+ (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
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+ (set (match_dup 1) (minus:SI (match_dup 1) (match_dup 2)))
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+ (set (match_dup 1) (minus:SI (match_dup 1) (match_dup 2)))
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+ (clobber (reg:CC CC_REG))]
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+ (clobber (reg:CC CC_REG))]
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+ "(ZIP_ATOMIC)"
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+ "(ZIP_ATOMIC)"
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+ "LOCK\n\tLOD %1,%0\n\tSUB %2,%0\n\tSTO %0,%1\n"
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+ "LOCK\n\tLW %1,%0\n\tSUB %2,%0\n\tSW %0,%1"
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+ [(set_attr "predicable" "no")])
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+ [(set_attr "predicable" "no")])
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+(define_insn "atomic_or_fetchsi"
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+(define_expand "atomic_or_fetchsi"
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+ [(match_operand:SI 0 "register_operand" "=r")
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+ (match_operand:SI 1 "memory_operand" "+Q")
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+ (match_operand:SI 2 "zip_opb_single_operand_p" "rO")
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+ (match_operand 3 "const_int_operand" "")
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+ (clobber (reg:CC CC_REG))]
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+ "(ZIP_ATOMIC)"
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+ {
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+ emit_insn(gen_reissue_atomic_or_fetchsi(
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+ operands[0], operands[1], operands[2]));
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+ DONE;
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+ })
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+(define_insn "reissue_atomic_or_fetchsi"
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+ [(set (match_operand:SI 0 "register_operand" "=r")
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+ [(set (match_operand:SI 0 "register_operand" "=r")
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+ (ior:SI (match_operand:SI 1 "zip_memory_operand_p" "+Q")
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+ (ior:SI (match_operand:SI 1 "memory_operand" "+Q")
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+ (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
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+ (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
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+ (set (match_dup 1) (ior:SI (match_dup 1) (match_dup 2)))
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+ (set (match_dup 1) (ior:SI (match_dup 1) (match_dup 2)))
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+ (clobber (reg:CC CC_REG))]
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+ (clobber (reg:CC CC_REG))]
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+ "(ZIP_ATOMIC)"
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+ "(ZIP_ATOMIC)"
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+ "LOCK\n\tLOD %1,%0\n\tOR %2,%0\n\tSTO %0,%1\n"
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+ "LOCK\n\tLW %1,%0\n\tOR %2,%0\n\tSW %0,%1"
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+ [(set_attr "predicable" "no")])
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+ [(set_attr "predicable" "no")])
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+(define_insn "atomic_and_fetchsi"
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+(define_expand "atomic_and_fetchsi"
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+ [(match_operand:SI 0 "register_operand" "=r")
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+ (match_operand:SI 1 "memory_operand" "+Q")
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+ (match_operand:SI 2 "zip_opb_single_operand_p" "rO")
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+ (match_operand 3 "const_int_operand" "")
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+ (clobber (reg:CC CC_REG))]
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+ "(ZIP_ATOMIC)"
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+ {
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+ emit_insn(gen_reissue_atomic_and_fetchsi(
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+ operands[0], operands[1], operands[2]));
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+ DONE;
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+ })
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+(define_insn "reissue_atomic_and_fetchsi"
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+ [(set (match_operand:SI 0 "register_operand" "=r")
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+ [(set (match_operand:SI 0 "register_operand" "=r")
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+ (and:SI (match_operand:SI 1 "zip_memory_operand_p" "+Q")
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+ (and:SI (match_operand:SI 1 "memory_operand" "+Q")
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+ (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
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+ (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
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+ (set (match_dup 1) (and:SI (match_dup 1) (match_dup 2)))
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+ (set (match_dup 1) (and:SI (match_dup 1) (match_dup 2)))
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+ (clobber (reg:CC CC_REG))]
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+ (clobber (reg:CC CC_REG))]
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+ "(ZIP_ATOMIC)"
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+ "(ZIP_ATOMIC)"
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+ "LOCK\n\tLOD %1,%0\n\tAND %2,%0\n\tSTO %0,%1\n"
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+ "LOCK\n\tLW %1,%0\n\tAND %2,%0\n\tSW %0,%1"
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+ [(set_attr "predicable" "no")])
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+ [(set_attr "predicable" "no")])
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+(define_insn "atomic_xor_fetchsi"
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+(define_expand "atomic_xor_fetchsi"
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+ [(match_operand:SI 0 "register_operand" "=r")
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+ (match_operand:SI 1 "memory_operand" "+Q")
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+ (match_operand:SI 2 "zip_opb_single_operand_p" "rO")
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+ (match_operand 3 "const_int_operand" "") ;// Memory model
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+ (clobber (reg:CC CC_REG))]
|
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+ "(ZIP_ATOMIC)"
|
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+ {
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+ emit_insn(gen_reissue_atomic_xor_fetchsi(
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|
+ operands[0], operands[1], operands[2]));
|
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+ DONE;
|
|
+ })
|
|
+(define_insn "reissue_atomic_xor_fetchsi"
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+ [(set (match_operand:SI 0 "register_operand" "=r")
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+ [(set (match_operand:SI 0 "register_operand" "=r")
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+ (xor:SI (match_operand:SI 1 "zip_memory_operand_p" "+Q")
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+ (xor:SI (match_operand:SI 1 "memory_operand" "+Q")
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+ (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
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+ (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
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+ (set (match_dup 1) (xor:SI (match_dup 1) (match_dup 2)))
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+ (set (match_dup 1) (xor:SI (match_dup 1) (match_dup 2)))
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+ (clobber (reg:CC CC_REG))]
|
+ (clobber (reg:CC CC_REG))]
|
+ "(ZIP_ATOMIC)"
|
+ "(ZIP_ATOMIC)"
|
+ "LOCK\n\tLOD %1,%0\n\tXOR %2,%0\n\tSTO %0,%1\n"
|
+ "LOCK\n\tLW %1,%0\n\tXOR %2,%0\n\tSW %0,%1"
|
+ [(set_attr "predicable" "no")])
|
+ [(set_attr "predicable" "no")])
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+(define_insn "atomic_fetch_addsi"
|
+(define_expand "atomic_fetch_addsi"
|
+ [(set (match_operand:SI 1 "zip_memory_operand_p" "+Q")
|
+ [(set (match_operand:SI 1 "memory_operand" "+Q")
|
+ (plus:SI (match_dup 1)
|
+ (plus:SI (match_dup 1)
|
+ (match_operand:SI 2 "register_operand" "=r")))
|
+ (match_operand:SI 2 "register_operand" "=r")))
|
+ (set (match_operand:SI 0 "register_operand" "=r")
|
+ (set (match_operand:SI 0 "register_operand" "=r")
|
+ (match_dup 1))
|
+ (match_dup 1))
|
+ (set (match_dup 2) (plus:SI (match_dup 1) (match_dup 2)))
|
+ (set (match_dup 2) (plus:SI (match_dup 1) (match_dup 2)))
|
+ ; (match_operand 3 "" "") ; Memory model used
|
+ (match_operand 3 "const_int_operand" "") ; Memory model used
|
+ (clobber (reg:CC CC_REG))]
|
+ (clobber (reg:CC CC_REG))]
|
+ "(ZIP_ATOMIC)"
|
+ "(ZIP_ATOMIC)"
|
+ "LOCK\n\tLOD %1,%0\n\tADD %0,%2\n\tSTO %2,%1\n"
|
+ {
|
|
+ emit_insn(gen_reissue_atomic_fetch_addsi(
|
|
+ operands[0], operands[1], operands[2]));
|
|
+ DONE;
|
|
+ })
|
|
+(define_insn "reissue_atomic_fetch_addsi"
|
|
+ [(set (match_operand:SI 1 "memory_operand" "+Q")
|
|
+ (plus:SI (match_dup 1)
|
|
+ (match_operand:SI 2 "register_operand" "=r")))
|
|
+ (set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (match_dup 1))
|
|
+ (set (match_dup 2) (plus:SI (match_dup 1) (match_dup 2)))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ "(ZIP_ATOMIC)"
|
|
+ "LOCK\n\tLW %1,%0\n\tADD %0,%2\n\tSW %2,%1"
|
|
+ [(set_attr "predicable" "no")])
|
|
+(define_expand "atomic_fetch_subsi"
|
|
+ [(match_operand:SI 0 "register_operand" "=r")
|
|
+ (match_operand:SI 1 "memory_operand" "+Q")
|
|
+ (match_operand:SI 2 "zip_opb_single_operand_p" "rO")
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ "(ZIP_ATOMIC)"
|
|
+ {
|
|
+ emit_insn(gen_reissue_atomic_fetch_subsi(
|
|
+ operands[0], operands[1], operands[2]));
|
|
+ DONE;
|
|
+ })
|
|
+(define_insn "reissue_atomic_fetch_subsi"
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (minus:SI (match_operand:SI 1 "memory_operand" "+Q")
|
|
+ (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
|
|
+ (set (match_dup 1) (minus:SI (match_dup 1) (match_dup 2)))
|
|
+ (clobber (match_scratch:SI 3 "=r")) ; Scratch register
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ "(ZIP_ATOMIC)"
|
|
+ "NEG %2,%3\n\tLOCK\n\tLW %1,%0\n\tADD %0,%3\n\tSW %3,%1"
|
+ [(set_attr "predicable" "no")])
|
+ [(set_attr "predicable" "no")])
|
+;(define_insn "atomic_fetch_subsi"
|
|
+; [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+; (minus:SI (match_operand:SI 1 "zip_memory_operand_p" "+Q")
|
|
+; (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
|
|
+; (set (match_dup 1) (minus:SI (match_dup 1) (match_dup 2)))
|
|
+; (clobber (reg:CC CC_REG))]
|
|
+; "(ZIP_ATOMIC)"
|
|
+;
|
|
+; HERE WE HAVE A PROBLEM ... swapping the arguments does not work for a
|
|
+; subtract. It creates the SUBR (subtract reverse) instruction, which is not
|
|
+; what the RTL names is supposed to capture. Hence ... we cannot do this one.
|
|
+; If we could do two ALU instructions during the LOCK, then we might make
|
|
+; this work--but LOCK only provides for a single ALU instruction.
|
|
+;
|
|
+; "LOCK\n\tLOD %1,%0\n\tSUB %2,%0\n\tSTO %0,%1\n"
|
|
+; "LOCK\n\tLOD %1,%0\n\tSUB %0,%2\n\tSTO %2,%1\n"
|
|
+; [(set_attr "predicable" "no")])
|
|
+(define_insn "atomic_fetch_orsi"
|
+(define_insn "atomic_fetch_orsi"
|
+ [(set (match_operand:SI 1 "zip_memory_operand_p" "+Q")
|
+ [(set (match_operand:SI 1 "memory_operand" "+Q")
|
+ (ior:SI (match_dup 1)
|
+ (ior:SI (match_dup 1)
|
+ (match_operand:SI 2 "register_operand" "=r")))
|
+ (match_operand:SI 2 "register_operand" "=r")))
|
+ (set (match_operand:SI 0 "register_operand" "=r")
|
+ (set (match_operand:SI 0 "register_operand" "=r")
|
+ (match_dup 1))
|
+ (match_dup 1))
|
+ (set (match_dup 2) (ior:SI (match_dup 1) (match_dup 2)))
|
+ (set (match_dup 2) (ior:SI (match_dup 1) (match_dup 2)))
|
+ ; (match_operand 3 "" "") ; Memory model used
|
+ (match_operand 3 "const_int_operand" "") ; Memory model used
|
+ (clobber (reg:CC CC_REG))]
|
+ (clobber (reg:CC CC_REG))]
|
+ "(ZIP_ATOMIC)"
|
+ "(ZIP_ATOMIC)"
|
+ "LOCK\n\tLOD %1,%0\n\tOR %0,%2\n\tSTO %2,%1\n"
|
+ "LOCK\n\tLW %1,%0\n\tOR %0,%2\n\tSW %2,%1"
|
+ [(set_attr "predicable" "no")])
|
+ [(set_attr "predicable" "no")])
|
+(define_insn "atomic_fetch_andsi"
|
+(define_insn "atomic_fetch_andsi"
|
+ [(set (match_operand:SI 1 "zip_memory_operand_p" "+Q")
|
+ [(set (match_operand:SI 1 "memory_operand" "+Q")
|
+ (and:SI (match_dup 1)
|
+ (and:SI (match_dup 1)
|
+ (match_operand:SI 2 "register_operand" "=r")))
|
+ (match_operand:SI 2 "register_operand" "=r")))
|
+ (set (match_operand:SI 0 "register_operand" "=r")
|
+ (set (match_operand:SI 0 "register_operand" "=r")
|
+ (match_dup 1))
|
+ (match_dup 1))
|
+ (set (match_dup 2) (and:SI (match_dup 1) (match_dup 2)))
|
+ (set (match_dup 2) (and:SI (match_dup 1) (match_dup 2)))
|
+ ; (match_operand 3 "" "") ; Memory model used
|
+ (match_operand 3 "const_int_operand" "") ; Memory model used
|
+ (clobber (reg:CC CC_REG))]
|
+ (clobber (reg:CC CC_REG))]
|
+ "(ZIP_ATOMIC)"
|
+ "(ZIP_ATOMIC)"
|
+ "LOCK\n\tLOD %1,%0\n\tAND %0,%2\n\tSTO %2,%1\n"
|
+ "LOCK\n\tLW %1,%0\n\tAND %0,%2\n\tSW %2,%1"
|
+ [(set_attr "predicable" "no")])
|
+ [(set_attr "predicable" "no")])
|
+(define_insn "atomic_fetch_xorsi"
|
+(define_insn "atomic_fetch_xorsi"
|
+ [(set (match_operand:SI 1 "zip_memory_operand_p" "+Q")
|
+ [(set (match_operand:SI 1 "memory_operand" "+Q")
|
+ (xor:SI (match_dup 1)
|
+ (xor:SI (match_dup 1)
|
+ (match_operand:SI 2 "register_operand" "=r")))
|
+ (match_operand:SI 2 "register_operand" "=r")))
|
+ (set (match_operand:SI 0 "register_operand" "=r")
|
+ (set (match_operand:SI 0 "register_operand" "=r")
|
+ (match_dup 1))
|
+ (match_dup 1))
|
+ (set (match_dup 2) (xor:SI (match_dup 1) (match_dup 2)))
|
+ (set (match_dup 2) (xor:SI (match_dup 1) (match_dup 2)))
|
+ ; (match_operand 3 "" "") ; Memory model used
|
+ (match_operand 3 "const_int_operand" "") ; Memory model used
|
+ (clobber (reg:CC CC_REG))]
|
+ (clobber (reg:CC CC_REG))]
|
+ "(ZIP_ATOMIC)"
|
+ "(ZIP_ATOMIC)"
|
+ "LOCK\n\tLOD %1,%0\n\tXOR %0,%2\n\tSTO %2,%1\n"
|
+ "LOCK\n\tLW %1,%0\n\tXOR %0,%2\n\tSW %2,%1"
|
+ [(set_attr "predicable" "no")])
|
+ [(set_attr "predicable" "no")])
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+(define_insn "atomic_test_and_set"
|
+(define_insn "atomic_test_and_set"
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
+ (match_operand:SI 1 "zip_memory_operand_p" "+Q"))
|
+ (zero_extend:SI
|
+ (set (match_dup 1)
|
+ (match_operand:QI 1 "memory_operand" "+Q")))
|
+ (if_then_else
|
+ (set (match_dup 1) (const_int 1))
|
+ (eq (match_dup 1)
|
+ (match_operand 2 "const_int_operand" "") ; Memory model used
|
+ (const_int 0))
|
+ (clobber (match_scratch:SI 3 "=r"))] ; Scratch register
|
+ (const_int 1)
|
|
+ (match_dup 1)))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 1) (const_int 0)))
|
|
+ (set (match_scratch:SI 3) (const_int 1))
|
|
+ (const (match_operand 2 "" ""))] ; Memory model used
|
|
+ "(ZIP_ATOMIC)"
|
+ "(ZIP_ATOMIC)"
|
+ "LDI 1,%3
|
+ "LDI 1,%3
|
+ LOCK
|
+ LOCK
|
+ LOD %1,%0
|
+ LB %1,%0
|
+ TST %0
|
+ SB %3,%1"
|
+ STO.Z %3,%1\n"
|
|
+ [(set_attr "predicable" "no")])
|
+ [(set_attr "predicable" "no")])
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+(define_insn "atomic_compare_and_swapsi"
|
+(define_expand "atomic_compare_and_swapsi"
|
|
+ [(match_operand:SI 0 "register_operand" "=r") ;; bool output
|
|
+ (match_operand:SI 1 "register_operand" "=r") ;; val output
|
|
+ (match_operand:SI 2 "memory_operand" "+Q") ;; memory
|
|
+ (match_operand:SI 3 "zip_opb_single_operand_p" "rO") ;; Expected
|
|
+ (match_operand:SI 4 "register_operand" "r") ;; Desired
|
|
+ (match_operand 5 "const_int_operand" "") ; is_weak
|
|
+ (match_operand 6 "const_int_operand" "") ; mem model on success
|
|
+ (match_operand 7 "const_int_operand" "") ; mem model on failure
|
|
+ ]
|
|
+ "(ZIP_ATOMIC)"
|
|
+ {
|
|
+ emit_insn(gen_reissue_atomic_compare_and_swapsi(
|
|
+ operands[0], operands[1],
|
|
+ operands[2], operands[3],
|
|
+ operands[4]));
|
|
+ DONE;
|
|
+ })
|
|
+
|
|
+(define_insn "reissue_atomic_compare_and_swapsi"
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
+ (if_then_else
|
+ (if_then_else
|
+ (eq (match_operand:SI 2 "zip_memory_operand_p" "+Q")
|
+ (eq (match_operand:SI 2 "memory_operand" "+Q")
|
+ (match_operand:SI 3 "zip_opb_single_operand_p" "rO"))
|
+ (match_operand:SI 3 "zip_opb_single_operand_p" "rO"))
|
+ (const_int 1)
|
+ (const_int 1)
|
+ (const_int 0)))
|
+ (const_int 0)))
|
+ (set (match_operand:SI 1 "register_operand" "=r") (match_dup 2))
|
+ (set (match_operand:SI 1 "register_operand" "=r") (match_dup 2))
|
+ (set (match_dup 2) (if_then_else
|
+ (set (match_dup 2) (if_then_else
|
| Line 11329... |
Line 11474... |
+ (match_operand:SI 4 "register_operand" "r")
|
+ (match_operand:SI 4 "register_operand" "r")
|
+ (match_dup 0)))]
|
+ (match_dup 0)))]
|
+ "(ZIP_ATOMIC)"
|
+ "(ZIP_ATOMIC)"
|
+ "CLR %0
|
+ "CLR %0
|
+ LOCK
|
+ LOCK
|
+ LOD %2,%1
|
+ LW %2,%1
|
+ CMP %3,%1
|
+ CMP %3,%1
|
+ STO.Z %4,%1
|
+ SW %4,%1
|
+ LDI.Z 1,%0"
|
+ LDI.Z 1,%0"
|
+ [(set_attr "predicable" "no")])
|
+ [(set_attr "predicable" "no")])
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+; STILL MISSING:
|
+; STILL MISSING:
|
+;
|
+;
|
+; deprecated sync_* atomic functions
|
+; deprecated sync_* atomic functions
|
+;
|
+;
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config.gcc gcc-5.3.0-zip/gcc/config.gcc
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config.gcc gcc-6.2.0-zip/gcc/config.gcc
|
--- gcc-5.3.0-original/gcc/config.gcc 2015-09-10 10:17:53.000000000 -0400
|
--- gcc-6.2.0/gcc/config.gcc 2016-06-08 09:34:25.000000000 -0400
|
+++ gcc-5.3.0-zip/gcc/config.gcc 2016-02-14 00:53:37.389411987 -0500
|
+++ gcc-6.2.0-zip/gcc/config.gcc 2016-12-31 16:41:06.258602919 -0500
|
@@ -479,6 +479,10 @@
|
@@ -493,6 +493,10 @@
|
tilepro*-*-*)
|
tilepro*-*-*)
|
cpu_type=tilepro
|
cpu_type=tilepro
|
;;
|
;;
|
+zip*)
|
+zip*)
|
+ cpu_type=zip
|
+ cpu_type=zip
|
+ tmake_file=zip/t-zip
|
+ tmake_file=zip/t-zip
|
+ ;;
|
+ ;;
|
esac
|
esac
|
|
|
tm_file=${cpu_type}/${cpu_type}.h
|
tm_file=${cpu_type}/${cpu_type}.h
|
@@ -2972,6 +2976,15 @@
|
@@ -3042,6 +3046,11 @@
|
c_target_objs="m32c-pragma.o"
|
c_target_objs="m32c-pragma.o"
|
cxx_target_objs="m32c-pragma.o"
|
cxx_target_objs="m32c-pragma.o"
|
;;
|
;;
|
+zip-*-netbsd*)
|
|
+ tm_file="${tm_file} elfos.h netbsd.h netbsd-elf.h zip/netbsd.h"
|
|
+ tmake_file="${tmake_file} zip/t-zip"
|
|
+ ;;
|
|
+zip*)
|
+zip*)
|
+ target_has_targetm_common=yes
|
+ target_has_targetm_common=yes
|
+ tm_file="elfos.h newlib-stdint.h ${tm_file}"
|
+ tm_file="elfos.h newlib-stdint.h ${tm_file}"
|
+ tmake_file="${tmake_file} zip/t-zip"
|
+ tmake_file="${tmake_file} zip/t-zip"
|
+ ;;
|
+ ;;
|
*)
|
*)
|
echo "*** Configuration ${target} not supported" 1>&2
|
echo "*** Configuration ${target} not supported" 1>&2
|
exit 1
|
exit 1
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/cse.c gcc-5.3.0-zip/gcc/cse.c
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/cse.c gcc-6.2.0-zip/gcc/cse.c
|
--- gcc-5.3.0-original/gcc/cse.c 2015-02-03 15:41:38.000000000 -0500
|
--- gcc-6.2.0/gcc/cse.c 2016-02-04 04:56:13.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/cse.c 2016-05-04 11:07:38.874831028 -0400
|
+++ gcc-6.2.0-zip/gcc/cse.c 2017-02-06 21:46:10.525049918 -0500
|
@@ -70,6 +70,7 @@
|
@@ -42,6 +42,16 @@
|
#include "dbgcnt.h"
|
#include "dbgcnt.h"
|
#include "rtl-iter.h"
|
#include "rtl-iter.h"
|
|
|
+
|
+
|
/* The basic idea of common subexpression elimination is to go
|
|
through the code, keeping a record of expressions that would
|
|
have the same value at the current scan point, and replacing
|
|
@@ -634,6 +635,16 @@
|
|
|
|
/* Nonzero if X has the form (PLUS frame-pointer integer). */
|
|
|
|
+// #define DO_ZIP_DEBUGS
|
+// #define DO_ZIP_DEBUGS
|
+#ifdef DO_ZIP_DEBUGS
|
+#ifdef DO_ZIP_DEBUGS
|
+#include <stdio.h>
|
+#include <stdio.h>
|
|
+#define ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s;%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
|
+extern void zip_debug_rtx(const_rtx);
|
+extern void zip_debug_rtx(const_rtx);
|
+extern void zip_debug_rtx_pfx(char *, const_rtx);
|
|
+#define ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s\n", STR); zip_debug_rtx(RTX); } while(0)
|
|
+#else
|
+#else
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
+#endif
|
+#endif
|
+
|
+
|
static bool
|
#ifndef LOAD_EXTEND_OP
|
fixed_base_plus_p (rtx x)
|
#define LOAD_EXTEND_OP(M) UNKNOWN
|
{
|
#endif
|
@@ -2898,6 +2909,7 @@
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/defaults.h gcc-6.2.0-zip/gcc/defaults.h
|
validate_canon_reg (&XVECEXP (x, i, j), insn);
|
--- gcc-6.2.0/gcc/defaults.h 2016-01-04 09:30:50.000000000 -0500
|
}
|
+++ gcc-6.2.0-zip/gcc/defaults.h 2016-12-31 16:42:29.094087738 -0500
|
|
@@ -495,6 +495,8 @@
|
+ ZIP_DEBUG_LINE("CANON-REG-RTN", x);
|
|
return x;
|
|
}
|
|
|
|
@@ -3125,6 +3137,8 @@
|
|
rtx new_rtx = 0;
|
|
int changed = 0;
|
|
|
|
+ZIP_DEBUG_LINE("CSE:FOLD-RTX", insn);
|
|
+
|
|
/* Operands of X. */
|
|
/* Workaround -Wmaybe-uninitialized false positive during
|
|
profiledbootstrap by initializing them. */
|
|
@@ -3144,14 +3158,16 @@
|
|
if (x == 0)
|
|
return x;
|
|
|
|
+ ZIP_DEBUG_LINE("FOLD-RTX", x);
|
|
/* Try to perform some initial simplifications on X. */
|
|
code = GET_CODE (x);
|
|
switch (code)
|
|
{
|
|
case MEM:
|
|
case SUBREG:
|
|
- if ((new_rtx = equiv_constant (x)) != NULL_RTX)
|
|
- return new_rtx;
|
|
+ if ((new_rtx = equiv_constant (x)) != NULL_RTX) {
|
|
+ ZIP_DEBUG_LINE("FOLD-RTX-NEW", new_rtx);
|
|
+ return new_rtx; }
|
|
return x;
|
|
|
|
case CONST:
|
|
@@ -3208,6 +3224,8 @@
|
|
rtx folded_arg = XEXP (x, i), const_arg;
|
|
machine_mode mode_arg = GET_MODE (folded_arg);
|
|
|
|
+ ZIP_DEBUG_LINE("FOLD-RTX-ARG = ", folded_arg);
|
|
+
|
|
switch (GET_CODE (folded_arg))
|
|
{
|
|
case MEM:
|
|
@@ -3317,6 +3335,7 @@
|
|
}
|
|
|
|
apply_change_group ();
|
|
+ ZIP_DEBUG_LINE("FOLD-RTX-CANONICALIZED = ", insn);
|
|
}
|
|
|
|
/* If X is an arithmetic operation, see if we can simplify it. */
|
|
@@ -4203,6 +4222,7 @@
|
|
{
|
|
rtx dest = SET_DEST (set);
|
|
rtx src = SET_SRC (set);
|
|
+ ZIP_DEBUG_LINE("TRY-BACK-SUBSTITUTE-REG", insn);
|
|
|
|
if (REG_P (dest)
|
|
&& REG_P (src) && ! HARD_REGISTER_P (src)
|
|
@@ -4258,6 +4278,7 @@
|
|
}
|
|
}
|
|
}
|
|
+ ZIP_DEBUG_LINE("TRY-BACK-SUBSTITUTE-REG, done", insn);
|
|
}
|
|
|
|
/* Record all the SETs in this instruction into SETS_PTR,
|
|
@@ -4351,6 +4372,7 @@
|
|
rtx tem;
|
|
rtx x = PATTERN (insn);
|
|
int i;
|
|
+ ZIP_DEBUG_LINE("CANONICALIZE-INSN", insn);
|
|
|
|
if (CALL_P (insn))
|
|
{
|
|
@@ -4364,6 +4386,7 @@
|
|
canon_reg (SET_SRC (x), insn);
|
|
apply_change_group ();
|
|
fold_rtx (SET_SRC (x), insn);
|
|
+ ZIP_DEBUG_LINE("CANONICALIZE-INSN, was set:", insn);
|
|
}
|
|
else if (GET_CODE (x) == CLOBBER)
|
|
{
|
|
@@ -4400,6 +4423,7 @@
|
|
canon_reg (PATTERN (insn), insn);
|
|
else if (GET_CODE (x) == PARALLEL)
|
|
{
|
|
+ ZIP_DEBUG_LINE("CANONICALIZE-INSN/parallel", insn);
|
|
for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
|
|
{
|
|
rtx y = XVECEXP (x, 0, i);
|
|
@@ -4491,6 +4515,7 @@
|
|
|
|
The result of apply_change_group can be ignored; see canon_reg. */
|
|
|
|
+ ZIP_DEBUG_LINE("CANONICALIZE-INSN/done", insn);
|
|
apply_change_group ();
|
|
}
|
|
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/defaults.h gcc-5.3.0-zip/gcc/defaults.h
|
|
--- gcc-5.3.0-original/gcc/defaults.h 2015-03-03 10:04:02.000000000 -0500
|
|
+++ gcc-5.3.0-zip/gcc/defaults.h 2016-02-06 16:57:53.939410173 -0500
|
|
@@ -480,6 +480,8 @@
|
|
#define LOG2_BITS_PER_UNIT 3
|
#define LOG2_BITS_PER_UNIT 3
|
#elif BITS_PER_UNIT == 16
|
#elif BITS_PER_UNIT == 16
|
#define LOG2_BITS_PER_UNIT 4
|
#define LOG2_BITS_PER_UNIT 4
|
+#elif BITS_PER_UNIT == 32
|
+#elif BITS_PER_UNIT == 32
|
+#define LOG2_BITS_PER_UNIT 5
|
+#define LOG2_BITS_PER_UNIT 5
|
#else
|
#else
|
#error Unknown BITS_PER_UNIT
|
#error Unknown BITS_PER_UNIT
|
#endif
|
#endif
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/df-scan.c gcc-5.3.0-zip/gcc/df-scan.c
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/df-scan.c gcc-6.2.0-zip/gcc/df-scan.c
|
--- gcc-5.3.0-original/gcc/df-scan.c 2015-01-09 15:18:42.000000000 -0500
|
--- gcc-6.2.0/gcc/df-scan.c 2016-01-04 09:30:50.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/df-scan.c 2016-04-14 16:12:03.614777002 -0400
|
+++ gcc-6.2.0-zip/gcc/df-scan.c 2016-12-31 16:43:04.557867015 -0500
|
@@ -61,6 +61,14 @@
|
@@ -35,6 +35,14 @@
|
|
#include "dumpfile.h"
|
|
|
typedef struct df_mw_hardreg *df_mw_hardreg_ptr;
|
|
|
|
+// #define DO_ZIP_DEBUGS
|
|
+#ifdef DO_ZIP_DEBUGS
|
+#ifdef DO_ZIP_DEBUGS
|
|
+#include <stdio.h>
|
|
+#define ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s;%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
|
+extern void zip_debug_rtx(const_rtx);
|
+extern void zip_debug_rtx(const_rtx);
|
+#define ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
|
|
+#else
|
+#else
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
+#endif
|
+#endif
|
+
|
+
|
|
/* The set of hard registers in eliminables[i].from. */
|
|
|
#ifndef HAVE_epilogue
|
static HARD_REG_SET elim_reg_set;
|
#define HAVE_epilogue 0
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/emit-rtl.c gcc-6.2.0-zip/gcc/emit-rtl.c
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/doc/gcc.log gcc-5.3.0-zip/gcc/doc/gcc.log
|
--- gcc-6.2.0/gcc/emit-rtl.c 2016-02-16 18:12:19.000000000 -0500
|
--- gcc-5.3.0-original/gcc/doc/gcc.log 1969-12-31 19:00:00.000000000 -0500
|
+++ gcc-6.2.0-zip/gcc/emit-rtl.c 2016-12-31 16:43:35.065677060 -0500
|
+++ gcc-5.3.0-zip/gcc/doc/gcc.log 2016-01-30 15:18:43.262724969 -0500
|
@@ -59,6 +59,15 @@
|
@@ -0,0 +1,214 @@
|
#include "stor-layout.h"
|
+This is pdfTeX, Version 3.1415926-2.5-1.40.14 (TeX Live 2013/Debian) (format=pdfetex 2014.5.7) 30 JAN 2016 15:17
|
#include "opts.h"
|
+entering extended mode
|
|
+ restricted \write18 enabled.
|
|
+ file:line:error style messages enabled.
|
|
+ %&-line parsing enabled.
|
|
+**\catcode126=12 \def\normaltilde{~}\catcode126=13 \let~\normaltilde \input ./
|
|
+gcc.texi
|
|
+(./gcc.texi (/usr/share/texmf/tex/texinfo/texinfo.tex
|
|
+Loading texinfo [version 2013-09-11.11]:
|
|
+\bindingoffset=\dimen16
|
|
+\normaloffset=\dimen17
|
|
+\pagewidth=\dimen18
|
|
+\pageheight=\dimen19
|
|
+\outerhsize=\dimen20
|
|
+\outervsize=\dimen21
|
|
+\cornerlong=\dimen22
|
|
+\cornerthick=\dimen23
|
|
+\topandbottommargin=\dimen24
|
|
+\headlinebox=\box16
|
|
+\footlinebox=\box17
|
|
+\margin=\insert252
|
|
+\EMsimple=\toks13
|
|
+\groupbox=\box18
|
|
+\groupinvalidhelp=\toks14
|
|
+\mil=\dimen25
|
|
+\exdentamount=\skip18
|
|
+\inmarginspacing=\skip19
|
|
+\centerpenalty=\count27
|
|
+ pdf,
|
|
+\tempnum=\count28
|
|
+\lnkcount=\count29
|
|
+\filename=\toks15
|
|
+\filenamelength=\count30
|
|
+\pgn=\count31
|
|
+\toksA=\toks16
|
|
+\toksB=\toks17
|
|
+\toksC=\toks18
|
|
+\toksD=\toks19
|
|
+\boxA=\box19
|
|
+\countA=\count32
|
|
+\nopdfimagehelp=\toks20
|
|
+ fonts,
|
|
+\sffam=\fam8
|
|
+\textleading=\dimen26
|
|
+ markup,
|
|
+\fontdepth=\count33
|
|
+ glyphs,
|
|
+\errorbox=\box20
|
|
+
|
|
+page headings,
|
|
+\titlepagetopglue=\skip20
|
|
+\titlepagebottomglue=\skip21
|
|
+\evenheadline=\toks21
|
|
+\oddheadline=\toks22
|
|
+\evenfootline=\toks23
|
|
+\oddfootline=\toks24
|
|
+ tables,
|
|
+\tableindent=\dimen27
|
|
+\itemindent=\dimen28
|
|
+\itemmargin=\dimen29
|
|
+\itemmax=\dimen30
|
|
+\itemno=\count34
|
|
+\multitableparskip=\skip22
|
|
+\multitableparindent=\skip23
|
|
+\multitablecolspace=\dimen31
|
|
+\multitablelinespace=\skip24
|
|
+\colcount=\count35
|
|
+\everytab=\toks25
|
|
+ conditionals,
|
|
+\doignorecount=\count36
|
|
+ indexing,
|
|
+\whatsitskip=\skip25
|
|
+\whatsitpenalty=\count37
|
|
+\secondaryindent=\skip26
|
|
+\partialpage=\box21
|
|
+\doublecolumnhsize=\dimen32
|
|
+ sectioning,
|
|
+\unnumberedno=\count38
|
|
+\chapno=\count39
|
|
+\secno=\count40
|
|
+\subsecno=\count41
|
|
+\subsubsecno=\count42
|
|
+\appendixno=\count43
|
|
+\absseclevel=\count44
|
|
+\secbase=\count45
|
|
+\chapheadingskip=\skip27
|
|
+\secheadingskip=\skip28
|
|
+\subsecheadingskip=\skip29
|
|
+ toc,
|
|
+\tocfile=\write0
|
|
+\contentsrightmargin=\skip30
|
|
+\savepageno=\count46
|
|
+\lastnegativepageno=\count47
|
|
+\tocindent=\dimen33
|
|
+ environments,
|
|
+\lispnarrowing=\skip31
|
|
+\envskipamount=\skip32
|
|
+\circthick=\dimen34
|
|
+\cartouter=\dimen35
|
|
+\cartinner=\dimen36
|
|
+\normbskip=\skip33
|
|
+\normpskip=\skip34
|
|
+\normlskip=\skip35
|
|
+\lskip=\skip36
|
|
+\rskip=\skip37
|
|
+\nonfillparindent=\dimen37
|
|
+\tabw=\dimen38
|
|
+\verbbox=\box22
|
|
+
|
|
+defuns,
|
|
+\defbodyindent=\skip38
|
|
+\defargsindent=\skip39
|
|
+\deflastargmargin=\skip40
|
|
+\defunpenalty=\count48
|
|
+\parencount=\count49
|
|
+\brackcount=\count50
|
|
+ macros,
|
|
+\paramno=\count51
|
|
+\macname=\toks26
|
|
+ cross references,
|
|
+\auxfile=\write1
|
|
+\savesfregister=\count52
|
|
+\toprefbox=\box23
|
|
+\printedrefnamebox=\box24
|
|
+\infofilenamebox=\box25
|
|
+\printedmanualbox=\box26
|
|
+ insertions,
|
|
+\footnoteno=\count53
|
|
+\SAVEfootins=\box27
|
|
+\SAVEmargin=\box28
|
|
+
|
|
+(/usr/share/texlive/texmf-dist/tex/generic/epsf/epsf.tex
|
|
+This is `epsf.tex' v2.7.4 <14 February 2011>
|
|
+\epsffilein=\read1
|
|
+\epsfframemargin=\dimen39
|
|
+\epsfframethickness=\dimen40
|
|
+\epsfrsize=\dimen41
|
|
+\epsftmp=\dimen42
|
|
+\epsftsize=\dimen43
|
|
+\epsfxsize=\dimen44
|
|
+\epsfysize=\dimen45
|
|
+\pspoints=\dimen46
|
|
+)
|
|
+\noepsfhelp=\toks27
|
|
+ localization,
|
|
+\nolanghelp=\toks28
|
|
+\countUTFx=\count54
|
|
+\countUTFy=\count55
|
|
+\countUTFz=\count56
|
|
+ formatting,
|
|
+\defaultparindent=\dimen47
|
|
+ and turning on texinfo input format.)
|
|
+\openout1 = `gcc.aux'.
|
|
+
|
|
+@cpindfile=@write2
|
|
+@fnindfile=@write3
|
|
+@vrindfile=@write4
|
|
+@tpindfile=@write5
|
|
+@kyindfile=@write6
|
|
+@pgindfile=@write7
|
|
+texinfo.tex: doing @include of gcc-common.texi
|
|
+
|
|
+
|
|
+./gcc.texi:25: I can't find file `gcc-common.texi'.
|
|
+@temp ->@input gcc-common.texi
|
|
+
|
|
+@includezzz ...and @input #1 }@expandafter }@temp
|
|
+ @popthisfilestack
|
|
+l.25 @include gcc-common.texi
|
|
+
|
|
+(Press Enter to retry, or Control-D to exit)
|
|
+Please type another input file name: include/gcc-common.texi
|
|
+(./include/gcc-common.texi
|
|
+texinfo.tex: doing @include of gcc-vers.texi
|
|
+
|
|
+
|
|
+./include/gcc-common.texi:11: I can't find file `gcc-vers.texi'.
|
|
+@temp ->@input gcc-vers.texi
|
|
+
|
|
+@includezzz ...and @input #1 }@expandafter }@temp
|
|
+ @popthisfilestack
|
|
+l.11 @include gcc-vers.texi
|
|
+
|
|
+(Press Enter to retry, or Control-D to exit)
|
|
+Please type another input file name: include/gcc-vers.texi
|
|
+./include/gcc-common.texi:11: I can't find file `include/gcc-vers.texi'.
|
|
+@temp ->@input gcc-vers.texi
|
|
+
|
|
+@includezzz ...and @input #1 }@expandafter }@temp
|
|
+ @popthisfilestack
|
|
+l.11 @include gcc-vers.texi
|
|
+
|
|
+(Press Enter to retry, or Control-D to exit)
|
|
+Please type another input file name:
|
|
+./include/gcc-common.texi:11: I can't find file `include/gcc-vers.texi'.
|
|
+@temp ->@input gcc-vers.texi
|
|
+
|
|
+@includezzz ...and @input #1 }@expandafter }@temp
|
|
+ @popthisfilestack
|
|
+l.11 @include gcc-vers.texi
|
|
+
|
|
+(Press Enter to retry, or Control-D to exit)
|
|
+Please type another input file name:
|
|
+./include/gcc-common.texi:11: Emergency stop.
|
|
+@temp ->@input gcc-vers.texi
|
|
+
|
|
+@includezzz ...and @input #1 }@expandafter }@temp
|
|
+ @popthisfilestack
|
|
+l.11 @include gcc-vers.texi
|
|
+
|
|
+End of file on the terminal!
|
|
+
|
|
+./include/gcc-common.texi:11: ==> Fatal error occurred, no output PDF file pro
|
|
+duced!
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/emit-rtl.c gcc-5.3.0-zip/gcc/emit-rtl.c
|
|
--- gcc-5.3.0-original/gcc/emit-rtl.c 2015-08-05 07:20:59.000000000 -0400
|
|
+++ gcc-5.3.0-zip/gcc/emit-rtl.c 2016-05-02 07:48:47.925017436 -0400
|
|
@@ -81,6 +81,15 @@
|
|
#include "builtins.h"
|
|
#include "rtl-iter.h"
|
|
|
|
+// #define DO_ZIP_DEBUGS
|
+
|
+#include <stdio.h>
|
|
+#ifdef DO_ZIP_DEBUGS
|
+#ifdef DO_ZIP_DEBUGS
|
+#define ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
|
+#include <stdio.h>
|
|
+#define ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s;%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
|
+extern void zip_debug_rtx(const_rtx);
|
+extern void zip_debug_rtx(const_rtx);
|
+#else
|
+#else
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
+#endif
|
+#endif
|
+
|
+
|
struct target_rtl default_target_rtl;
|
struct target_rtl default_target_rtl;
|
#if SWITCHABLE_TARGET
|
#if SWITCHABLE_TARGET
|
struct target_rtl *this_target_rtl = &default_target_rtl;
|
struct target_rtl *this_target_rtl = &default_target_rtl;
|
@@ -2979,6 +2988,8 @@
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/final.c gcc-6.2.0-zip/gcc/final.c
|
break;
|
--- gcc-6.2.0/gcc/final.c 2016-01-22 11:44:10.000000000 -0500
|
}
|
+++ gcc-6.2.0-zip/gcc/final.c 2017-02-06 15:35:15.410085646 -0500
|
|
@@ -79,6 +79,16 @@
|
+ZIP_DEBUG_LINE("Before RTX_FLAG",x);
|
|
+
|
|
/* This rtx may not be shared. If it has already been seen,
|
|
replace it with a copy of itself. */
|
|
|
|
@@ -2989,6 +3000,8 @@
|
|
}
|
|
RTX_FLAG (x, used) = 1;
|
|
|
|
+ZIP_DEBUG_LINE("Post RTX_FLAG",x);
|
|
+
|
|
/* Now scan the subexpressions recursively.
|
|
We can store any replaced subexpressions directly into X
|
|
since we know X is not shared! Any vectors in X
|
|
@@ -3665,7 +3678,9 @@
|
|
split_branch_probability = XINT (note, 0);
|
|
probability = split_branch_probability;
|
|
|
|
+ZIP_DEBUG_LINE("Before split", trial);
|
|
seq = safe_as_a <rtx_insn *> (split_insns (pat, trial));
|
|
+ZIP_DEBUG_LINE("After split", seq);
|
|
|
|
split_branch_probability = -1;
|
|
|
|
@@ -3834,6 +3849,7 @@
|
|
if (! tem->deleted () && INSN_P (tem))
|
|
tem = try_split (PATTERN (tem), tem, 1);
|
|
|
|
+
|
|
/* Return either the first or the last insn, depending on which was
|
|
requested. */
|
|
return last
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/expr.c gcc-5.3.0-zip/gcc/expr.c
|
|
--- gcc-5.3.0-original/gcc/expr.c 2015-04-07 10:34:06.000000000 -0400
|
|
+++ gcc-5.3.0-zip/gcc/expr.c 2016-03-08 04:07:01.426335724 -0500
|
|
@@ -7999,6 +7999,8 @@
|
|
the back of the caller.
|
|
The normal operating mode is to pass FALSE for this parameter. */
|
|
|
|
+#include "print-tree.h"
|
|
+
|
|
rtx
|
|
expand_expr_real (tree exp, rtx target, machine_mode tmode,
|
|
enum expand_modifier modifier, rtx *alt_rtl,
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/final.c gcc-5.3.0-zip/gcc/final.c
|
|
--- gcc-5.3.0-original/gcc/final.c 2015-01-15 08:28:42.000000000 -0500
|
|
+++ gcc-5.3.0-zip/gcc/final.c 2016-04-20 20:52:07.186056061 -0400
|
|
@@ -109,6 +109,14 @@
|
|
#include "wide-int-print.h"
|
|
#include "rtl-iter.h"
|
#include "rtl-iter.h"
|
|
#include "print-rtl.h"
|
|
|
|
+
|
+// #define DO_ZIP_DEBUGS
|
+// #define DO_ZIP_DEBUGS
|
+#ifdef DO_ZIP_DEBUGS
|
+#ifdef DO_ZIP_DEBUGS
|
+extern void zip_debug_rtx(const_rtx);
|
+#include <stdio.h>
|
+#define ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
|
+#define ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
|
|
+extern void zip_debug_rtx(const_rtx);
|
+#else
|
+#else
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
+#endif
|
+#endif
|
+
|
+
|
#ifdef XCOFF_DEBUGGING_INFO
|
#ifdef XCOFF_DEBUGGING_INFO
|
#include "xcoffout.h" /* Needed for external data
|
#include "xcoffout.h" /* Needed for external data declarations. */
|
declarations for e.g. AIX 4.x. */
|
#endif
|
@@ -2071,6 +2079,8 @@
|
@@ -2944,6 +2954,8 @@
|
/* Output the insns. */
|
|
for (insn = first; insn;)
|
current_output_insn = debug_insn = insn;
|
{
|
|
+ ZIP_DEBUG_LINE("final()\n", insn);
|
+ZIP_DEBUG_LINE("FINAL-INSN", insn);
|
+
|
+
|
if (HAVE_ATTR_length)
|
/* Find the proper template for this insn. */
|
{
|
templ = get_insn_template (insn_code_number, insn);
|
if ((unsigned) INSN_UID (insn) >= INSN_ADDRESSES_SIZE ())
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/genmodes.c gcc-5.3.0-zip/gcc/genmodes.c
|
|
--- gcc-5.3.0-original/gcc/genmodes.c 2015-01-05 07:33:28.000000000 -0500
|
|
+++ gcc-5.3.0-zip/gcc/genmodes.c 2016-03-04 21:27:49.669147699 -0500
|
|
@@ -330,7 +330,8 @@
|
|
the size of a CC mode is four units. */
|
|
validate_mode (m, UNSET, UNSET, UNSET, UNSET, UNSET);
|
|
|
|
- m->bytesize = 4;
|
|
+ /* For the ZipCPU, however, it is only one unit */
|
|
+ m->bytesize = 1;
|
|
m->ncomponents = 1;
|
|
m->component = 0;
|
|
break;
|
|
@@ -766,11 +767,12 @@
|
|
|
|
/* So put the default value unless the target needs a non standard
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/fold-const.c gcc-6.2.0-zip/gcc/fold-const.c
|
value. */
|
--- gcc-6.2.0/gcc/fold-const.c 2016-07-08 16:20:23.000000000 -0400
|
-#ifdef BITS_PER_UNIT
|
+++ gcc-6.2.0-zip/gcc/fold-const.c 2016-12-31 16:47:49.000093249 -0500
|
- bits_per_unit = BITS_PER_UNIT;
|
@@ -1247,7 +1247,7 @@
|
-#else
|
wide_int w2 = arg2;
|
- bits_per_unit = 8;
|
f2.data.high = w2.elt (1);
|
-#endif
|
f2.data.low = w2.elt (0);
|
+// #ifdef BITS_PER_UNIT
|
- f2.mode = SImode;
|
+ // bits_per_unit = BITS_PER_UNIT;
|
+ f2.mode = word_mode;
|
+// #else
|
|
+ bits_per_unit = 32;
|
|
+#warning "Is there a more automated way to set bits per unit?"
|
|
+// #endif
|
|
|
|
#ifdef MAX_BITSIZE_MODE_ANY_INT
|
|
max_bitsize_mode_any_int = MAX_BITSIZE_MODE_ANY_INT;
|
|
@@ -1083,7 +1085,7 @@
|
|
first = modes[c];
|
|
last = 0;
|
|
for (m = first; m; last = m, m = m->next)
|
|
- ;
|
|
+ if ((m->next)&&(m->next->bytesize == m->bytesize)) first = m;
|
|
|
|
/* Don't use BImode for MIN_MODE_INT, since otherwise the middle
|
|
end will try to use it for bitfields in structures and the
|
|
@@ -1268,7 +1270,7 @@
|
|
continue;
|
|
if (m->precision != (unsigned int) -1)
|
|
{
|
|
- if (m2->precision != 2 * m->precision)
|
|
+ if (m2->precision < 2 * m->precision)
|
|
continue;
|
|
}
|
|
else
|
|
@@ -1323,7 +1325,6 @@
|
|
tagged_printf ("MODE_MASK (%u)", m->precision, m->name);
|
|
else
|
|
tagged_printf ("MODE_MASK (%u*BITS_PER_UNIT)", m->bytesize, m->name);
|
|
-
|
|
puts ("#undef MODE_MASK");
|
|
print_closer ();
|
|
}
|
}
|
@@ -1351,12 +1352,23 @@
|
break;
|
int c;
|
|
struct mode_data *m;
|
|
|
|
+ puts(
|
|
+"\n\n/* This is a rather strange conundrum. Alignment is used by the host in\n"
|
|
+" * the assembly file, whereas the size is used by the target. Thus, for\n"
|
|
+" * now, to align to a single target word means to align to 4 8-bit bytes in\n"
|
|
+" * assembly. If you get it wrong, the assembler will try to help. Thus,\n"
|
|
+" * aligning to anything less than 4 (1 target word) will cause an alignment\n"
|
|
+" * of the target word in size. However, this tries to do a little something\n"
|
|
+" * teach our compiler what we are doing.\n"
|
|
+" */\n");
|
|
print_maybe_const_decl ("%sunsigned char",
|
|
"mode_base_align", "NUM_MACHINE_MODES",
|
|
alignment);
|
|
|
|
for_all_modes (c, m)
|
|
- tagged_printf ("%u", m->alignment, m->name);
|
|
+ tagged_printf ("%u", 4*m->bytesize,
|
|
+ // m->alignment,
|
|
+ m->name);
|
|
|
|
print_closer ();
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/jump.c gcc-6.2.0-zip/gcc/jump.c
|
}
|
--- gcc-6.2.0/gcc/jump.c 2016-01-04 09:30:50.000000000 -0500
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/jump.c gcc-5.3.0-zip/gcc/jump.c
|
+++ gcc-6.2.0-zip/gcc/jump.c 2016-12-31 16:49:10.675582836 -0500
|
--- gcc-5.3.0-original/gcc/jump.c 2015-01-27 04:19:30.000000000 -0500
|
@@ -50,6 +50,15 @@
|
+++ gcc-5.3.0-zip/gcc/jump.c 2016-04-06 14:06:50.207563805 -0400
|
#include "cfgrtl.h"
|
@@ -80,6 +80,14 @@
|
|
#include "target.h"
|
|
#include "rtl-iter.h"
|
#include "rtl-iter.h"
|
|
|
+// #define DO_ZIP_DEBUGS
|
+
|
+#ifdef DO_ZIP_DEBUGS
|
+#ifdef DO_ZIP_DEBUGS
|
+#include <stdio.h>
|
+#include <stdio.h>
|
+#define ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX); }while(0)
|
+#define ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s;%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
|
+extern void zip_debug_rtx(const_rtx);
|
+extern void zip_debug_rtx(const_rtx);
|
+#else
|
+#else
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
+#endif
|
+#endif
|
|
+
|
/* Optimize jump y; x: ... y: jumpif... x?
|
/* Optimize jump y; x: ... y: jumpif... x?
|
Don't know if it is worth bothering with. */
|
Don't know if it is worth bothering with. */
|
/* Optimize two cases of conditional jump to conditional jump?
|
/* Optimize two cases of conditional jump to conditional jump?
|
@@ -1136,6 +1144,7 @@
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/loop-doloop.c gcc-6.2.0-zip/gcc/loop-doloop.c
|
int i;
|
--- gcc-6.2.0/gcc/loop-doloop.c 2016-01-14 18:12:53.000000000 -0500
|
const char *fmt;
|
+++ gcc-6.2.0-zip/gcc/loop-doloop.c 2016-12-31 16:50:27.099104820 -0500
|
|
@@ -37,6 +37,15 @@
|
+ZIP_DEBUG_LINE("Mark jump label",insn);
|
#include "regs.h"
|
switch (code)
|
#include "df.h"
|
{
|
|
case PC:
|
|
@@ -1248,6 +1257,8 @@
|
|
break;
|
|
}
|
|
|
|
+ZIP_DEBUG_LINE("Post case",insn);
|
|
+
|
+
|
fmt = GET_RTX_FORMAT (code);
|
|
|
|
/* The primary target of a tablejump is the label of the ADDR_VEC,
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/loop-doloop.c gcc-5.3.0-zip/gcc/loop-doloop.c
|
|
--- gcc-5.3.0-original/gcc/loop-doloop.c 2015-01-15 08:28:42.000000000 -0500
|
|
+++ gcc-5.3.0-zip/gcc/loop-doloop.c 2016-09-13 12:12:36.248901944 -0400
|
|
@@ -62,6 +62,13 @@
|
|
#include "dumpfile.h"
|
|
#include "loop-unroll.h"
|
|
|
|
+// #define DO_ZIP_DEBUGS
|
|
+#ifdef DO_ZIP_DEBUGS
|
+#ifdef DO_ZIP_DEBUGS
|
|
+#include <stdio.h>
|
|
+#define ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s;%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
|
+extern void zip_debug_rtx(const_rtx);
|
+extern void zip_debug_rtx(const_rtx);
|
+#define ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr, "%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX); }while(0)
|
|
+#else
|
+#else
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
+#endif
|
+#endif
|
|
+
|
/* This module is used to modify loops with a determinable number of
|
/* This module is used to modify loops with a determinable number of
|
iterations to use special low-overhead looping instructions.
|
iterations to use special low-overhead looping instructions.
|
|
|
@@ -138,7 +145,7 @@
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/loop-iv.c gcc-6.2.0-zip/gcc/loop-iv.c
|
|
--- gcc-6.2.0/gcc/loop-iv.c 2016-01-04 09:30:50.000000000 -0500
|
pattern = PATTERN (doloop_pat);
|
+++ gcc-6.2.0-zip/gcc/loop-iv.c 2016-12-31 16:52:42.034259845 -0500
|
|
@@ -1715,8 +1715,8 @@
|
- if (GET_CODE (pattern) != PARALLEL)
|
if (op0 != XEXP (cond, 0)
|
+ if (GET_CODE (doloop_pat) != PARALLEL)
|
|| op1 != XEXP (cond, 1)
|
|
|| code != GET_CODE (cond)
|
|
- || GET_MODE (cond) != SImode)
|
|
- cond = gen_rtx_fmt_ee (code, SImode, op0, op1);
|
|
+ || GET_MODE (cond) != word_mode)
|
|
+ cond = gen_rtx_fmt_ee (code, word_mode, op0, op1);
|
|
|
|
return cond;
|
|
}
|
|
@@ -2083,9 +2083,9 @@
|
|
rtx mmin, mmax, cond_over, cond_under;
|
|
|
|
get_mode_bounds (mode, signed_p, iv->extend_mode, &mmin, &mmax);
|
|
- cond_under = simplify_gen_relational (LT, SImode, iv->extend_mode,
|
|
+ cond_under = simplify_gen_relational (LT, word_mode, iv->extend_mode,
|
|
iv->base, mmin);
|
|
- cond_over = simplify_gen_relational (GT, SImode, iv->extend_mode,
|
|
+ cond_over = simplify_gen_relational (GT, word_mode, iv->extend_mode,
|
|
iv->base, mmax);
|
|
|
|
switch (cond)
|
|
@@ -2464,7 +2464,7 @@
|
|
if (iv0.step == const0_rtx)
|
{
|
{
|
rtx cond;
|
tmp = lowpart_subreg (mode, iv0.base, comp_mode);
|
rtx prev_insn = prev_nondebug_insn (doloop_pat);
|
- assumption = simplify_gen_relational (EQ, SImode, mode, tmp,
|
@@ -186,10 +193,11 @@
|
+ assumption = simplify_gen_relational (EQ, word_mode, mode, tmp,
|
}
|
mode_mmax);
|
|
if (assumption == const_true_rtx)
|
|
goto zero_iter_simplify;
|
|
@@ -2474,7 +2474,7 @@
|
else
|
else
|
{
|
{
|
- cmp = XVECEXP (pattern, 0, 0);
|
tmp = lowpart_subreg (mode, iv1.base, comp_mode);
|
- inc = XVECEXP (pattern, 0, 1);
|
- assumption = simplify_gen_relational (EQ, SImode, mode, tmp,
|
+ cmp = XVECEXP (doloop_pat, 0, 0);
|
+ assumption = simplify_gen_relational (EQ, word_mode, mode, tmp,
|
+ inc = XVECEXP (doloop_pat, 0, 1);
|
mode_mmin);
|
}
|
if (assumption == const_true_rtx)
|
|
goto zero_iter_simplify;
|
+
|
@@ -2561,10 +2561,10 @@
|
/* Check for (set (reg) (something)). */
|
bound = simplify_gen_binary (MINUS, comp_mode, bound, delta);
|
if (GET_CODE (inc) != SET)
|
bound = lowpart_subreg (mode, bound, comp_mode);
|
return 0;
|
tmp = lowpart_subreg (mode, iv0.base, comp_mode);
|
@@ -227,6 +235,7 @@
|
- may_xform = simplify_gen_relational (cond, SImode, mode,
|
&& XEXP (condition, 1) != const1_rtx))
|
+ may_xform = simplify_gen_relational (cond, word_mode, mode,
|
return 0;
|
bound, tmp);
|
|
may_not_xform = simplify_gen_relational (reverse_condition (cond),
|
+
|
- SImode, mode,
|
if ((XEXP (condition, 0) == reg)
|
+ word_mode, mode,
|
/* For the third case: */
|
bound, tmp);
|
|| ((cc_reg != NULL_RTX)
|
|
@@ -235,7 +244,7 @@
|
|
|| (GET_CODE (XEXP (condition, 0)) == PLUS
|
|
&& XEXP (XEXP (condition, 0), 0) == reg))
|
|
{
|
|
- if (GET_CODE (pattern) != PARALLEL)
|
|
+ if (GET_CODE (doloop_pat) != PARALLEL)
|
|
/* For the second form we expect:
|
|
|
|
(set (reg) (plus (reg) (const_int -1))
|
|
@@ -275,6 +284,7 @@
|
|
return condition;
|
|
}
|
}
|
|
else
|
+
|
@@ -2573,10 +2573,10 @@
|
/* ??? If a machine uses a funny comparison, we could return a
|
bound = simplify_gen_binary (PLUS, comp_mode, bound, delta);
|
canonicalized form here. */
|
bound = lowpart_subreg (mode, bound, comp_mode);
|
|
tmp = lowpart_subreg (mode, iv1.base, comp_mode);
|
@@ -500,7 +510,6 @@
|
- may_xform = simplify_gen_relational (cond, SImode, mode,
|
default:
|
+ may_xform = simplify_gen_relational (cond, word_mode, mode,
|
gcc_unreachable ();
|
tmp, bound);
|
|
may_not_xform = simplify_gen_relational (reverse_condition (cond),
|
|
- SImode, mode,
|
|
+ word_mode, mode,
|
|
tmp, bound);
|
|
}
|
|
}
|
|
@@ -2629,7 +2629,7 @@
|
|
tmp0 = lowpart_subreg (mode, iv0.base, comp_mode);
|
|
tmp1 = lowpart_subreg (mode, iv1.base, comp_mode);
|
|
assumption = simplify_gen_relational (reverse_condition (cond),
|
|
- SImode, mode, tmp0, tmp1);
|
|
+ word_mode, mode, tmp0, tmp1);
|
|
if (assumption == const_true_rtx)
|
|
goto zero_iter_simplify;
|
|
else if (assumption != const0_rtx)
|
|
@@ -2671,7 +2671,7 @@
|
|
|
|
tmp1 = lowpart_subreg (mode, iv1.base, comp_mode);
|
|
tmp = simplify_gen_binary (UMOD, mode, tmp1, gen_int_mode (d, mode));
|
|
- assumption = simplify_gen_relational (NE, SImode, mode, tmp, const0_rtx);
|
|
+ assumption = simplify_gen_relational (NE, word_mode, mode, tmp, const0_rtx);
|
|
desc->infinite = alloc_EXPR_LIST (0, assumption, desc->infinite);
|
|
|
|
tmp = simplify_gen_binary (UDIV, mode, tmp1, gen_int_mode (d, mode));
|
|
@@ -2703,19 +2703,19 @@
|
|
/* If s is power of 2, we know that the loop is infinite if
|
|
a % s <= b % s and b + s overflows. */
|
|
assumption = simplify_gen_relational (reverse_condition (cond),
|
|
- SImode, mode,
|
|
+ word_mode, mode,
|
|
tmp1, bound);
|
|
|
|
t0 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp0), step);
|
|
t1 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp1), step);
|
|
- tmp = simplify_gen_relational (cond, SImode, mode, t0, t1);
|
|
- assumption = simplify_gen_binary (AND, SImode, assumption, tmp);
|
|
+ tmp = simplify_gen_relational (cond, word_mode, mode, t0, t1);
|
|
+ assumption = simplify_gen_binary (AND, word_mode, assumption, tmp);
|
|
desc->infinite =
|
|
alloc_EXPR_LIST (0, assumption, desc->infinite);
|
}
|
}
|
-
|
else
|
if (increment_count)
|
|
count = simplify_gen_binary (PLUS, mode, count, const1_rtx);
|
|
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/machmode.def gcc-5.3.0-zip/gcc/machmode.def
|
|
--- gcc-5.3.0-original/gcc/machmode.def 2015-01-05 07:33:28.000000000 -0500
|
|
+++ gcc-5.3.0-zip/gcc/machmode.def 2016-03-08 11:56:45.375491523 -0500
|
|
@@ -184,11 +184,11 @@
|
|
larger types, then corresponding modes must be added here. The
|
|
name OI is reserved for a 256-bit type (needed by some back ends).
|
|
*/
|
|
-INT_MODE (QI, 1);
|
|
-INT_MODE (HI, 2);
|
|
-INT_MODE (SI, 4);
|
|
-INT_MODE (DI, 8);
|
|
-INT_MODE (TI, 16);
|
|
+// INT_MODE (QI, 1);
|
|
+// INT_MODE (HI, 1);
|
|
+INT_MODE (SI, 1);
|
|
+INT_MODE (DI, 2);
|
|
+INT_MODE (TI, 4);
|
|
|
|
/* No partial integer modes are defined by default. */
|
|
|
|
@@ -206,35 +206,35 @@
|
|
These are the IEEE mappings. They can be overridden with
|
|
RESET_FLOAT_FORMAT or at runtime (in TARGET_OPTION_OVERRIDE). */
|
|
|
|
-FLOAT_MODE (SF, 4, ieee_single_format);
|
|
-FLOAT_MODE (DF, 8, ieee_double_format);
|
|
+FLOAT_MODE (SF, 1, ieee_single_format);
|
|
+FLOAT_MODE (DF, 2, ieee_double_format);
|
|
|
|
/* Basic CC modes.
|
|
FIXME define this only for targets that need it. */
|
|
CC_MODE (CC);
|
|
|
|
/* Fixed-point modes. */
|
|
-FRACT_MODE (QQ, 1, 7); /* s.7 */
|
|
-FRACT_MODE (HQ, 2, 15); /* s.15 */
|
|
-FRACT_MODE (SQ, 4, 31); /* s.31 */
|
|
-FRACT_MODE (DQ, 8, 63); /* s.63 */
|
|
-FRACT_MODE (TQ, 16, 127); /* s.127 */
|
|
-
|
|
-UFRACT_MODE (UQQ, 1, 8); /* .8 */
|
|
-UFRACT_MODE (UHQ, 2, 16); /* .16 */
|
|
-UFRACT_MODE (USQ, 4, 32); /* .32 */
|
|
-UFRACT_MODE (UDQ, 8, 64); /* .64 */
|
|
-UFRACT_MODE (UTQ, 16, 128); /* .128 */
|
|
-
|
|
-ACCUM_MODE (HA, 2, 8, 7); /* s8.7 */
|
|
-ACCUM_MODE (SA, 4, 16, 15); /* s16.15 */
|
|
-ACCUM_MODE (DA, 8, 32, 31); /* s32.31 */
|
|
-ACCUM_MODE (TA, 16, 64, 63); /* s64.63 */
|
|
-
|
|
-UACCUM_MODE (UHA, 2, 8, 8); /* 8.8 */
|
|
-UACCUM_MODE (USA, 4, 16, 16); /* 16.16 */
|
|
-UACCUM_MODE (UDA, 8, 32, 32); /* 32.32 */
|
|
-UACCUM_MODE (UTA, 16, 64, 64); /* 64.64 */
|
|
+/* FRACT_MODE (QQ, 1, 7); /* s.7 */
|
|
+/* FRACT_MODE (HQ, 1, 15); /* s.15 */
|
|
+FRACT_MODE (SQ, 1, 31); /* s.31 */
|
|
+FRACT_MODE (DQ, 2, 63); /* s.63 */
|
|
+FRACT_MODE (TQ, 4, 127); /* s.127 */
|
|
+
|
|
+/* UFRACT_MODE (UQQ, 1, 8); /* .8 */
|
|
+/* UFRACT_MODE (UHQ, 1, 16); /* .16 */
|
|
+UFRACT_MODE (USQ, 1, 32); /* .32 */
|
|
+UFRACT_MODE (UDQ, 2, 64); /* .64 */
|
|
+UFRACT_MODE (UTQ, 4, 128); /* .128 */
|
|
+
|
|
+/* ACCUM_MODE (HA, 2, 8, 7); /* s8.7 */
|
|
+ACCUM_MODE (SA, 1, 16, 15); /* s16.15 */
|
|
+ACCUM_MODE (DA, 2, 32, 31); /* s32.31 */
|
|
+ACCUM_MODE (TA, 4, 64, 63); /* s64.63 */
|
|
+
|
|
+/* UACCUM_MODE (UHA, 2, 8, 8); /* 8.8 */
|
|
+UACCUM_MODE (USA, 1, 16, 16); /* 16.16 */
|
|
+UACCUM_MODE (UDA, 2, 32, 32); /* 32.32 */
|
|
+UACCUM_MODE (UTA, 4, 64, 64); /* 64.64 */
|
|
|
|
/* Allow the target to specify additional modes of various kinds. */
|
|
#if HAVE_EXTRA_MODES
|
|
@@ -246,9 +246,9 @@
|
|
COMPLEX_MODES (FLOAT);
|
|
|
|
/* Decimal floating point modes. */
|
|
-DECIMAL_FLOAT_MODE (SD, 4, decimal_single_format);
|
|
-DECIMAL_FLOAT_MODE (DD, 8, decimal_double_format);
|
|
-DECIMAL_FLOAT_MODE (TD, 16, decimal_quad_format);
|
|
+DECIMAL_FLOAT_MODE (SD, 1, decimal_single_format);
|
|
+DECIMAL_FLOAT_MODE (DD, 2, decimal_double_format);
|
|
+DECIMAL_FLOAT_MODE (TD, 4, decimal_quad_format);
|
|
|
|
/* The symbol Pmode stands for one of the above machine modes (usually SImode).
|
|
The tm.h file specifies which one. It is not a distinct mode. */
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/machmode.h gcc-5.3.0-zip/gcc/machmode.h
|
|
--- gcc-5.3.0-original/gcc/machmode.h 2015-01-05 07:33:28.000000000 -0500
|
|
+++ gcc-5.3.0-zip/gcc/machmode.h 2016-02-06 17:21:49.592924065 -0500
|
|
@@ -180,13 +180,7 @@
|
|
/* Get the size in bytes and bits of an object of mode MODE. */
|
|
|
|
extern CONST_MODE_SIZE unsigned char mode_size[NUM_MACHINE_MODES];
|
|
-#if GCC_VERSION >= 4001
|
|
-#define GET_MODE_SIZE(MODE) \
|
|
- ((unsigned short) (__builtin_constant_p (MODE) \
|
|
- ? mode_size_inline (MODE) : mode_size[MODE]))
|
|
-#else
|
|
#define GET_MODE_SIZE(MODE) ((unsigned short) mode_size[MODE])
|
|
-#endif
|
|
#define GET_MODE_BITSIZE(MODE) \
|
|
((unsigned short) (GET_MODE_SIZE (MODE) * BITS_PER_UNIT))
|
|
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/objc/objc-encoding.c gcc-5.3.0-zip/gcc/objc/objc-encoding.c
|
|
--- gcc-5.3.0-original/gcc/objc/objc-encoding.c 2015-01-09 15:18:42.000000000 -0500
|
|
+++ gcc-5.3.0-zip/gcc/objc/objc-encoding.c 2016-03-04 22:53:40.431902505 -0500
|
|
@@ -765,10 +765,14 @@
|
|
{
|
|
switch (TYPE_MODE (type))
|
|
{
|
|
+#ifdef HAVE_QImode
|
|
case QImode:
|
|
charType = 'C'; break;
|
|
+#endif
|
|
+#ifdef HAVE_HImode
|
|
case HImode:
|
|
charType = 'S'; break;
|
|
+#endif
|
|
case SImode:
|
|
{
|
|
if (type == long_unsigned_type_node)
|
|
@@ -788,10 +792,14 @@
|
|
{
|
|
switch (TYPE_MODE (type))
|
|
{
|
{
|
+#ifdef HAVE_QImode
|
- assumption = simplify_gen_relational (cond, SImode, mode,
|
case QImode:
|
+ assumption = simplify_gen_relational (cond, word_mode, mode,
|
charType = 'c'; break;
|
tmp1, bound);
|
+#endif
|
desc->assumptions =
|
+#ifdef HAVE_HImode
|
alloc_EXPR_LIST (0, assumption, desc->assumptions);
|
case HImode:
|
@@ -2724,7 +2724,7 @@
|
charType = 's'; break;
|
tmp = simplify_gen_binary (PLUS, comp_mode, iv1.base, iv0.step);
|
+#endif
|
tmp = lowpart_subreg (mode, tmp, comp_mode);
|
case SImode:
|
assumption = simplify_gen_relational (reverse_condition (cond),
|
|
- SImode, mode, tmp0, tmp);
|
|
+ word_mode, mode, tmp0, tmp);
|
|
|
|
delta = simplify_gen_binary (PLUS, mode, tmp1, step);
|
|
delta = simplify_gen_binary (MINUS, mode, delta, tmp0);
|
|
@@ -2747,19 +2747,19 @@
|
|
/* If s is power of 2, we know that the loop is infinite if
|
|
a % s <= b % s and a - s overflows. */
|
|
assumption = simplify_gen_relational (reverse_condition (cond),
|
|
- SImode, mode,
|
|
+ word_mode, mode,
|
|
bound, tmp0);
|
|
|
|
t0 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp0), step);
|
|
t1 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp1), step);
|
|
- tmp = simplify_gen_relational (cond, SImode, mode, t0, t1);
|
|
- assumption = simplify_gen_binary (AND, SImode, assumption, tmp);
|
|
+ tmp = simplify_gen_relational (cond, word_mode, mode, t0, t1);
|
|
+ assumption = simplify_gen_binary (AND, word_mode, assumption, tmp);
|
|
desc->infinite =
|
|
alloc_EXPR_LIST (0, assumption, desc->infinite);
|
|
}
|
|
else
|
{
|
{
|
if (type == long_integer_type_node)
|
- assumption = simplify_gen_relational (cond, SImode, mode,
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/postreload.c gcc-5.3.0-zip/gcc/postreload.c
|
+ assumption = simplify_gen_relational (cond, word_mode, mode,
|
--- gcc-5.3.0-original/gcc/postreload.c 2015-07-17 09:50:38.000000000 -0400
|
bound, tmp0);
|
+++ gcc-5.3.0-zip/gcc/postreload.c 2016-03-24 21:30:23.402590035 -0400
|
desc->assumptions =
|
@@ -71,6 +71,14 @@
|
alloc_EXPR_LIST (0, assumption, desc->assumptions);
|
#include "df.h"
|
@@ -2768,7 +2768,7 @@
|
#include "dbgcnt.h"
|
tmp = simplify_gen_binary (PLUS, comp_mode, iv0.base, iv1.step);
|
|
tmp = lowpart_subreg (mode, tmp, comp_mode);
|
|
assumption = simplify_gen_relational (reverse_condition (cond),
|
|
- SImode, mode,
|
|
+ word_mode, mode,
|
|
tmp, tmp1);
|
|
delta = simplify_gen_binary (MINUS, mode, tmp0, step);
|
|
delta = simplify_gen_binary (MINUS, mode, tmp1, delta);
|
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/optabs.c gcc-6.2.0-zip/gcc/optabs.c
|
|
--- gcc-6.2.0/gcc/optabs.c 2016-02-16 10:15:40.000000000 -0500
|
|
+++ gcc-6.2.0-zip/gcc/optabs.c 2017-03-01 15:46:15.660221429 -0500
|
|
@@ -43,6 +43,17 @@
|
|
#include "optabs-tree.h"
|
|
#include "libfuncs.h"
|
|
|
|
+
|
+// #define DO_ZIP_DEBUGS
|
+// #define DO_ZIP_DEBUGS
|
+#ifdef DO_ZIP_DEBUGS
|
+#ifdef DO_ZIP_DEBUGS
|
+extern void zip_debug_rtx(const_rtx);
|
+#include <stdio.h>
|
+#define ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
|
+#define ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
|
|
+extern void zip_debug_rtx(const_rtx);
|
|
+extern void zip_debug_rtx_pfx(const char *,const_rtx);
|
+#else
|
+#else
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
+#endif
|
+#endif
|
+
|
+
|
static int reload_cse_noop_set_p (rtx);
|
static void prepare_float_lib_cmp (rtx, rtx, enum rtx_code, rtx *,
|
static bool reload_cse_simplify (rtx_insn *, rtx);
|
machine_mode *);
|
static void reload_cse_regs_1 (void);
|
static rtx expand_unop_direct (machine_mode, optab, rtx, rtx, int);
|
@@ -120,6 +128,8 @@
|
@@ -6985,6 +6996,15 @@
|
basic_block insn_bb = BLOCK_FOR_INSN (insn);
|
maybe_gen_insn (enum insn_code icode, unsigned int nops,
|
unsigned insn_bb_succs = EDGE_COUNT (insn_bb->succs);
|
struct expand_operand *ops)
|
|
|
+ ZIP_DEBUG_LINE("RELOAD-CSE-SIMPLIFY:",insn);
|
|
+
|
|
if (GET_CODE (body) == SET)
|
|
{
|
|
int count = 0;
|
|
@@ -147,6 +157,7 @@
|
|
apply_change_group ();
|
|
else
|
|
reload_cse_simplify_operands (insn, testreg);
|
|
+ ZIP_DEBUG_LINE("End of reload_cse_simplify_operands", insn);
|
|
}
|
|
else if (GET_CODE (body) == PARALLEL)
|
|
{
|
{
|
@@ -205,6 +216,7 @@
|
+#ifdef DO_ZIP_DEBUGS
|
apply_change_group ();
|
+fprintf(stderr, "ICODE = %d\n", icode);
|
else
|
+fprintf(stderr, "NOPS = %d\n", nops);
|
reload_cse_simplify_operands (insn, testreg);
|
+for(int i=0; i<nops; i++) {
|
+ ZIP_DEBUG_LINE("End of reload_cse_simplify_operands", insn);
|
+ char str[10];
|
}
|
+ sprintf(str, "Op %d: ", i);
|
|
+ zip_debug_rtx_pfx(str, ops[i].value);
|
done:
|
+}
|
@@ -246,6 +258,7 @@
|
+#endif
|
cfg_changed |= reload_cse_simplify (insn, testreg);
|
gcc_assert (nops == (unsigned int) insn_data[(int) icode].n_generator_args);
|
|
if (!maybe_legitimize_operands (icode, 0, nops, ops))
|
cselib_process_insn (insn);
|
return NULL;
|
+ ZIP_DEBUG_LINE("End-CSE-REGS-1:",insn);
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/recog.c gcc-6.2.0-zip/gcc/recog.c
|
}
|
--- gcc-6.2.0/gcc/recog.c 2016-01-29 13:47:17.000000000 -0500
|
|
+++ gcc-6.2.0-zip/gcc/recog.c 2017-02-06 15:47:48.493946049 -0500
|
/* Clean up. */
|
@@ -40,6 +40,16 @@
|
@@ -276,6 +289,8 @@
|
#include "reload.h"
|
#endif
|
#include "tree-pass.h"
|
bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
|
|
|
|
+
|
+
|
+ ZIP_DEBUG_LINE("RELOAD:Attempting to simplify set",set);
|
|
dreg = true_regnum (SET_DEST (set));
|
|
if (dreg < 0)
|
|
return 0;
|
|
@@ -427,6 +442,7 @@
|
|
/* Array of alternatives, sorted in order of decreasing desirability. */
|
|
int *alternative_order;
|
|
|
|
+ ZIP_DEBUG_LINE("Simplify-Operands", insn);
|
|
extract_constrain_insn (insn);
|
|
|
|
if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
|
|
@@ -519,6 +535,7 @@
|
|
SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
|
|
}
|
|
|
|
+ ZIP_DEBUG_LINE("Simplify-Operands - A", insn);
|
|
alternative_mask preferred = get_preferred_alternatives (insn);
|
|
for (i = 0; i < recog_data.n_operands; i++)
|
|
{
|
|
@@ -617,6 +634,7 @@
|
|
}
|
|
}
|
|
}
|
|
+ ZIP_DEBUG_LINE("Simplify-Operands - B", insn);
|
|
|
|
/* Record all alternatives which are better or equal to the currently
|
|
matching one in the alternative_order array. */
|
|
@@ -666,6 +684,7 @@
|
|
validate_change (insn, recog_data.operand_loc[i],
|
|
gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
|
|
}
|
|
+ ZIP_DEBUG_LINE("Simplify-Operands - C", insn);
|
|
|
|
for (i = recog_data.n_dups - 1; i >= 0; i--)
|
|
{
|
|
@@ -679,6 +698,7 @@
|
|
gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
|
|
}
|
|
|
|
+ ZIP_DEBUG_LINE("Simplify-Operands - C", insn);
|
|
return apply_change_group ();
|
|
}
|
|
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/recog.c gcc-5.3.0-zip/gcc/recog.c
|
|
--- gcc-5.3.0-original/gcc/recog.c 2015-03-20 02:07:30.000000000 -0400
|
|
+++ gcc-5.3.0-zip/gcc/recog.c 2016-04-14 23:19:07.630839483 -0400
|
|
@@ -68,6 +68,15 @@
|
|
#include "df.h"
|
|
#include "insn-codes.h"
|
|
|
|
+// #define DO_ZIP_DEBUGS
|
+// #define DO_ZIP_DEBUGS
|
+#ifdef DO_ZIP_DEBUGS
|
+#ifdef DO_ZIP_DEBUGS
|
+extern void zip_debug_rtx(const_rtx);
|
+#include <stdio.h>
|
+#define ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
|
+#define ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
|
|
+extern void zip_debug_rtx(const_rtx);
|
+#else
|
+#else
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
+#endif
|
+#endif
|
+
|
+
|
+
|
#ifndef STACK_POP_CODE
|
#ifndef STACK_PUSH_CODE
|
#if STACK_GROWS_DOWNWARD
|
#ifdef STACK_GROWS_DOWNWARD
|
#define STACK_POP_CODE POST_INC
|
#define STACK_PUSH_CODE PRE_DEC
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/reload1.c gcc-6.2.0-zip/gcc/reload1.c
|
@@ -2283,6 +2292,7 @@
|
--- gcc-6.2.0/gcc/reload1.c 2016-03-18 04:25:57.000000000 -0400
|
recog_data.n_dups = 0;
|
+++ gcc-6.2.0-zip/gcc/reload1.c 2017-02-06 15:54:21.067740343 -0500
|
recog_data.is_asm = false;
|
@@ -42,6 +42,15 @@
|
|
|
+ZIP_DEBUG_LINE("Extract-insn", insn);
|
|
switch (GET_CODE (body))
|
|
{
|
|
case USE:
|
|
@@ -3671,7 +3681,6 @@
|
|
break;
|
|
|
|
/* The buffer filled to the current maximum, so try to match. */
|
|
-
|
|
pos = peep2_buf_position (peep2_current + peep2_current_count);
|
|
peep2_insn_data[pos].insn = PEEP2_EOB;
|
|
COPY_REG_SET (peep2_insn_data[pos].live_before, live);
|
|
@@ -3704,6 +3713,7 @@
|
|
rebuild_jump_labels (get_insns ());
|
|
if (peep2_do_cleanup_cfg)
|
|
cleanup_cfg (CLEANUP_CFG_CHANGED);
|
|
+
|
|
}
|
|
#endif /* HAVE_peephole2 */
|
|
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/reload1.c gcc-5.3.0-zip/gcc/reload1.c
|
|
--- gcc-5.3.0-original/gcc/reload1.c 2015-01-15 08:28:42.000000000 -0500
|
|
+++ gcc-5.3.0-zip/gcc/reload1.c 2016-11-02 12:07:12.261675054 -0400
|
|
@@ -72,6 +72,14 @@
|
|
#include "dumpfile.h"
|
#include "dumpfile.h"
|
#include "rtl-iter.h"
|
#include "rtl-iter.h"
|
|
|
+// #define DO_ZIP_DEBUGS
|
|
+#ifdef DO_ZIP_DEBUGS
|
+#ifdef DO_ZIP_DEBUGS
|
+extern void zip_debug_rtx(const_rtx);
|
+#include <stdio.h>
|
+#define ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
|
+#define ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
|
|
+extern void zip_debug_rtx(const_rtx);
|
+#else
|
+#else
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
+#endif
|
+#endif
|
+
|
+
|
|
+
|
/* This file contains the reload pass of the compiler, which is
|
/* This file contains the reload pass of the compiler, which is
|
run after register allocation has been done. It checks that
|
run after register allocation has been done. It checks that
|
each insn is valid (operands required to be in registers really
|
each insn is valid (operands required to be in registers really
|
@@ -794,6 +802,20 @@
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/reload.c gcc-6.2.0-zip/gcc/reload.c
|
basic_block bb;
|
--- gcc-6.2.0/gcc/reload.c 2016-02-13 20:37:40.000000000 -0500
|
bool inserted;
|
+++ gcc-6.2.0-zip/gcc/reload.c 2017-03-01 15:46:26.784221658 -0500
|
|
@@ -106,6 +106,15 @@
|
+#ifdef DO_ZIP_DEBUGS
|
#include "addresses.h"
|
+ {
|
#include "params.h"
|
+ fprintf(stderr, "BEFORE-RELOAD\n");
|
|
+ int total_count = 0, current_count = 0;
|
|
+ for (insn = first; insn; insn = NEXT_INSN (insn))
|
|
+ total_count++;
|
|
+ for (insn = first; insn; insn = NEXT_INSN (insn)) {
|
|
+ fprintf(stderr, "B %3d/%3d", current_count++, total_count);
|
|
+ zip_debug_rtx(insn);
|
|
+ }
|
|
+ fprintf(stderr, "BEFORE-RELOAD -- END OF INSTRUCTION LIST\n");
|
|
+ }
|
|
+#endif
|
|
+
|
|
/* Make sure even insns with volatile mem refs are recognizable. */
|
|
init_recog ();
|
|
|
|
@@ -1366,6 +1388,20 @@
|
|
|
|
reload_completed = !failure;
|
|
|
|
+#ifdef DO_ZIP_DEBUGS
|
|
+ {
|
|
+ fprintf(stderr, "AFTER-RELOAD\n");
|
|
+ int total_count = 0, current_count = 0;
|
|
+ for (insn = first; insn; insn = NEXT_INSN (insn))
|
|
+ total_count++;
|
|
+ for (insn = first; insn; insn = NEXT_INSN (insn)) {
|
|
+ fprintf(stderr, "A %3d/%3d", current_count++, total_count);
|
|
+ zip_debug_rtx(insn);
|
|
+ }
|
|
+ fprintf(stderr, "AFTER-RELOAD -- END OF INSTRUCTION LIST\n");
|
|
+ }
|
|
+#endif
|
|
+
|
|
return need_dce;
|
|
}
|
|
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/reload.c gcc-5.3.0-zip/gcc/reload.c
|
|
--- gcc-5.3.0-original/gcc/reload.c 2015-01-15 08:28:42.000000000 -0500
|
|
+++ gcc-5.3.0-zip/gcc/reload.c 2016-11-02 12:07:03.653725635 -0400
|
|
@@ -136,6 +136,15 @@
|
|
#include "target.h"
|
|
#include "ira.h"
|
|
|
|
+// #define DO_ZIP_DEBUGS
|
+// #define DO_ZIP_DEBUGS
|
+#ifdef DO_ZIP_DEBUGS
|
+#ifdef DO_ZIP_DEBUGS
|
+extern void zip_debug_rtx(const_rtx);
|
+#include <stdio.h>
|
+#define ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr, "%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX); }while(0)
|
+#define ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr, "%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX); }while(0)
|
|
+extern void zip_debug_rtx(const_rtx);
|
+#else
|
+#else
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
+#endif
|
+#endif
|
+
|
+
|
+
|
|
/* True if X is a constant that can be forced into the constant pool.
|
/* True if X is a constant that can be forced into the constant pool.
|
MODE is the mode of the operand, or VOIDmode if not known. */
|
MODE is the mode of the operand, or VOIDmode if not known. */
|
#define CONST_POOL_OK_P(MODE, X) \
|
#define CONST_POOL_OK_P(MODE, X) \
|
@@ -2700,6 +2709,8 @@
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/testsuite/lib/target-supports.exp gcc-6.2.0-zip/gcc/testsuite/lib/target-supports.exp
|
hard_regs_live_known = live_known;
|
--- gcc-6.2.0/gcc/testsuite/lib/target-supports.exp 2016-07-05 13:54:02.000000000 -0400
|
static_reload_reg_p = reload_reg_p;
|
+++ gcc-6.2.0-zip/gcc/testsuite/lib/target-supports.exp 2016-12-31 16:59:52.719091392 -0500
|
|
@@ -545,6 +545,11 @@
|
+ZIP_DEBUG_LINE("Find reloads\n", insn);
|
|
+
|
|
/* JUMP_INSNs and CALL_INSNs are not allowed to have any output reloads;
|
|
neither are insns that SET cc0. Insns that use CC0 are not allowed
|
|
to have any input reloads. */
|
|
@@ -2707,8 +2718,17 @@
|
|
no_output_reloads = 1;
|
|
|
|
#ifdef HAVE_cc0
|
|
+ // If the instruction depends upon cc0, such as a branch, if_then_else, or
|
|
+ // cond_exec instruction, we cannot change the input so that the instruction
|
|
+ // relies on another register--cc0 is specific. This requries that the
|
|
+ // references be only cc0 and (const_int 0), rather than allowing other
|
|
+ // registers here as well.
|
|
if (reg_referenced_p (cc0_rtx, PATTERN (insn)))
|
|
no_input_reloads = 1;
|
|
+ // If the result of an instruction is the cc0 register, that cannot
|
|
+ // be changed, therefore no output reloading is allowed. This only
|
|
+ // works if instructions *only* set the cc0 register, and not multiple
|
|
+ // registers.
|
|
if (reg_set_p (cc0_rtx, PATTERN (insn)))
|
|
no_output_reloads = 1;
|
|
#endif
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/target-def.h gcc-5.3.0-zip/gcc/target-def.h
|
|
--- gcc-5.3.0-original/gcc/target-def.h 2015-01-05 07:33:28.000000000 -0500
|
|
+++ gcc-5.3.0-zip/gcc/target-def.h 2016-05-12 15:20:06.896745740 -0400
|
|
@@ -29,24 +29,44 @@
|
|
rather than the .c file, then we need to wrap the default
|
|
definition in a #ifndef, since files include tm.h before this one. */
|
|
|
|
+#ifndef TARGET_ASM_ALIGNED_HI_OP
|
|
#define TARGET_ASM_ALIGNED_HI_OP "\t.short\t"
|
|
+#endif
|
|
+#ifndef TARGET_ASM_ALIGNED_SI_OP
|
|
#define TARGET_ASM_ALIGNED_SI_OP "\t.long\t"
|
|
+#endif
|
|
#define TARGET_ASM_ALIGNED_DI_OP NULL
|
|
#define TARGET_ASM_ALIGNED_TI_OP NULL
|
|
|
|
/* GAS and SYSV4 assemblers accept these. */
|
|
#if defined (OBJECT_FORMAT_ELF)
|
|
-#define TARGET_ASM_UNALIGNED_HI_OP "\t.2byte\t"
|
|
-#define TARGET_ASM_UNALIGNED_SI_OP "\t.4byte\t"
|
|
-#define TARGET_ASM_UNALIGNED_DI_OP "\t.8byte\t"
|
|
-#define TARGET_ASM_UNALIGNED_TI_OP NULL
|
|
+# ifndef TARGET_ASM_UNALIGNED_HI_OP
|
|
+# define TARGET_ASM_UNALIGNED_HI_OP "\t.2byte\t"
|
|
+# endif
|
|
+# ifndef TARGET_ASM_UNALIGNED_SI_OP
|
|
+# define TARGET_ASM_UNALIGNED_SI_OP "\t.4b0te\t"
|
|
+# endif
|
|
+# ifndef TARGET_ASM_UNALIGNED_DI_OP
|
|
+# define TARGET_ASM_UNALIGNED_DI_OP "\t.8byte\t"
|
|
+# endif
|
|
+# define TARGET_ASM_UNALIGNED_TI_OP NULL
|
|
#else
|
|
-#define TARGET_ASM_UNALIGNED_HI_OP NULL
|
|
-#define TARGET_ASM_UNALIGNED_SI_OP NULL
|
|
-#define TARGET_ASM_UNALIGNED_DI_OP NULL
|
|
-#define TARGET_ASM_UNALIGNED_TI_OP NULL
|
|
+# ifndef TARGET_ASM_UNALIGNED_HI_OP
|
|
+# define TARGET_ASM_UNALIGNED_HI_OP NULL
|
|
+# endif
|
|
+# ifndef TARGET_ASM_UNALIGNED_SI_OP
|
|
+# define TARGET_ASM_UNALIGNED_SI_OP NULL
|
|
+# endif
|
|
+# ifndef TARGET_ASM_UNALIGNED_DI_OP
|
|
+# define TARGET_ASM_UNALIGNED_DI_OP NULL
|
|
+# endif
|
|
+# define TARGET_ASM_UNALIGNED_TI_OP NULL
|
|
#endif /* OBJECT_FORMAT_ELF */
|
|
|
|
+#ifndef TARGET_ASM_UNALIGNED_TI_OP
|
|
+#define TARGET_ASM_UNALIGNED_TI_OP NULL
|
|
+#endif
|
|
+
|
|
#if !defined(TARGET_ASM_CONSTRUCTOR) && !defined(USE_COLLECT2)
|
|
# ifdef CTORS_SECTION_ASM_OP
|
|
# define TARGET_ASM_CONSTRUCTOR default_ctor_section_asm_out_constructor
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/testsuite/lib/target-supports.exp gcc-5.3.0-zip/gcc/testsuite/lib/target-supports.exp
|
|
--- gcc-5.3.0-original/gcc/testsuite/lib/target-supports.exp 2015-11-26 05:10:58.000000000 -0500
|
|
+++ gcc-5.3.0-zip/gcc/testsuite/lib/target-supports.exp 2016-01-30 15:14:21.620586694 -0500
|
|
@@ -503,6 +503,11 @@
|
|
return 0
|
return 0
|
}
|
}
|
|
|
+ # Zip CPU doesn't support profiling (yet)
|
+ # ZipCPU doesnt support profiling (yet).
|
+ if { [istarget zip*] }
|
+ if { [istarget zip*] } {
|
+ return 0
|
+ return 0
|
+ }
|
+ }
|
+
|
+
|
# MinGW does not support -p.
|
# cygwin does not support -p.
|
if { [istarget *-*-mingw*] && $test_what == "-p" } {
|
if { [istarget *-*-cygwin*] && $test_what == "-p" } {
|
return 0
|
return 0
|
@@ -986,6 +991,12 @@
|
@@ -1090,6 +1095,12 @@
|
}]
|
}]
|
}
|
}
|
|
|
+ # No real hardware FPU support for ZipCPU yet--even though the instruction
|
+ # No real hardware FPU support for ZipCPU yet --- even though the
|
+ # set supports it, the CPU just isn't ready yet.
|
+ # instruction set supports it, the CPU just isn't ready (yet).
|
+ if { [istarget zip*-*-*] } {
|
+ if { [istarget zip*] } {
|
+ return 0
|
+ return 0
|
+ }
|
+ }
|
+
|
+
|
# This proc is actually checking the availabilty of FPU
|
# This proc is actually checking the availabilty of FPU
|
# support for doubles, so on the RX we must fail if the
|
# support for doubles, so on the RX we must fail if the
|
# 64-bit double multilib has been selected.
|
# 64-bit double multilib has been selected.
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/tree-ssa-math-opts.c gcc-5.3.0-zip/gcc/tree-ssa-math-opts.c
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/tree-ssa-math-opts.c gcc-6.2.0-zip/gcc/tree-ssa-math-opts.c
|
--- gcc-5.3.0-original/gcc/tree-ssa-math-opts.c 2015-08-11 03:58:07.000000000 -0400
|
--- gcc-6.2.0/gcc/tree-ssa-math-opts.c 2016-04-04 11:42:19.000000000 -0400
|
+++ gcc-5.3.0-zip/gcc/tree-ssa-math-opts.c 2016-02-12 11:21:11.309149239 -0500
|
+++ gcc-6.2.0-zip/gcc/tree-ssa-math-opts.c 2016-12-31 17:02:24.405602214 -0500
|
@@ -972,7 +972,7 @@
|
@@ -983,7 +983,7 @@
|
{
|
{
|
if (val & 1)
|
if (val & 1)
|
{
|
{
|
- digit = val & ((1 << POWI_WINDOW_SIZE) - 1);
|
- digit = val & ((1 << POWI_WINDOW_SIZE) - 1);
|
+ digit = val & ((1l << POWI_WINDOW_SIZE) - 1);
|
+ digit = val & ((1l << POWI_WINDOW_SIZE) - 1);
|
result += powi_lookup_cost (digit, cache)
|
result += powi_lookup_cost (digit, cache)
|
+ POWI_WINDOW_SIZE + 1;
|
+ POWI_WINDOW_SIZE + 1;
|
val >>= POWI_WINDOW_SIZE;
|
val >>= POWI_WINDOW_SIZE;
|
@@ -1012,7 +1012,7 @@
|
@@ -1023,7 +1023,7 @@
|
}
|
}
|
else if (n & 1)
|
else if (n & 1)
|
{
|
{
|
- digit = n & ((1 << POWI_WINDOW_SIZE) - 1);
|
- digit = n & ((1 << POWI_WINDOW_SIZE) - 1);
|
+ digit = n & ((1l << POWI_WINDOW_SIZE) - 1);
|
+ digit = n & ((1l << POWI_WINDOW_SIZE) - 1);
|
op0 = powi_as_mults_1 (gsi, loc, type, n - digit, cache);
|
op0 = powi_as_mults_1 (gsi, loc, type, n - digit, cache);
|
op1 = powi_as_mults_1 (gsi, loc, type, digit, cache);
|
op1 = powi_as_mults_1 (gsi, loc, type, digit, cache);
|
}
|
}
|
@@ -1651,7 +1651,7 @@
|
@@ -1957,7 +1957,7 @@
|
};
|
};
|
|
|
#define BITS_PER_MARKER 8
|
#define BITS_PER_MARKER 8
|
-#define MARKER_MASK ((1 << BITS_PER_MARKER) - 1)
|
-#define MARKER_MASK ((1 << BITS_PER_MARKER) - 1)
|
+#define MARKER_MASK ((1l << BITS_PER_MARKER) - 1)
|
+#define MARKER_MASK ((1l << BITS_PER_MARKER) - 1)
|
#define MARKER_BYTE_UNKNOWN MARKER_MASK
|
#define MARKER_BYTE_UNKNOWN MARKER_MASK
|
#define HEAD_MARKER(n, size) \
|
#define HEAD_MARKER(n, size) \
|
((n) & ((uint64_t) MARKER_MASK << (((size) - 1) * BITS_PER_MARKER)))
|
((n) & ((uint64_t) MARKER_MASK << (((size) - 1) * BITS_PER_MARKER)))
|
@@ -1687,7 +1687,7 @@
|
@@ -1993,7 +1993,7 @@
|
/* Zero out the extra bits of N in order to avoid them being shifted
|
/* Zero out the extra bits of N in order to avoid them being shifted
|
into the significant bits. */
|
into the significant bits. */
|
if (size < 64 / BITS_PER_MARKER)
|
if (size < 64 / BITS_PER_MARKER)
|
- n->n &= ((uint64_t) 1 << (size * BITS_PER_MARKER)) - 1;
|
- n->n &= ((uint64_t) 1 << (size * BITS_PER_MARKER)) - 1;
|
+ n->n &= ((uint64_t) 1l << (size * BITS_PER_MARKER)) - 1;
|
+ n->n &= ((uint64_t) 1l << (size * BITS_PER_MARKER)) - 1;
|
|
|
switch (code)
|
switch (code)
|
{
|
{
|
@@ -1714,7 +1714,7 @@
|
@@ -2020,7 +2020,7 @@
|
}
|
}
|
/* Zero unused bits for size. */
|
/* Zero unused bits for size. */
|
if (size < 64 / BITS_PER_MARKER)
|
if (size < 64 / BITS_PER_MARKER)
|
- n->n &= ((uint64_t) 1 << (size * BITS_PER_MARKER)) - 1;
|
- n->n &= ((uint64_t) 1 << (size * BITS_PER_MARKER)) - 1;
|
+ n->n &= ((uint64_t) 1l << (size * BITS_PER_MARKER)) - 1;
|
+ n->n &= ((uint64_t) 1l << (size * BITS_PER_MARKER)) - 1;
|
return true;
|
return true;
|
}
|
}
|
|
|
@@ -1761,7 +1761,7 @@
|
@@ -2067,7 +2067,7 @@
|
n->n = CMPNOP;
|
n->n = CMPNOP;
|
|
|
if (size < 64 / BITS_PER_MARKER)
|
if (size < 64 / BITS_PER_MARKER)
|
- n->n &= ((uint64_t) 1 << (size * BITS_PER_MARKER)) - 1;
|
- n->n &= ((uint64_t) 1 << (size * BITS_PER_MARKER)) - 1;
|
+ n->n &= ((uint64_t) 1l << (size * BITS_PER_MARKER)) - 1;
|
+ n->n &= ((uint64_t) 1l << (size * BITS_PER_MARKER)) - 1;
|
|
|
return true;
|
return true;
|
}
|
}
|
@@ -2020,7 +2020,7 @@
|
@@ -2372,7 +2372,7 @@
|
{
|
|
int i, size = TYPE_PRECISION (n->type) / BITS_PER_UNIT;
|
|
uint64_t val = int_cst_value (rhs2), mask = 0;
|
|
- uint64_t tmp = (1 << BITS_PER_UNIT) - 1;
|
|
+ uint64_t tmp = (1l << BITS_PER_UNIT) - 1;
|
|
|
|
/* Only constants masking full bytes are allowed. */
|
|
for (i = 0; i < size; i++, tmp <<= BITS_PER_UNIT)
|
|
@@ -2064,7 +2064,7 @@
|
|
{
|
{
|
/* If STMT casts to a smaller type mask out the bits not
|
/* If STMT casts to a smaller type mask out the bits not
|
belonging to the target type. */
|
belonging to the target type. */
|
- n->n &= ((uint64_t) 1 << (type_size * BITS_PER_MARKER)) - 1;
|
- n->n &= ((uint64_t) 1 << (type_size * BITS_PER_MARKER)) - 1;
|
+ n->n &= ((uint64_t) 1l << (type_size * BITS_PER_MARKER)) - 1;
|
+ n->n &= ((uint64_t) 1l << (type_size * BITS_PER_MARKER)) - 1;
|
}
|
}
|
n->type = type;
|
n->type = type;
|
if (!n->base_addr)
|
if (!n->base_addr)
|
@@ -2177,7 +2177,7 @@
|
@@ -2489,7 +2489,7 @@
|
{
|
{
|
uint64_t mask;
|
uint64_t mask;
|
|
|
- mask = ((uint64_t) 1 << (n->range * BITS_PER_MARKER)) - 1;
|
- mask = ((uint64_t) 1 << (n->range * BITS_PER_MARKER)) - 1;
|
+ mask = ((uint64_t) 1l << (n->range * BITS_PER_MARKER)) - 1;
|
+ mask = ((uint64_t) 1l << (n->range * BITS_PER_MARKER)) - 1;
|
cmpxchg >>= (64 / BITS_PER_MARKER - n->range) * BITS_PER_MARKER;
|
cmpxchg >>= (64 / BITS_PER_MARKER - n->range) * BITS_PER_MARKER;
|
cmpnop &= mask;
|
cmpnop &= mask;
|
}
|
}
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/var-tracking.c gcc-5.3.0-zip/gcc/var-tracking.c
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/varasm.c gcc-6.2.0-zip/gcc/varasm.c
|
--- gcc-5.3.0-original/gcc/var-tracking.c 2015-03-26 09:19:00.000000000 -0400
|
--- gcc-6.2.0/gcc/varasm.c 2016-03-31 11:30:33.000000000 -0400
|
+++ gcc-5.3.0-zip/gcc/var-tracking.c 2016-03-31 18:55:03.584197958 -0400
|
+++ gcc-6.2.0-zip/gcc/varasm.c 2016-12-31 17:03:08.629193673 -0500
|
@@ -143,6 +143,13 @@
|
@@ -2771,7 +2771,7 @@
|
#include "rtl-iter.h"
|
|
#include "fibonacci_heap.h"
|
/* Put out the first word with the specified alignment. */
|
|
if (reverse)
|
+#ifdef DO_ZIP_DEBUGS
|
- elt = flip_storage_order (SImode, gen_int_mode (data[nelts - 1], SImode));
|
+#include <stdio.h>
|
+ elt = flip_storage_order (word_mode, gen_int_mode (data[nelts - 1], SImode));
|
+extern void zip_debug_rtx(const_rtx);
|
else
|
+#define ZIP_DEBUG_LINE(STR,RTX) do {fprintf(stderr,"%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
|
elt = GEN_INT (data[0]);
|
+#else
|
assemble_integer (elt, MIN (nunits, units_per), align, 1);
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
@@ -2783,7 +2783,7 @@
|
+#endif
|
for (int i = 1; i < nelts; i++)
|
typedef fibonacci_heap <long, basic_block_def> bb_heap_t;
|
|
typedef fibonacci_node <long, basic_block_def> bb_heap_node_t;
|
|
|
|
@@ -6356,6 +6363,7 @@
|
|
machine_mode indmode
|
|
= TYPE_MODE (TREE_TYPE (argtype));
|
|
rtx mem = gen_rtx_MEM (indmode, x);
|
|
+ ZIP_DEBUG_LINE("Var-tracking mem-ref", mem);
|
|
cselib_val *val = cselib_lookup (mem, indmode, 0, VOIDmode);
|
|
if (val && cselib_preserved_value_p (val))
|
|
{
|
{
|
@@ -6462,12 +6470,14 @@
|
if (reverse)
|
machine_mode mode
|
- elt = flip_storage_order (SImode,
|
= TYPE_MODE (TREE_TYPE (OBJ_TYPE_REF_EXPR (obj_type_ref)));
|
+ elt = flip_storage_order (word_mode,
|
rtx clobbered = gen_rtx_MEM (mode, this_arg);
|
gen_int_mode (data[nelts - 1 - i], SImode));
|
+ ZIP_DEBUG_LINE("Var-tracking mem-ref/clobbered", clobbered);
|
else
|
HOST_WIDE_INT token
|
elt = GEN_INT (data[i]);
|
= tree_to_shwi (OBJ_TYPE_REF_TOKEN (obj_type_ref));
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/libgcc/config/zip/sfp-machine.h gcc-6.2.0-zip/libgcc/config/zip/sfp-machine.h
|
if (token)
|
--- gcc-6.2.0/libgcc/config/zip/sfp-machine.h 1969-12-31 19:00:00.000000000 -0500
|
clobbered = plus_constant (mode, clobbered,
|
+++ gcc-6.2.0-zip/libgcc/config/zip/sfp-machine.h 2017-01-27 12:27:05.094921759 -0500
|
token * GET_MODE_SIZE (mode));
|
@@ -0,0 +1,53 @@
|
clobbered = gen_rtx_MEM (mode, clobbered);
|
+#ifndef ZIP_SFP_MACHINE_H
|
+ ZIP_DEBUG_LINE("Var-tracking mem-ref/clobbered-2", clobbered);
|
+#define ZIP_SFP_MACHINE_H
|
x = gen_rtx_CONCAT (mode, gen_rtx_CLOBBER (VOIDmode, pc_rtx), clobbered);
|
+
|
call_arguments
|
+#define __BIG_ENDIAN 4321
|
= gen_rtx_EXPR_LIST (VOIDmode, x, call_arguments);
|
+#define __BYTE_ORDER __BIG_ENDIAN
|
@@ -9790,6 +9800,7 @@
|
+
|
machine_mode indmode
|
+#define _FP_W_TYPE_SIZE 32
|
= TYPE_MODE (TREE_TYPE (TREE_TYPE (parm)));
|
+#define _FP_W_TYPE unsigned int
|
rtx mem = gen_rtx_MEM (indmode, incoming);
|
+#define _FP_WS_TYPE signed int
|
+ ZIP_DEBUG_LINE("Var-tracking mem-ref/incoming", incoming);
|
+#define _FP_I_TYPE long
|
cselib_val *val = cselib_lookup_from_insn (mem, indmode, true,
|
+
|
VOIDmode,
|
+#define _FP_MUL_MEAT_S(R,X,Y) _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm)
|
get_insns ());
|
+#define _FP_MUL_MEAT_D(R,X,Y) _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/libgcc/config.host gcc-5.3.0-zip/libgcc/config.host
|
+
|
--- gcc-5.3.0-original/libgcc/config.host 2015-10-01 08:01:18.000000000 -0400
|
+#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_loop(S,R,X,Y)
|
+++ gcc-5.3.0-zip/libgcc/config.host 2016-11-10 07:09:05.510509734 -0500
|
+#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y)
|
@@ -195,6 +195,9 @@
|
+
|
|
+#define _FP_NANFRAC_S ((_FP_QNANBIT_S<<1)-1)
|
|
+#define _FP_NANFRAC_D ((_FP_QNANBIT_D<<1)-1), -1
|
|
+
|
|
+#define _FP_QNANNEGATEDP 0
|
|
+#define _FP_NANSIGN_S 0
|
|
+#define _FP_NANSIGN_D 0
|
|
+#define _FP_KEEPNANFRACP 1
|
|
+
|
|
+/* Someone please check this. --- copied from one of many other places */
|
|
+#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
|
|
+ do { \
|
|
+ if ((_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs) \
|
|
+ && !(_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs)) \
|
|
+ { \
|
|
+ R##_s = Y##_s; \
|
|
+ _FP_FRAC_COPY_##wc(R,Y); \
|
|
+ } \
|
|
+ else \
|
|
+ { \
|
|
+ R##_s = X##_s; \
|
|
+ _FP_FRAC_COPY_##wc(R,X); \
|
|
+ } \
|
|
+ R##_c = FP_CLS_NAN; \
|
|
+ } while (0)
|
|
+
|
|
+/* Not checked. */
|
|
+#define _FP_TININESS_AFTER_ROUNDING 0
|
|
+
|
|
+#ifndef __BYTE_ORDER
|
|
+#define __BYTE_ORDER __BIG_ENDIAN
|
|
+#endif
|
|
+
|
|
+#define strong_alias(name, aliasname) _stong_alias(name, aliasname)
|
|
+#define _strong_alias(name, aliasname) \
|
|
+ extern __typeof(name) aliasname __attribute__ ((alias (#name)));
|
|
+#endif
|
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/libgcc/config.host gcc-6.2.0-zip/libgcc/config.host
|
|
--- gcc-6.2.0/libgcc/config.host 2016-05-17 02:15:52.000000000 -0400
|
|
+++ gcc-6.2.0-zip/libgcc/config.host 2017-01-27 12:28:31.470410459 -0500
|
|
@@ -197,6 +197,9 @@
|
tic6x-*-*)
|
tic6x-*-*)
|
cpu_type=c6x
|
cpu_type=c6x
|
;;
|
;;
|
+zip*)
|
+zip*)
|
+ cpu_type=zip
|
+ cpu_type=zip
|
+ ;;
|
+ ;;
|
esac
|
esac
|
|
|
# Common parts for widely ported systems.
|
# Common parts for widely ported systems.
|
@@ -1296,6 +1299,9 @@
|
@@ -1328,6 +1331,10 @@
|
tmake_file="$tmake_file nvptx/t-nvptx"
|
tmake_file="$tmake_file nvptx/t-nvptx"
|
extra_parts="crt0.o"
|
extra_parts="crt0.o"
|
;;
|
;;
|
+zip*)
|
+zip*)
|
+ tmake_file="${tmake_file} t-softfp-sfdf t-softfp"
|
+ tmake_file="$tmake_file t-softfp-sfdf t-softfp-excl t-softfp"
|
|
+ # extra_parts="crt0.o"
|
+ ;;
|
+ ;;
|
*)
|
*)
|
echo "*** Configuration ${host} not supported" 1>&2
|
echo "*** Configuration ${host} not supported" 1>&2
|
exit 1
|
exit 1
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/libgcc/libgcc2.h gcc-5.3.0-zip/libgcc/libgcc2.h
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/libgcc/configure gcc-6.2.0-zip/libgcc/configure
|
--- gcc-5.3.0-original/libgcc/libgcc2.h 2015-01-05 07:33:28.000000000 -0500
|
--- gcc-6.2.0/libgcc/configure 2016-04-11 15:45:35.000000000 -0400
|
+++ gcc-5.3.0-zip/libgcc/libgcc2.h 2016-11-19 08:23:48.085519135 -0500
|
+++ gcc-6.2.0-zip/libgcc/configure 2017-01-27 15:53:43.141531475 -0500
|
@@ -113,10 +113,10 @@
|
@@ -3805,13 +3805,13 @@
|
because the sizes for those types can be configured to be anything.
|
CFLAGS=$ac_save_CFLAGS
|
Instead we use the following special type names. */
|
elif test $ac_cv_prog_cc_g = yes; then
|
|
if test "$GCC" = yes; then
|
-typedef int QItype __attribute__ ((mode (QI)));
|
- CFLAGS="-g -O2"
|
-typedef unsigned int UQItype __attribute__ ((mode (QI)));
|
+ CFLAGS="-O3"
|
-typedef int HItype __attribute__ ((mode (HI)));
|
else
|
-typedef unsigned int UHItype __attribute__ ((mode (HI)));
|
CFLAGS="-g"
|
+typedef int QItype __attribute__ ((mode (SI)));
|
fi
|
+typedef unsigned int UQItype __attribute__ ((mode (SI)));
|
else
|
+typedef int HItype __attribute__ ((mode (SI)));
|
if test "$GCC" = yes; then
|
+typedef unsigned int UHItype __attribute__ ((mode (SI)));
|
- CFLAGS="-O2"
|
#if MIN_UNITS_PER_WORD > 1
|
+ CFLAGS="-O3"
|
/* These typedefs are usually forbidden on dsp's with UNITS_PER_WORD 1. */
|
else
|
typedef int SItype __attribute__ ((mode (SI)));
|
CFLAGS=
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/libgomp/configure.tgt gcc-5.3.0-zip/libgomp/configure.tgt
|
fi
|
--- gcc-5.3.0-original/libgomp/configure.tgt 2015-03-13 06:57:07.000000000 -0400
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/libgcc/Makefile.in gcc-6.2.0-zip/libgcc/Makefile.in
|
+++ gcc-5.3.0-zip/libgomp/configure.tgt 2016-01-30 15:16:51.323521641 -0500
|
--- gcc-6.2.0/libgcc/Makefile.in 2016-02-25 07:23:52.000000000 -0500
|
@@ -150,6 +150,9 @@
|
+++ gcc-6.2.0-zip/libgcc/Makefile.in 2017-01-27 15:54:32.241240828 -0500
|
# Need to link with -lpthread so libgomp.so is self-contained.
|
@@ -229,8 +229,8 @@
|
XLDFLAGS="${XLDFLAGS} -lpthread"
|
|
|
# Options to use when compiling libgcc2.a.
|
|
#
|
|
-LIBGCC2_DEBUG_CFLAGS = -g
|
|
-LIBGCC2_CFLAGS = -O2 $(LIBGCC2_INCLUDES) $(GCC_CFLAGS) $(HOST_LIBGCC2_CFLAGS) \
|
|
+LIBGCC2_DEBUG_CFLAGS =
|
|
+LIBGCC2_CFLAGS = -O3 $(LIBGCC2_INCLUDES) $(GCC_CFLAGS) $(HOST_LIBGCC2_CFLAGS) \
|
|
$(LIBGCC2_DEBUG_CFLAGS) -DIN_LIBGCC2 \
|
|
-fbuilding-libgcc -fno-stack-protector \
|
|
$(INHIBIT_LIBC_CFLAGS)
|
|
@@ -284,7 +284,7 @@
|
|
$(INCLUDES) @set_have_cc_tls@ @set_use_emutls@
|
|
|
|
# Options to use when compiling crtbegin/end.
|
|
-CRTSTUFF_CFLAGS = -O2 $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -g0 \
|
|
+CRTSTUFF_CFLAGS = -O3 $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -g0 \
|
|
$(NO_PIE_CFLAGS) -finhibit-size-directive -fno-inline -fno-exceptions \
|
|
-fno-zero-initialized-in-bss -fno-toplevel-reorder -fno-tree-vectorize \
|
|
-fbuilding-libgcc -fno-stack-protector $(FORCE_EXPLICIT_EH_REGISTRY) \
|
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/libgomp/configure.tgt gcc-6.2.0-zip/libgomp/configure.tgt
|
|
--- gcc-6.2.0/libgomp/configure.tgt 2015-09-03 12:20:35.000000000 -0400
|
|
+++ gcc-6.2.0-zip/libgomp/configure.tgt 2016-12-31 17:06:26.795473062 -0500
|
|
@@ -161,6 +161,9 @@
|
|
config_path="rtems posix"
|
|
fi
|
;;
|
;;
|
+ zip*)
|
+ zip*)
|
+ config_path="bsd posix"
|
+ config_path="bsd posix"
|
+ ;;
|
+ ;;
|
|
|
