| Line 46... |
Line 46... |
; http://www.gnu.org/licenses/gpl.html
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; http://www.gnu.org/licenses/gpl.html
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;
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;
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;
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;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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;
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// #include "sys.i"
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#include "sys.i"
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sys.bus equ 0xc0000000
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sys.bus equ 0xc0000000
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sys.breaken equ 0x080
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sys.breaken equ 0x080
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sys.step equ 0x040
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sys.step equ 0x040
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sys.gie equ 0x020
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sys.gie equ 0x020
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sys.sleep equ 0x010
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sys.sleep equ 0x010
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sys.ccv equ 0x008
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sys.ccv equ 0x008
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sys.ccn equ 0x004
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sys.ccn equ 0x004
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sys.ccc equ 0x002
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sys.ccc equ 0x002
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sys.ccz equ 0x001
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sys.ccz equ 0x001
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sys.cctrap equ 0x200
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sys.bu.pic equ 0x000
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sys.bu.pic equ 0x000
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sys.bus.wdt equ 0x001
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sys.bus.wdt equ 0x001
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sys.bus.cache equ 0x002
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sys.bus.cache equ 0x002
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sys.bus.ctrpic equ 0x003
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sys.bus.ctrpic equ 0x003
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sys.bus.tma equ 0x004
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sys.bus.tma equ 0x004
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| Line 73... |
Line 74... |
sys.bus.utask equ 0x00c
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sys.bus.utask equ 0x00c
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sys.bus.upstl equ 0x00d
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sys.bus.upstl equ 0x00d
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sys.bus.uastl equ 0x00e
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sys.bus.uastl equ 0x00e
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sys.bus.ustl equ 0x00f
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sys.bus.ustl equ 0x00f
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#define DO_TEST_ASSEMBLER
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#define DO_TEST_ASSEMBLER
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#define BREAK_TEST
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#define OVERFLOW_TEST
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#define CARRY_TEST
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#define LOOP_TEST
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#define SHIFT_TEST
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#define TRAP_TEST
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#define MPY_TEST
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// #define PUSH_TEST
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test:
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test:
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#ifdef DO_TEST_ASSEMBLER
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#ifdef DO_TEST_ASSEMBLER
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; We start out by testing our assembler. We give it some instructions, which
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; We start out by testing our assembler. We give it some instructions, which
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; are then manually checked by disassembling/dumping the result and making
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; are then manually checked by disassembling/dumping the result and making
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; certain they match. This is not an automated test, but it is an important
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; certain they match. This is not an automated test, but it is an important
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; one.
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; one.
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noop
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noop
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bra continue_test_with_testable_instructions
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bra continue_test_with_testable_instructions
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break
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break
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wait
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wait
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break
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busy
|
busy
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rtu
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rtu
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continue_test_with_testable_instructions:
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continue_test_with_testable_instructions:
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; Now, let's place the assembler into a known state
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; Now, let's place the assembler into a known state
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clr r0
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clr r0
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| Line 204... |
Line 214... |
bnz test_failure
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bnz test_failure
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lod junk_address(pc),r5 ; Test loads with pc-relative addressing
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lod junk_address(pc),r5 ; Test loads with pc-relative addressing
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lod junk_address(pc),r6
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lod junk_address(pc),r6
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cmp r5,r6
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cmp r5,r6
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bnz test_failure
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bnz test_failure
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; Now, let's test whether or not our LSR and carry flags work
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ldi -1,r0 ; First test: shifting all the way should yield zero
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lsr 32,r0
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cmp 0,r0
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bnz test_failure
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ldi -1,r0 ; Second test: anything greater than zero should set
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lsr 0,r0 ; the carry flag
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bc test_failure
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lsr 1,r0
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tst sys.ccc,cc
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bz test_failure
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lsr 31,r0
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tst sys.ccc,cc
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bz test_failure
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lsr 1,r0
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bc test_failure
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; Now repeat the above tests, looking to see whether or not ASR works
|
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ldi -1,r0
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asr 32,r0
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cmp -1,r0
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bnz test_failure
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ldi -1,r0
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asr 0,r0
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bc test_failure
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cmp -1,r0
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bnz test_failure
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asr 1,r0
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tst sys.ccc,r14
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bz test_failure
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asr 30,r0
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tst sys.ccc,r14
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bz test_failure
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#endif
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#endif
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|
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#ifdef NOONE // Testing comments after ifdef
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#ifdef NOONE // Testing comments after ifdef
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#else ; After else
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#else ; After else
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#endif /* and after endif */
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#endif /* and after endif */
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|
|
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#ifdef BREAK_TEST
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breaktest:
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bra breaksupervisor
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breakuser:
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clr r0
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mov 1+r0,r1
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mov 1+r1,r2
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mov 1+r2,r3
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break ; At address 0x0100097
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mov 1+r4,r5
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mov 1+r5,r6
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clr cc
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busy
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breaksupervisor:
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ldi -1,r0
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mov breakuser(pc),upc
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rtu ; Should just keep returning immediately
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mov upc,r0
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rtu
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rtu
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mov upc,r1
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cmp r0,r1
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bnz test_failure
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#endif
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|
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#ifdef TRAP_TEST
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traptest:
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bra traptest_supervisor
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busy
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traptest_user:
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trap 0
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busy
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traptest_supervisor:
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mov traptest_user(pc),upc
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rtu
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mov cc,r0
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tst sys.cctrap,r0
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bz test_failure
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#endif
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|
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testbench:
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testbench:
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// Let's build a software test bench.
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// Let's build a software test bench.
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ldi $c0000000h,r12 ; Set R12 to point to our peripheral address
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ldi $c0000000h,r12 ; Set R12 to point to our peripheral address
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mov r12,ur12
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mov r12,ur12
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mov test_start(pc),upc
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mov test_start(pc),upc
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ldi 0x8000ffff,r0 ; Clear interrupts, turn all vectors off
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ldi 0x8000ffff,r0 ; Clear interrupts, turn all vectors off
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sto r0,(r12)
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sto r0,(r12)
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rtu
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rtu
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mov ucc,r0
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mov ucc,r0
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tst -256,r0
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cmp sys.cctrap,r0
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bnz test_failure
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bnz test_failure
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halt
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halt
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// Go into an infinite loop if the trap fails
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// Go into an infinite loop if the trap fails
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// Permanent loop instruction -- a busy halt if you will
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// Permanent loop instruction -- a busy halt if you will
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test_failure:
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test_failure:
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| Line 267... |
Line 286... |
; Test LDI to PC
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; Test LDI to PC
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; Some data registers
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; Some data registers
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test_data:
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test_data:
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.dat __here__+0x0100000+5
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.dat __here__+0x0100000+5
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test_start:
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test_start:
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ldi $0x0100,r11
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ldi $0x01000,r11
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lod test_data+pc,pc
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lod test_data+pc,pc
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clr r11
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clr r11
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noop
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noop
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cmp $0,r11
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cmp $0,r11
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trap.z r11
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trap.z r11
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add $1,r0
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add $1,r0
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add $1,r0
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add $1,r0
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|
|
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#ifdef OVERFLOW_TEST
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// Let's test whether overflow works
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// Let's test whether overflow works
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ldi $0x0200,r11
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ldi $0x02000,r11
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ldi $-1,r0
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ldi $-1,r0
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lsr $1,r0
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lsr $1,r0
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add $1,r0
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add $1,r0
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bv first_overflow_passes
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bv first_overflow_passes
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trap r11
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trap r11
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first_overflow_passes:
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first_overflow_passes:
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// Overflow set from subtraction
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// Overflow set from subtraction
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ldi $0x0300,r11
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ldi $0x03000,r11
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ldi $1,r0
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ldi $1,r0
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rol $31,r0 ; rol $31,r0
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rol $31,r0 ; rol $31,r0
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sub $1,r0
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sub $1,r0
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bv subtraction_overflow_passes
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bv subtraction_overflow_passes
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trap r11
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trap r11
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subtraction_overflow_passes:
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subtraction_overflow_passes:
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// Overflow set from LSR
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// Overflow set from LSR
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ldi $0x0400,r11
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ldi $0x04000,r11
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ldi $1,r0
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ldi $1,r0
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rol $31,r0 ; rol $31,r0
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rol $31,r0 ; rol $31,r0
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lsr $1,r0
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lsr $1,r0
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bv lsr_overflow_passes
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bv lsr_overflow_passes
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trap r11
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trap r11
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lsr_overflow_passes:
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lsr_overflow_passes:
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// Overflow set from LSL
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// Overflow set from LSL
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ldi $0x0500,r11
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ldi $0x05000,r11
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ldi $1,r0
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ldi $1,r0
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rol $30,r0
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rol $30,r0
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lsl $1,r0
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lsl $1,r0
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bv lsl_overflow_passes
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bv lsl_overflow_passes
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trap r11
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trap r11
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lsl_overflow_passes:
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lsl_overflow_passes:
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// Overflow set from LSL, negative to positive
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// Overflow set from LSL, negative to positive
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ldi $0x0600,r11
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ldi $0x06000,r11
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ldi $1,r0
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ldi $1,r0
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rol $31,r0
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rol $31,r0
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lsl $1,r0
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lsl $1,r0
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bv second_lsl_overflow_passes
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bv second_lsl_overflow_passes
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trap r11
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trap r11
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#endif // OVERFLOW_TEST
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#ifdef CARRY_TEST
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second_lsl_overflow_passes:
|
second_lsl_overflow_passes:
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// Test carry
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// Test carry
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ldi $0x0700,r11
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ldi $0x07000,r11
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ldi $-1,r0
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ldi $-1,r0
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add $1,r0
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add $1,r0
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tst $2,cc
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tst $2,cc
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trap.z r11
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trap.z r11
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// and carry from subtraction
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// and carry from subtraction
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ldi $0x0800,r11
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ldi $0x08000,r11
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clr r0
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sub $1,r0
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sub $1,r0
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tst $2,cc
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tst $2,cc
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trap.z r11
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trap.z r11
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#endif
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|
|
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#ifdef LOOP_TEST
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|
|
// Let's try a loop: for i=0; i<5; i++)
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// Let's try a loop: for i=0; i<5; i++)
|
// We'll use R0=i, Immediates for 5
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// We'll use R0=i, Immediates for 5
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ldi $0x0800,r11
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ldi $0x09000,r11
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clr r0
|
clr r0
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for_loop:
|
for_loop:
|
noop
|
noop
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add $1,r0
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add $1,r0
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cmp $5,r0
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cmp $5,r0
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| Line 344... |
Line 370... |
// implement, and this one is no different: 2 loop instructions
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// implement, and this one is no different: 2 loop instructions
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// (minus setup instructions) vs 3 from before.
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// (minus setup instructions) vs 3 from before.
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// R0 = 5; (from before)
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// R0 = 5; (from before)
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// do {
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// do {
|
// } while (R0 > 0);
|
// } while (R0 > 0);
|
ldi $0x0900,r11
|
ldi $0x0a000,r11
|
bgt_loop:
|
bgt_loop:
|
noop
|
noop
|
sub $1,r0
|
sub $1,r0
|
bgt bgt_loop
|
bgt bgt_loop
|
|
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| Line 366... |
Line 392... |
// Let's try the reverse loop again, only this time we'll store our
|
// Let's try the reverse loop again, only this time we'll store our
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// loop variable in memory.
|
// loop variable in memory.
|
// R0 = 5; (from before)
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// R0 = 5; (from before)
|
// do {
|
// do {
|
// } while (R0 > 0);
|
// } while (R0 > 0);
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ldi $0x0a00,r11
|
ldi $0x0b000,r11
|
bra mem_loop_test
|
bra mem_loop_test
|
loop_var:
|
loop_var:
|
.dat 0
|
.dat 0
|
mem_loop_test:
|
mem_loop_test:
|
mov loop_var(pc),r1
|
mov loop_var(pc),r1
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| Line 384... |
Line 410... |
sub $1,r0
|
sub $1,r0
|
sto r0,(r1)
|
sto r0,(r1)
|
bgt mem_loop
|
bgt mem_loop
|
cmp $5,r2
|
cmp $5,r2
|
trap.ne r11
|
trap.ne r11
|
|
#endif
|
|
|
|
#ifdef SHIFT_TEST
|
|
; Now, let's test whether or not our LSR and carry flags work
|
|
ldi $0x0c000,r11
|
|
ldi -1,r0 ; First test: shifting all the way should yield zero
|
|
lsr 32,r0
|
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cmp 0,r0
|
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bnz test_failure
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ldi -1,r0 ; Second test: anything greater than zero should set
|
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lsr 0,r0 ; the carry flag
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bc test_failure
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lsr 1,r0
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tst sys.ccc,cc ; FAILS HERE!!! @0x010007c
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bz test_failure
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lsr 31,r0
|
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tst sys.ccc,cc
|
|
bz test_failure
|
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lsr 1,r0
|
|
bc test_failure
|
|
; Now repeat the above tests, looking to see whether or not ASR works
|
|
ldi -1,r0
|
|
asr 32,r0
|
|
cmp -1,r0
|
|
bnz test_failure
|
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ldi -1,r0
|
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asr 0,r0
|
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bc test_failure
|
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cmp -1,r0
|
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bnz test_failure
|
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asr 1,r0
|
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tst sys.ccc,r14
|
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bz test_failure
|
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asr 30,r0
|
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tst sys.ccc,r14
|
|
bz test_failure
|
|
|
// Let's test whether LSL works
|
// Let's test whether LSL works
|
ldi $0x0b00,r11
|
|
ldi 0x035,r2
|
ldi 0x035,r2
|
lsl 8,r2
|
lsl 8,r2
|
ldi 0x03500,r1
|
ldi 0x03500,r1
|
cmp r2,r1
|
cmp r2,r1
|
trap.ne r11
|
trap.ne r11
|
ldi 0x074,r0
|
ldi 0x074,r0
|
and 0x0ff,r0
|
and 0x0ff,r0
|
or r0,r2
|
or r0,r2
|
cmp 0x03574,r2
|
cmp 0x03574,r2
|
trap.ne r11
|
trap.ne r11
|
|
#endif
|
|
|
|
#ifdef MPY_TEST
|
|
|
|
// We have two multiply instructions. Let's see if those work
|
|
ldi $0x0d000,r11 // Mark our test
|
|
ldi 23171,r0 // = sqrt(2)/2 * 32768
|
|
mpyu r0,r0 // Should = 2/4 * 2^30 = 2^29 or thereabouts
|
|
ldi 536895241,r2
|
|
cmp r0,r2
|
|
trap.ne r11
|
|
ldi 0x0ffff,r0
|
|
mpyu r0,r0
|
|
ldi 0xfffe0001,r1
|
|
cmp r1,r0
|
|
trap.ne r11
|
|
ldi 0x08001,r0
|
|
ldi 0x07fff,r1
|
|
mpys r0,r1 // FAILS: result is 0x008001 ??? (pipeline prob)
|
|
ldi 0x3fff0001,r2
|
|
neg r2
|
|
cmp r2,r1 // @0x010011c
|
|
trap.ne r11 //TRAP FAILS TO TRIGGER ????? (R2=0x0c000ffff,R1=0x0008001 -- did mpy even happen?)
|
|
mpys r0,r0 // FAILS: result is 0x40010001
|
|
ldi 0x3fff0001,r2
|
|
cmp r2,r0
|
|
trap.ne r11 // TRAP FAILS TO TRIGGER AGAIN
|
|
ldi 0x08000,r0
|
|
mpys r0,r0 // R0 now equals 0x40000000
|
|
ldi 0x40000000,r1
|
|
cmp r0,r1
|
|
trap.ne r11
|
|
#endif
|
|
|
// Return success / Test the trap interrupt
|
// Return success / Test the trap interrupt
|
clr r11
|
clr r11
|
trap r11
|
trap r11
|
noop
|
noop
|
