OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [sw/] [zasm/] [test.S] - Diff between revs 34 and 36

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 34 Rev 36
Line 105... Line 105...
        clr     r3
        clr     r3
        clr     r4
        clr     r4
        clr     r5
        clr     r5
        clr     r6
        clr     r6
        clr     r7
        clr     r7
 
        clr     r8
        clr     r9
        clr     r9
        clr     r10
        clr     r10
        clr     r11
        clr     r11
        clr     r12
        clr     r12
        clr     r13
        clr     r13
Line 182... Line 183...
        clr     r3
        clr     r3
        clr     r4
        clr     r4
        clr     r5
        clr     r5
        clr     r6
        clr     r6
        clr     r7
        clr     r7
 
        clr     r8
        clr     r9
        clr     r9
        clr     r10
        clr     r10
        clr     r11
        clr     r11
        clr     r12
        clr     r12
        clr     r13
        clr     r13
Line 207... Line 209...
        nop
        nop
        add     r2,r0
        add     r2,r0
        add     $32,r0
        add     $32,r0
        add     $-33,r0
        add     $-33,r0
        bnz     test_failure
        bnz     test_failure
        not.z   r0
        not     r0
        bge     test_failure
        bge     test_failure
junk_address:
junk_address:
        clrf    r0
        clrf    r0
        bnz     test_failure
        bnz     test_failure
        ldi     $5,r1
        ldi     $5,r1
Line 298... Line 300...
; Some data registers
; Some data registers
test_data:
test_data:
        .dat    __here__+0x0100000+5
        .dat    __here__+0x0100000+5
test_start:
test_start:
        ldi     $0x01000,r11
        ldi     $0x01000,r11
 
        ldi     -1,r10
        lod     test_data+pc,pc
        lod     test_data+pc,pc
        clr     r11
        clr     r10
        noop
        noop
        cmp     $0,r11
        cmp     $0,r10
        trap.z  r11
        trap.z  r11
        add     $1,r0
        add     $1,r0
        add     $1,r0
        add     $1,r0
 
 
#ifdef  OVERFLOW_TEST
#ifdef  OVERFLOW_TEST
Line 528... Line 531...
        halt
        halt
 
 
// Now, let's test whether or not we can handle a subroutine
// Now, let's test whether or not we can handle a subroutine
#ifdef  PUSH_TEST
#ifdef  PUSH_TEST
reverse_bit_order:
reverse_bit_order:
        PUSH(R1,SP)
        PUSH(R1,SP)     ; R1 will be our loop counter
        PUSH(R2,SP)
        PUSH(R2,SP)     ; R2 will be our accumulator and eventual result
        LDI     32,R1
        LDI     32,R1
        CLR     R2
        CLR     R2
reverse_bit_order_loop:
reverse_bit_order_loop:
        LSL     1,R2
        LSL     1,R2
        LSR     1,R0
        LSR     1,R0

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.