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[/] [zipcpu/] [trunk/] [sw/] [zasm/] [test.S] - Diff between revs 36 and 39

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Rev 36 Rev 39
Line 517... Line 517...
        cmp     r0,r1
        cmp     r0,r1
        trap.ne r11
        trap.ne r11
        cmp     r0,r7
        cmp     r0,r7
        trap.ne r11
        trap.ne r11
#endif
#endif
 
 
 
#define PIPELINE_STACK_TEST
 
#ifdef  PIPELINE_STACK_TEST
 
        ldi     $0x0f000,r11    // Mark our test
 
        LDI     1,R0
 
        MOV     1(R0),R1
 
        MOV     1(R1),R2
 
        MOV     1(R2),R3
 
        MOV     1(R3),R4
 
        MOV     1(R4),R5
 
        MOV     1(R5),R6
 
        JSR(pipeline_stack_test,R7)
 
        CMP     1,R0
 
        trap.ne R11
 
        CMP     2,R1
 
        trap.ne R11
 
        CMP     3,R2
 
        trap.ne R11
 
        CMP     4,R3
 
        trap.ne R11
 
        CMP     5,R4
 
        trap.ne R11
 
        CMP     6,R5
 
        trap.ne R11
 
        CMP     7,R6
 
        trap.ne R11
 
#endif
// Return success / Test the trap interrupt
// Return success / Test the trap interrupt
        clr     r11
        clr     r11
        trap    r11
        trap    r11
        noop
        noop
        noop
        noop
Line 546... Line 573...
        MOV     R2,R0
        MOV     R2,R0
        POP(R2,SP)
        POP(R2,SP)
        POP(R1,SP)
        POP(R1,SP)
        RET
        RET
#endif
#endif
 
 
 
#ifdef  PIPELINE_STACK_TEST
 
pipeline_stack_test:
 
        SUB     13,SP
 
        STO     R0,1(SP)
 
        STO     R1,2(SP)
 
        STO     R2,3(SP)
 
        STO     R3,4(SP)
 
        STO     R4,5(SP)
 
        STO     R5,6(SP)
 
        STO     R6,7(SP)
 
        STO     R7,8(SP)
 
        STO     R8,9(SP)
 
        STO     R9,10(SP)
 
        STO     R10,11(SP)
 
        STO     R11,12(SP)
 
        STO     R12,13(SP)
 
        XOR     -1,R0
 
        XOR     -1,R1
 
        XOR     -1,R2
 
        XOR     -1,R3
 
        XOR     -1,R4
 
        XOR     -1,R5
 
        XOR     -1,R6
 
        XOR     -1,R7
 
        XOR     -1,R8
 
        XOR     -1,R9
 
        XOR     -1,R10
 
        XOR     -1,R11
 
        XOR     -1,R12
 
        LOD     1(SP),R0
 
        LOD     2(SP),R1
 
        LOD     3(SP),R2
 
        LOD     4(SP),R3
 
        LOD     5(SP),R4
 
        LOD     6(SP),R5
 
        LOD     7(SP),R6
 
        LOD     8(SP),R7
 
        LOD     9(SP),R8
 
        LOD     10(SP),R9
 
        LOD     11(SP),R10
 
        LOD     12(SP),R11
 
        LOD     13(SP),R12
 
        ADD     13,SP
 
        LOD     1(SP),PC
 
#endif // PIPELINE_STACK_TEST
 
 
        fill    512,0
        fill    512,0
stack:  // Must point to a valid word initially
stack:  // Must point to a valid word initially
        word    0
        word    0

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