| Line 84... |
Line 84... |
#define TRAP_TEST
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#define TRAP_TEST
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#define MPY_TEST
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#define MPY_TEST
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#define PUSH_TEST
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#define PUSH_TEST
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#define PIPELINE_STACK_TEST
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#define PIPELINE_STACK_TEST
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#define MEM_PIPELINE_TEST
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#define MEM_PIPELINE_TEST
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#define CONDITIONAL_EXECUTION_TEST
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#define NOWAIT_PIPELINE_TEST // Were wait states btwn regs removed properly?
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#define NOWAIT_PIPELINE_TEST // Were wait states btwn regs removed properly?
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test:
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test:
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#ifdef DO_TEST_ASSEMBLER
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#ifdef DO_TEST_ASSEMBLER
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; We start out by testing our assembler. We give it some instructions, which
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; We start out by testing our assembler. We give it some instructions, which
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; are then manually checked by disassembling/dumping the result and making
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; are then manually checked by disassembling/dumping the result and making
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| Line 570... |
Line 571... |
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#ifdef MEM_PIPELINE_TEST
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#ifdef MEM_PIPELINE_TEST
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JSR(mem_pipeline_test,R0)
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JSR(mem_pipeline_test,R0)
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#endif // MEM_PIPELINE_TEST
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#endif // MEM_PIPELINE_TEST
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#ifdef CONDITIONAL_EXECUTION_TEST
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JSR(conditional_execution_test,R0)
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#endif // CONDITIONAL_EXECUTION_TEST
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#ifdef NOWAIT_PIPELINE_TEST
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#ifdef NOWAIT_PIPELINE_TEST
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JSR(nowait_pipeline_test,R0)
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JSR(nowait_pipeline_test,R0)
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#endif // NOWAIT_PIPELINE_TEST
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#endif // NOWAIT_PIPELINE_TEST
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// Return success / Test the trap interrupt
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// Return success / Test the trap interrupt
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| Line 696... |
Line 701... |
LOD 2(SP),R1
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LOD 2(SP),R1
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ADD 4,SP
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ADD 4,SP
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RETN
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RETN
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#endif
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#endif
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#ifdef CONDITIONAL_EXECUTION_TEST
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conditional_execution_test:
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; R0 is corrupt on entry, no need to save it
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; SUB 1,SP
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; STO R0,1(SP)
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CLRF R0
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ADD.Z 1,R0
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TRAP.NZ R11
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CMP.Z 0,R0
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TRAP.Z R11
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; LOD 1(SP),R0
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; ADD 1,SP
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; ; Stall
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RETN
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#endif
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;
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;
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; Pipeline stalls have been hideous problems for me. The CPU has been modified
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; Pipeline stalls have been hideous problems for me. The CPU has been modified
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; with special logic to keep stages from stalling. For the most part, this
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; with special logic to keep stages from stalling. For the most part, this
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; means that ALU and memory results may be accessed either before or as they
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; means that ALU and memory results may be accessed either before or as they
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; are written to the register file. This set of code is designed to test
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; are written to the register file. This set of code is designed to test
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; whether this bypass logic works.
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; whether this bypass logic works.
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#ifdef NOWAIT_PIPELINE_TEST
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#ifdef NOWAIT_PIPELINE_TEST
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nowait_pipeline_test:
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nowait_pipeline_test:
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; Allocate for us some number of registers
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; Allocate for us some number of registers
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;
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;
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SUB 5,SP
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SUB 6,SP
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STO R0,1(SP)
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; Leave a spot open on the stack for a local variable,
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STO R1,2(SP)
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; kept in memory.
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STO R2,3(SP)
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STO R0,2(SP)
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STO R3,4(SP)
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STO R1,3(SP)
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STO R4,5(SP)
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STO R2,4(SP)
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STO R3,5(SP)
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STO R4,6(SP)
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;
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;
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; Let's start with ALU-ALU testing
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; Let's start with ALU-ALU testing
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; AA: result->input A
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; AA: result->input A
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CLR R0
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ADD 1,R0
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CMP 1,R0
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TRAP.NZ R11
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; AA: result->input B
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; AA: result->input B
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CLR R0
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CLR R1
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ADD 1,R0
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CMP R0,R1
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TRAP.Z R11
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; AA: result->input A on condition
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; AA: result->input A on condition
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CLRF R0
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ADD.Z 5,R0
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CMP 5,R0
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TRAP.NZ R11
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; AA: result->input B on condition
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; AA: result->input B on condition
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CLR R0
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CLRF R1
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ADD.Z 5,R0
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CMP R0,R1
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TRAP.Z R11
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; AA: result->input B plus offset
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; AA: result->input B plus offset
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CLR R0
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CLRF R1
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ADD 5,R0
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CMP -5(R0),R1
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TRAP.NZ R11
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; AA: result->input B plus offset on condition
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; AA: result->input B plus offset on condition
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CLR R0
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CLRF R1
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ADD.Z 5,R0
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CMP -5(R0),R1
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TRAP.NZ R11
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;
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;
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; Then we need to do ALU-Mem input testing
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; Then we need to do ALU-Mem input testing
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; (not implemented yet)
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;
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CLR R0
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STO R0,1(SP)
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LDI 8352,R0
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LOD 1(SP),R0
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TST -1,R0
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TRAP.NZ R11
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LDI 937,R0 ; Let's try again, this time something that's
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STO R0,1(SP) ; not zero
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NOOP
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LOD 1(SP),R0
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CMP 938,R0 ; Let's not compare with self, let's that
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TRAP.GE R11 ; masks a problem--compare with a different
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CMP 936,R0 ; number instead.
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TRAP.LT R11
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; Mem output->ALU input testing
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; Mem output->ALU input testing
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; (not implemented yet)
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; We just did that as partof our last test
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; Mem output->MEM input testing
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; Mem output->MEM input testing
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; (not implemented yet)
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;
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;
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LOD 1(SP),R0
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LDI 5328,R2
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LOD 2(SP),R1
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LOD 1(SP),R2
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LOD 3(SP),R2
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STO R2,1(SP)
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LOD 4(SP),R3
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LOD 1(SP),R1
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LOD 5(SP),R4
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CMP 937,R1
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ADD 5,SP
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TRAP.NZ R11
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;
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LOD 2(SP),R0
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LOD 3(SP),R1
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LOD 4(SP),R2
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LOD 5(SP),R3
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LOD 6(SP),R4
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ADD 6,SP
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RETN
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RETN
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#endif // NOWAIT_PIPELINE_TEST
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#endif // NOWAIT_PIPELINE_TEST
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fill 512,0
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fill 512,0
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stack: // Must point to a valid word initially
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stack: // Must point to a valid word initially
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