URL https://opencores.org/ocsvn/zx_ula/zx_ula/trunk

Subversion Repositories zx_ula

[/] [zx_ula/] [branches/] [xilinx/] [spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/] [spectrum48k_tld.v] - Diff between revs 15 and 18

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Rev 15	Rev 18
Line 93...	Line 93...
`wire ulaplusaddr_cs = !iorq_n & a[0] & !a[2] & a[7:6]==2'b00 & (a[15:14]==2'b10); // port BF3Bh`	`wire ulaplusaddr_cs = !iorq_n & a[0] & !a[2] & a[7:6]==2'b00 & (a[15:14]==2'b10); // port BF3Bh`
`wire ulaplusdata_cs = !iorq_n & a[0] & !a[2] & a[7:6]==2'b00 & (a[15:14]==2'b11); // port FF3Bh`	`wire ulaplusdata_cs = !iorq_n & a[0] & !a[2] & a[7:6]==2'b00 & (a[15:14]==2'b11); // port FF3Bh`
`wire rom_cs = !a[15] & !a[14] & !mreq_n & !rd_n;`	`wire rom_cs = !a[15] & !a[14] & !mreq_n & !rd_n;`

`/////////////////////////////////////`	`/////////////////////////////////////`
`// Master clock (14MHz) generation`	`// Clock generation`
`/////////////////////////////////////`	`/////////////////////////////////////`
`wire clk28mhz;`	`wire clk56mhz;`
`master_clock clock28mhz (`	`master_clock clock56mhz (`
`.CLKIN_IN(clk50),`	`.CLKIN_IN(clk50),`
`.CLKFX_OUT(clk28mhz),`	`.CLKFX_OUT(clk56mhz),`
`.CLKIN_IBUFG_OUT(),`	`.CLKIN_IBUFG_OUT(),`
`.CLK0_OUT()`	`.CLK0_OUT()`
`);`	`);`
`reg clk14 = 0;`	`reg [1:0] cnt56;`
`always @(posedge clk28mhz) begin`	`always @(posedge clk56mhz) begin`
`clk14 = !clk14;`	`cnt56 = cnt56 + 1;`
`end`	`end`
	`wire clk28 = cnt56[0];`
	`wire clk14 = cnt56[1];`
`wire clkula = clk14;`	`wire clkula = clk14;`
`wire clkmem = clk28mhz;`	`wire clkdacvideo = clk56mhz;`
`wire clkaudio = clk14;`	`wire clkmem = clk28;`
	`wire clkdacaudio = clk14;`
`wire clkkbd = clk14;`	`wire clkkbd = clk14;`

`/////////////////////////////////////`	`/////////////////////////////////////`
`// ROM`	`// ROM`
`/////////////////////////////////////`	`/////////////////////////////////////`
Line 153...	Line 156...
`);`	`);`

`/////////////////////////////////////`	`/////////////////////////////////////`
`// The ULA`	`// The ULA`
`/////////////////////////////////////`	`/////////////////////////////////////`
	`wire ula_r,ula_g,ula_b,ula_i,ulaplus_enabled;`
	`wire [7:0] rgbulaplus;`
`ula the_ula (`	`ula the_ula (`
`.clk14(clkula),`	`.clk14(clkula),`
`.reset(reset),`	`.reset(reset),`
`.a(a),`	`.a(a),`
`.din(uladin),`	`.din(uladin),`
Line 177...	Line 182...
`.ear(ear),`	`.ear(ear),`
`.mic(mic),`	`.mic(mic),`
`.spk(spk),`	`.spk(spk),`
`.kbrows(),`	`.kbrows(),`
`.kbcolumns(kbd_columns),`	`.kbcolumns(kbd_columns),`
	`.r(ula_r),`
	`.g(ula_g),`
	`.b(ula_b),`
	`.i(ula_i),`
	`.rgbulaplus(rgbulaplus),`
	`.ulaplus_enabled(ulaplus_enabled),`
	`.csync(csync)`
	`);`

	`/////////////////////////////////////`
	`// ULA/ULA+ video selector and enconding`
	`/////////////////////////////////////`
	`assign i = 1;`
	`rgbdtoa video_final_stage (`
	`.clk(clkdacvideo),`
	`.reset(reset),`
	`.select(ulaplus_enabled),`
	`.ri(ula_r),`
	`.gi(ula_g),`
	`.bi(ula_b),`
	`.hi(ula_i),`
	`.rgbulap(rgbulaplus),`
`.r(r),`	`.r(r),`
`.g(g),`	`.g(g),`
`.b(b),`	`.b(b)`
`.i(i),`
`.csync(csync)`
`);`	`);`

`/////////////////////////////////////`	`/////////////////////////////////////`
`// The CPU Z80A`	`// The CPU Z80A`
`/////////////////////////////////////`	`/////////////////////////////////////`
Line 223...	Line 248...

`/////////////////////////////////////`	`/////////////////////////////////////`
`// Audio mixer`	`// Audio mixer`
`/////////////////////////////////////`	`/////////////////////////////////////`
`mixer audio_mix (`	`mixer audio_mix (`
`.clkdac(clkaudio),`	`.clkdac(clkdacaudio),`
`.reset(reset),`	`.reset(reset),`
`.ear(ear),`	`.ear(ear),`
`.mic(mic),`	`.mic(mic),`
`.spk(spk),`	`.spk(spk),`
`.audio(audio_out)`	`.audio(audio_out)`

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[/] [zx_ula/] [branches/] [xilinx/] [spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/] [spectrum48k_tld.v] - Diff between revs 15 and 18