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[/] [zx_ula/] [branches/] [xilinx/] [spectrum_48k_spartan3_starter_kit_timex_hicolor_ulaplus/] [spectrum48k_tld.v] - Diff between revs 18 and 22

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Rev 18 Rev 22
Line 59... Line 59... 
        wire iorq_n;
 
        wire iorq_n;
 
        wire wr_n;
 
        wire wr_n;
 
        wire rd_n;
 
        wire rd_n;
 
        wire rfsh_n;
 
        wire rfsh_n;
 
        wire int_n;
 
        wire int_n;
 
 
 
        wire m1_n;
 
 
 
 
 
        // VRAM signals
 
        // VRAM signals
 
        wire [13:0] va;
 
        wire [13:0] va;
 
        wire [7:0] vramdin;
 
        wire [7:0] vramdin;
 
        wire [7:0] vramdout;
 
        wire [7:0] vramdout;
Line 85... Line 86... 
 
 
 
 
        // ROM data bus
 
        // ROM data bus
 
        wire [7:0] romdout;
 
        wire [7:0] romdout;
 
 
 
 
 
        wire sram_cs = a[15] & !mreq_n;
 
        wire sram_cs = a[15] & !mreq_n;
 
        wire ula_cs = !a[0] & !iorq_n;
 
        wire ula_cs = !a[0] & !iorq_n & m1_n;
 
        wire vram_cs = !a[15] & a[14] & !mreq_n;
 
        wire vram_cs = !a[15] & a[14] & !mreq_n;
 
        wire port255_cs = !iorq_n && a[7:0]==8'hFF && !rd_n;
 
        wire port255_cs = !iorq_n && m1_n && a[7:0]==8'hFF && !rd_n;
 
        wire ulaplusaddr_cs = !iorq_n & a[0] & !a[2] & a[7:6]==2'b00 & (a[15:14]==2'b10); // port BF3Bh
 
        wire ulaplusaddr_cs = !iorq_n & m1_n & a[0] & !a[2] & a[7:6]==2'b00 & (a[15:14]==2'b10); // port BF3Bh
 
        wire ulaplusdata_cs = !iorq_n & a[0] & !a[2] & a[7:6]==2'b00 & (a[15:14]==2'b11);  // port FF3Bh
 
        wire ulaplusdata_cs = !iorq_n & m1_n & a[0] & !a[2] & a[7:6]==2'b00 & (a[15:14]==2'b11);  // port FF3Bh
 
        wire rom_cs = !a[15] & !a[14] & !mreq_n & !rd_n;
 
        wire rom_cs = !a[15] & !a[14] & !mreq_n & !rd_n;
 
 
 
 
 
        /////////////////////////////////////
 
        /////////////////////////////////////
 
        // Clock generation
 
        // Clock generation
 
        /////////////////////////////////////
 
        /////////////////////////////////////
Line 214... Line 215... 
   /////////////////////////////////////
 
   /////////////////////////////////////
 
   // The CPU Z80A
 
   // The CPU Z80A
 
   /////////////////////////////////////        
   /////////////////////////////////////        
   tv80n cpu (
 
   tv80n cpu (
 
                // Outputs
 
                // Outputs
 
                .m1_n(),
 
                .m1_n(m1_n),
 
                .mreq_n(mreq_n),
 
                .mreq_n(mreq_n),
 
                .iorq_n(iorq_n),
 
                .iorq_n(iorq_n),
 
                .rd_n(rd_n),
 
                .rd_n(rd_n),
 
                .wr_n(wr_n),
 
                .wr_n(wr_n),
 
                .rfsh_n(rfsh_n),
 
                .rfsh_n(rfsh_n),

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