| Line 52... |
Line 52... |
// Video output
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// Video output
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output r, //
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output r, //
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output g, // RGB TTL signal
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output g, // RGB TTL signal
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output b, // with separate bright
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output b, // with separate bright
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output i, // and composite sync
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output i, // and composite sync
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output [7:0] rgbulaplus, // 8-bit RGB value for current pixel, ULA+
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output ulaplus_enabled, // =1 if ULAPlus enabled. To help selecting the right outputs to the RGB DAC
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output csync //
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output csync //
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);
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);
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reg [2:0] BorderColor = 3'b100;
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reg [2:0] BorderColor = 3'b100;
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reg TimexHiColorMode = 0;
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reg TimexHiColorMode = 0;
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reg ULAPlusConfig = 0;
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reg ULAPlusConfig = 0; // bit 0 of reg.64
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reg [7:0] ULAPlusAddrReg = 0;
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reg [7:0] ULAPlusAddrReg = 0; // ULA+ register address, BF3Bh port.
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assign ulaplus_enabled = ULAPlusConfig;
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wire addrportsel = !iorq_n && a[0] && !a[2] && (a[7:6]==2'b00) && (a[15:14]==2'b10); // port BF3Bh
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wire addrportsel = !iorq_n && a[0] && !a[2] && (a[7:6]==2'b00) && (a[15:14]==2'b10); // port BF3Bh
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wire dataportsel = !iorq_n && a[0] && !a[2] && (a[7:6]==2'b00) && (a[15:14]==2'b11); // port FF3Bh
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wire dataportsel = !iorq_n && a[0] && !a[2] && (a[7:6]==2'b00) && (a[15:14]==2'b11); // port FF3Bh
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wire cpu_writes_palette = dataportsel && !wr_n && (ULAPlusAddrReg[7:6]==2'b00);
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wire cpu_writes_palette = dataportsel && !wr_n && (ULAPlusAddrReg[7:6]==2'b00); //=1 if CPU wants to write a palette entry to RAM
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reg [5:0] paletteaddr;
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reg [5:0] paletteaddr; // address bus of palette RAM
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wire [7:0] palettedout;
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wire [7:0] palettedout; // data out port of palette RAM
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reg palettewe;
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reg palettewe; // WE signal of palette RAM (palette RAM is always selected and output enabled)
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ram64bytes palette (
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ram64bytes palette (
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.clk(clk14),
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.clk(clk14), // only for write operations. Read operations are asynchronous
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.a(paletteaddr),
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.a(paletteaddr),
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.din(din),
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.din(din),
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.dout(palettedout),
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.dout(palettedout),
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.we(palettewe)
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.we(palettewe) // RAM is written if WE is enabled at the rising edge of clk
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);
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);
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// Pixel clock
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// Pixel clock
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reg clk7 = 0;
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reg clk7 = 0;
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always @(posedge clk14)
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always @(posedge clk14)
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| Line 299... |
Line 302... |
rVOE = !rd_n;
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rVOE = !rd_n;
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rVWE = !wr_n;
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rVWE = !wr_n;
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end
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end
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end
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end
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// Palette addr and control bus multiplexing
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// ULA+ : palette RAM address and control bus multiplexing
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always @(*) begin
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always @(*) begin
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if (Border_n && (hc[3:0]==10 || hc[3:0]==14)) begin // present address of paper to palette RAM
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if (Border_n && (hc[3:0]==10 || hc[3:0]==14)) begin // present address of paper to palette RAM
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palettewe = 0;
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palettewe = 0;
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paletteaddr = { AttrReg[7:6],1'b1,AttrReg[5:3] };
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paletteaddr = { AttrReg[7:6],1'b1,AttrReg[5:3] };
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end
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end
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Line 316... |
end
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end
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else if (dataportsel) begin // if CPU requests access, give it palette control
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else if (dataportsel) begin // if CPU requests access, give it palette control
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paletteaddr = ULAPlusAddrReg[5:0];
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paletteaddr = ULAPlusAddrReg[5:0];
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palettewe = cpu_writes_palette;
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palettewe = cpu_writes_palette;
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end
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end
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else begin
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else begin // if palette RAM is not being used to display pixels, and the CPU doesn't need it, put the border color address
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palettewe = 0; // blocking assignment, so we will first deassert WE at palette RAM...
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palettewe = 0; // blocking assignment, so we will first deassert WE at palette RAM...
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paletteaddr = {3'b001, BorderColor}; // ... then, we can change the palette RAM address
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paletteaddr = {3'b001, BorderColor}; // ... then, we can change the palette RAM address
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end
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end
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end
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end
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//ULA+ : palette reading and attribute generation
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// First buffers for paper and ink
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reg [7:0] ULAPlusPaper = 0;
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reg [7:0] ULAPlusInk = 0;
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reg [7:0] ULAPlusBorder = 0;
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wire ULAPlusPixel = SRegister[7];
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always @(negedge clk14) begin
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if (Border_n && (hc[3:0]==10 || hc[3:0]==14) && !clk7) // this happens 1/2 clk7 after address is settled
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ULAPlusPaper <= palettedout;
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else if (Border_n && (hc[3:0]==11 || hc[3:0]==15) && !clk7) // this happens 1/2 clk7 after address is settled
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ULAPlusInk <= palettedout;
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else if (hc[3:0]==12 && !dataportsel) // On cycle 12, palette RAM is not used to retrieve ink/paper color. If CPU is not reclaiming it...
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ULAPlusBorder <= palettedout; //... take the chance to update the BorderColor register by reading the palette RAM. The address
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end // presented at the palette RAM address bus will be 001BBB, where BBB is the border color code.
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// Second buffers for paper and ink
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reg [7:0] ULAPlusPaperOut = 0;
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reg [7:0] ULAPlusInkOut = 0;
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always @(negedge AOLatch_n) begin
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if (!VidEN_n) begin // if it's "paper time", load output buffers with current ink and paper color
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ULAPlusPaperOut <= ULAPlusPaper;
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ULAPlusInkOut <= ULAPlusInk;
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end
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else begin // if not, it's "border/blanking time", so load output buffers with current border color
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ULAPlusPaperOut <= ULAPlusBorder;
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ULAPlusInkOut <= ULAPlusBorder;
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end
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end
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// ULA+ : final RGB generation depending on pixel value and blanking period.
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reg [7:0] rRGBULAPlus;
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assign rgbulaplus = rRGBULAPlus;
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always @(*) begin
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if (HBlank_n && VBlank_n)
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rRGBULAPlus = (ULAPlusPixel)? ULAPlusInkOut : ULAPlusPaperOut;
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else
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rRGBULAPlus = 8'h00;
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end
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// CPU contention
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// CPU contention
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reg CPUClk = 0;
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reg CPUClk = 0;
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assign clkcpu = CPUClk;
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assign clkcpu = CPUClk;
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reg ioreqtw3 = 0;
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reg ioreqtw3 = 0;
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reg mreqt23 = 0;
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reg mreqt23 = 0;
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| Line 347... |
Line 387... |
always @(posedge CPUClk) begin
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always @(posedge CPUClk) begin
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ioreqtw3 <= ioreq_n;
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ioreqtw3 <= ioreq_n;
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mreqt23 <= mreq_n;
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mreqt23 <= mreq_n;
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end
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end
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// ULA+ palette management
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// ULA+ : palette management
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always @(posedge clk7 or posedge reset) begin
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always @(posedge clk7 or posedge reset) begin
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if (reset)
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if (reset)
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ULAPlusConfig <= 0;
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ULAPlusConfig <= 0;
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else begin
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else begin
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if (addrportsel && !wr_n)
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if (addrportsel && !wr_n)
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