`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// Company: Dept. Architecture and Computing Technology. University of Seville
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// Company: Dept. Architecture and Computing Technology. University of Seville
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// Engineer: Miguel Angel Rodriguez Jodar. rodriguj@atc.us.es
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// Engineer: Miguel Angel Rodriguez Jodar. rodriguj@atc.us.es
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//
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//
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// Create Date: 19:13:39 4-Apr-2012
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// Create Date: 19:13:39 4-Apr-2012
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// Design Name: ZX Spectrum
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// Design Name: ZX Spectrum
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// Module Name: ula
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// Module Name: ula
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// Project Name:
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// Project Name:
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// Target Devices:
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// Target Devices:
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// Tool versions:
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// Tool versions:
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// Description:
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// Description:
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//
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//
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// Dependencies:
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// Dependencies:
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//
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//
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// Revision:
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// Revision:
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// Revision 1.00 - File Created
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// Revision 1.00 - File Created
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// Additional Comments: GPL License policies apply to the contents of this file.
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// Additional Comments: GPL License policies apply to the contents of this file.
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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`define cyclestart(a,b) ((a)==(b))
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`define cyclestart(a,b) ((a)==(b))
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`define cycleend(a,b) ((a)==(b+1))
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`define cycleend(a,b) ((a)==(b+1))
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module ula(
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module ula(
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input clk14, // 14MHz master clock
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input clk28, // 28MHz master clock
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input reset_n, // to reset the ULA to normal color mode.
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input reset_n, // to reset the ULA to normal color mode.
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// CPU interfacing
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// CPU interfacing
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input [15:0] a, // Address bus from CPU (not all lines are used)
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input a15, // Address bus from CPU (not all lines are used)
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input [7:0] din, // Input data bus from CPU
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input a14,
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output [7:0] dout, // Output data bus to CPU
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input a7,
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input a6,
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input a2,
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inout [7:0] d, // Data bus from/to CPU
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input mreq_n, // MREQ from CPU
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input mreq_n, // MREQ from CPU
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input ioreq_n, // IORQ+A0 from main board
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input ioreq_n, // IORQ+A0 from main board
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input iorq_n, // IORQ from CPU
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input iorq_n, // IORQ from CPU
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input rd_n, // RD from CPU
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input rd_n, // RD from CPU
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input wr_n, // WR from CPU
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input wr_n, // WR from CPU
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output clkcpu, // CLK to CPU
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output clkcpu, // CLK to CPU
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output msk_int_n, // Vertical retrace interrupt, to CPU
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output msk_int_n, // Vertical retrace interrupt, to CPU
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// VRAM interfacing
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// VRAM interfacing
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output [13:0] va, // Address bus to VRAM (16K)
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output [6:0] va, // Address bus to VRAM (16K)
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input [7:0] vramdout,// Data from VRAM to ULA/CPU
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output ras_n, //
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output [7:0] vramdin,// Data from CPU to VRAM
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output cas_n, // Control signals for VRAM
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output vramoe, //
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output dramwe_n, //
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output vramcs, // Control signals for VRAM
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output vramwe, //
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// ULA I/O
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// ULA I/O
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input ear, //
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input ear, //
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output mic, // I/O ports
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output mic, // I/O ports
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output spk, //
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output spk, //
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input [4:0] kbcolumns, // Keyboard columns
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input [4:0] kbcolumns, // Keyboard columns
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// Video output
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// Video output
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output r, //
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output r, //
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output g, // RGB TTL signal
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output g, // RGB TTL signal
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output b, // with separate bright
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output b, // with separate bright
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output i, // and composite sync
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output i, // and composite sync
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output [7:0] rgbulaplus, // 8-bit RGB value for current pixel, ULA+
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output [7:0] rgbulaplus, // 8-bit RGB value for current pixel, ULA+
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output ulaplus_enabled, // =1 if ULAPlus enabled. To help selecting the right outputs to the RGB DAC
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output ulaplus_enabled, // =1 if ULAPlus enabled. To help selecting the right outputs to the RGB DAC
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output csync //
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output csync //
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);
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);
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reg [2:0] BorderColor = 3'b100;
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reg [2:0] BorderColor = 3'b100;
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reg TimexHiColorMode = 0;
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reg TimexHiColorMode = 0;
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reg ULAPlusConfig = 0; // bit 0 of reg.64
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reg ULAPlusConfig = 0; // bit 0 of reg.64
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reg [7:0] ULAPlusAddrReg = 0; // ULA+ register address, BF3Bh port.
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reg [7:0] ULAPlusAddrReg = 0; // ULA+ register address, BF3Bh port.
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assign ulaplus_enabled = ULAPlusConfig;
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assign ulaplus_enabled = ULAPlusConfig;
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wire addrportsel = !iorq_n && a[0] && !a[2] && (a[7:6]==2'b00) && (a[15:14]==2'b10); // port BF3Bh
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wire a0 = (!ioreq_n && !iorq_n)? 0 : 1; // Regenerate a valid (for IORQ access) a0 signal
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wire dataportsel = !iorq_n && a[0] && !a[2] && (a[7:6]==2'b00) && (a[15:14]==2'b11); // port FF3Bh
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wire addrportsel = !iorq_n && a0 && !a2 && !a7 && !a6 && a15 && !a14; // port BF3Bh
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wire dataportsel = !iorq_n && a0 && !a2 && !a7 && !a6 && a15 && a14; // port FF3Bh
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wire cpu_writes_palette = dataportsel && !wr_n && (ULAPlusAddrReg[7:6]==2'b00); //=1 if CPU wants to write a palette entry to RAM
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wire cpu_writes_palette = dataportsel && !wr_n && (ULAPlusAddrReg[7:6]==2'b00); //=1 if CPU wants to write a palette entry to RAM
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reg [5:0] paletteaddr; // address bus of palette RAM
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reg [5:0] paletteaddr; // address bus of palette RAM
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wire [7:0] palettedout; // data out port of palette RAM
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wire [7:0] palettedout; // data out port of palette RAM
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reg palettewe; // WE signal of palette RAM (palette RAM is always selected and output enabled)
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reg palettewe; // WE signal of palette RAM (palette RAM is always selected and output enabled)
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// Clocks
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reg [1:0] clk28div = 0;
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always @(posedge clk28) // 28MHz for RAS/CAS generation
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clk28div <= clk28div + 1;
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wire clk7 = clk28div[1]; // For pixel operations
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wire clk14 = clk28div[0]; // For palette operations
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// Palette RAM instantiation
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ram64bytes palette (
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ram64bytes palette (
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.clk(clk14), // only for write operations. Read operations are asynchronous
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.clk(clk14), // only for write operations. Read operations are asynchronous
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.a(paletteaddr),
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.a(paletteaddr),
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.din(din),
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.din(din),
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.dout(palettedout),
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.dout(palettedout),
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.we(palettewe) // RAM is written if WE is enabled at the rising edge of clk
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.we(palettewe) // RAM is written if WE is enabled at the rising edge of clk
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);
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);
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// Pixel clock
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reg clk7 = 0;
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always @(posedge clk14)
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clk7 <= !clk7;
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// Horizontal counter
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// Horizontal counter
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reg [8:0] hc = 0;
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reg [8:0] hc = 0;
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always @(posedge clk7) begin
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always @(posedge clk7) begin
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if (hc==447)
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if (hc==447)
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hc <= 0;
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hc <= 0;
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else
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else
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hc <= hc + 1;
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hc <= hc + 1;
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end
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end
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// Vertical counter
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// Vertical counter
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reg [8:0] vc = 0;
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reg [8:0] vc = 0;
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always @(posedge clk7) begin
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always @(posedge clk7) begin
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if (hc==447) begin
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if (hc==447) begin
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if (vc == 311)
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if (vc == 311)
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vc <= 0;
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vc <= 0;
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else
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else
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vc <= vc + 1;
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vc <= vc + 1;
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end
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end
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end
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end
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// HBlank generation
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// HBlank generation
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reg HBlank_n = 1;
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reg HBlank_n = 1;
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always @(negedge clk7) begin
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always @(negedge clk7) begin
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if (`cyclestart(hc,320))
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if (`cyclestart(hc,320))
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HBlank_n <= 0;
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HBlank_n <= 0;
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else if (`cycleend(hc,415))
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else if (`cycleend(hc,415))
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HBlank_n <= 1;
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HBlank_n <= 1;
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end
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end
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// HSync generation (6C ULA version)
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// HSync generation (6C ULA version)
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reg HSync_n = 1;
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reg HSync_n = 1;
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always @(negedge clk7) begin
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always @(negedge clk7) begin
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if (`cyclestart(hc,344))
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if (`cyclestart(hc,344))
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HSync_n <= 0;
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HSync_n <= 0;
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else if (`cycleend(hc,375))
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else if (`cycleend(hc,375))
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HSync_n <= 1;
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HSync_n <= 1;
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end
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end
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// VBlank generation
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// VBlank generation
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reg VBlank_n = 1;
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reg VBlank_n = 1;
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always @(negedge clk7) begin
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always @(negedge clk7) begin
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if (`cyclestart(vc,248))
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if (`cyclestart(vc,248))
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VBlank_n <= 0;
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VBlank_n <= 0;
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else if (`cycleend(vc,255))
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else if (`cycleend(vc,255))
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VBlank_n <= 1;
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VBlank_n <= 1;
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end
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end
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// VSync generation (PAL)
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// VSync generation (PAL)
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reg VSync_n = 1;
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reg VSync_n = 1;
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always @(negedge clk7) begin
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always @(negedge clk7) begin
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if (`cyclestart(vc,248))
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if (`cyclestart(vc,248))
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VSync_n <= 0;
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VSync_n <= 0;
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else if (`cycleend(vc,251))
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else if (`cycleend(vc,251))
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VSync_n <= 1;
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VSync_n <= 1;
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end
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end
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// INT generation
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// INT generation
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reg INT_n = 1;
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reg INT_n = 1;
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assign msk_int_n = INT_n;
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assign msk_int_n = INT_n;
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always @(negedge clk7) begin
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always @(negedge clk7) begin
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if (`cyclestart(vc,248) && `cyclestart(hc,0))
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if (`cyclestart(vc,248) && `cyclestart(hc,0))
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INT_n <= 0;
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INT_n <= 0;
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else if (`cyclestart(vc,248) && `cycleend(hc,31))
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else if (`cyclestart(vc,248) && `cycleend(hc,31))
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INT_n <= 1;
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INT_n <= 1;
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end
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end
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// Border control signal (=0 when we're not displaying paper/ink pixels)
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// Border control signal (=0 when we're not displaying paper/ink pixels)
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reg Border_n = 1;
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reg Border_n = 1;
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always @(negedge clk7) begin
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always @(negedge clk7) begin
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if ( (vc[7] & vc[6]) | vc[8] | hc[8])
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if ( (vc[7] & vc[6]) | vc[8] | hc[8])
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Border_n <= 0;
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Border_n <= 0;
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else
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else
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Border_n <= 1;
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Border_n <= 1;
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end
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end
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// VidEN generation (delaying Border 8 clocks)
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// VidEN generation (delaying Border 8 clocks)
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reg VidEN_n = 1;
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reg VidEN_n = 1;
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always @(negedge clk7) begin
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always @(negedge clk7) begin
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if (hc[3])
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if (hc[3])
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VidEN_n <= !Border_n;
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VidEN_n <= !Border_n;
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end
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end
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// DataLatch generation (posedge to capture data from memory)
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// DataLatch generation (posedge to capture data from memory)
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reg DataLatch_n = 1;
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reg DataLatch_n = 1;
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always @(negedge clk7) begin
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always @(negedge clk7) begin
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if (hc[0] & hc[1] & Border_n & hc[3])
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if (hc[0] & hc[1] & Border_n & hc[3])
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DataLatch_n <= 0;
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DataLatch_n <= 0;
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else
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else
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DataLatch_n <= 1;
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DataLatch_n <= 1;
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end
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end
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// AttrLatch generation (posedge to capture data from memory)
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// AttrLatch generation (posedge to capture data from memory)
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reg AttrLatch_n = 1;
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reg AttrLatch_n = 1;
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always @(negedge clk7) begin
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always @(negedge clk7) begin
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if (hc[0] & !hc[1] & Border_n & hc[3])
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if (hc[0] & !hc[1] & Border_n & hc[3])
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AttrLatch_n <= 0;
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AttrLatch_n <= 0;
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else
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else
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AttrLatch_n <= 1;
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AttrLatch_n <= 1;
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end
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end
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// SLoad generation (negedge to load shift register)
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// SLoad generation (negedge to load shift register)
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reg SLoad = 0;
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reg SLoad = 0;
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always @(negedge clk7) begin
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always @(negedge clk7) begin
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if (!hc[0] & !hc[1] & hc[2] & !VidEN_n)
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if (!hc[0] & !hc[1] & hc[2] & !VidEN_n)
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SLoad <= 1;
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SLoad <= 1;
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else
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else
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SLoad <= 0;
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SLoad <= 0;
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end
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end
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// AOLatch generation (negedge to update attr output latch)
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// AOLatch generation (negedge to update attr output latch)
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reg AOLatch_n = 1;
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reg AOLatch_n = 1;
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always @(negedge clk7) begin
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always @(negedge clk7) begin
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if (hc[0] & !hc[1] & hc[2])
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if (hc[0] & !hc[1] & hc[2])
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AOLatch_n <= 0;
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AOLatch_n <= 0;
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else
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else
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AOLatch_n <= 1;
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AOLatch_n <= 1;
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end
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end
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// First buffer for bitmap
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// First buffer for bitmap
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reg [7:0] BitmapReg = 0;
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reg [7:0] BitmapReg = 0;
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always @(negedge DataLatch_n) begin
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always @(negedge DataLatch_n) begin
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BitmapReg <= vramdout;
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BitmapReg <= vramdout;
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end
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end
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// Shift register (second bitmap register)
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// Shift register (second bitmap register)
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reg [7:0] SRegister = 0;
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reg [7:0] SRegister = 0;
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always @(negedge clk7) begin
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always @(negedge clk7) begin
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if (SLoad)
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if (SLoad)
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SRegister <= BitmapReg;
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SRegister <= BitmapReg;
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else
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else
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SRegister <= {SRegister[6:0],1'b0};
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SRegister <= {SRegister[6:0],1'b0};
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end
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end
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// First buffer for attribute
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// First buffer for attribute
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reg [7:0] AttrReg = 0;
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reg [7:0] AttrReg = 0;
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always @(negedge AttrLatch_n) begin
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always @(negedge AttrLatch_n) begin
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AttrReg <= vramdout;
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AttrReg <= vramdout;
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end
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end
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// Second buffer for attribute
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// Second buffer for attribute
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reg [7:0] AttrOut = 0;
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reg [7:0] AttrOut = 0;
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always @(negedge AOLatch_n) begin
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always @(negedge AOLatch_n) begin
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if (!VidEN_n)
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if (!VidEN_n)
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AttrOut <= AttrReg;
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AttrOut <= AttrReg;
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else
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else
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AttrOut <= {2'b00,BorderColor,BorderColor};
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AttrOut <= {2'b00,BorderColor,BorderColor};
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end
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end
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// Flash counter and pixel generation
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// Flash counter and pixel generation
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reg [4:0] FlashCnt = 0;
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reg [4:0] FlashCnt = 0;
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always @(negedge VSync_n) begin
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always @(negedge VSync_n) begin
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FlashCnt <= FlashCnt + 1;
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FlashCnt <= FlashCnt + 1;
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end
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end
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wire Pixel = SRegister[7] ^ (AttrOut[7] & FlashCnt[4]);
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wire Pixel = SRegister[7] ^ (AttrOut[7] & FlashCnt[4]);
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// RGB generation
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// RGB generation
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reg rI,rG,rR,rB;
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reg rI,rG,rR,rB;
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assign r = rR;
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assign r = rR;
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assign g = rG;
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assign g = rG;
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assign b = rB;
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assign b = rB;
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assign i = rI;
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assign i = rI;
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always @(*) begin
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always @(*) begin
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if (HBlank_n && VBlank_n)
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if (HBlank_n && VBlank_n)
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{rI,rG,rR,rB} = (Pixel)? {AttrOut[6],AttrOut[2:0]} : {AttrOut[6],AttrOut[5:3]};
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{rI,rG,rR,rB} = (Pixel)? {AttrOut[6],AttrOut[2:0]} : {AttrOut[6],AttrOut[5:3]};
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else
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else
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{rI,rG,rR,rB} = 4'b0000;
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{rI,rG,rR,rB} = 4'b0000;
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end
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end
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//CSync generation
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//CSync generation
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assign csync = HSync_n & VSync_n;
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assign csync = HSync_n & VSync_n;
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// VRAM address and control line generation
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// VRAM address and control line generation (TO-DO)
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reg [13:0] rVA = 0;
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reg [13:0] rVA = 0;
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reg rVCS = 0;
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reg rVCS = 0;
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reg rVOE = 0;
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reg rVOE = 0;
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reg rVWE = 0;
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reg rVWE = 0;
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assign va = rVA;
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assign vramcs = rVCS;
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assign vramoe = rVOE;
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assign vramwe = rVWE;
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// Latches to hold delayed versions of V and H counters
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// Latches to hold delayed versions of V and H counters
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reg [8:0] v = 0;
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reg [8:0] v = 0;
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reg [8:0] c = 0;
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reg [8:0] c = 0;
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// Address and control line multiplexor ULA/CPU
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// Address and control line multiplexor ULA/CPU
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always @(negedge clk7) begin
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always @(negedge clk7) begin
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if (Border_n && (hc[3:0]==4'b0111 || hc[3:0]==4'b1011)) begin // cycles 7 and 11: load V and C from VC and HC
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if (Border_n && (hc[3:0]==7 || hc[3:0]==11)) begin // cycles 7 and 11: load V and C from VC and HC
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c <= hc;
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c <= hc;
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v <= vc;
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v <= vc;
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end
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end
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end
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end
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// Address and control line multiplexor ULA/CPU
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// Address and control line multiplexor ULA/CPU
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always @(*) begin
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always @(*) begin
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if (Border_n && (hc[3:0]==4'b1000 || hc[3:0]==4'b1001 || hc[3:0]==4'b1100 || hc[3:0]==4'b1101)) begin // cycles 8 and 12: present attribute address to VRAM
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if (Border_n && (hc[3:0]==8 || hc[3:0]==9 || hc[3:0]==12 || hc[3:0]==13)) begin // cycles 8 and 12: present attribute address to VRAM
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rVA = (TimexHiColorMode)? {1'b1,v[7:6],v[2:0],v[5:3],c[7:3]} : // (cycles 9 and 13 load attr byte).
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rVA = (TimexHiColorMode)? {1'b1,v[7:6],v[2:0],v[5:3],c[7:3]} : // (cycles 9 and 13 load attr byte).
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{4'b0110,v[7:3],c[7:3]}; // Attribute address depends upon the mode selected
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{4'b0110,v[7:3],c[7:3]}; // Attribute address depends upon the mode selected
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rVCS = 1;
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rVCS = 1;
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rVOE = !hc[0];
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rVOE = !hc[0];
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rVWE = 0;
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rVWE = 0;
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end
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end
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else if (Border_n && (hc[3:0]==4'b1010 || hc[3:0]==4'b1011 || hc[3:0]==4'b1110 || hc[3:0]==4'b1111)) begin // cycles 10 and 14: present display address to VRAM
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else if (Border_n && (hc[3:0]==10 || hc[3:0]==11 || hc[3:0]==14 || hc[3:0]==15)) begin // cycles 10 and 14: present display address to VRAM
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rVA = {1'b0,v[7:6],v[2:0],v[5:3],c[7:3]}; // (cycles 11 and 15 load display byte)
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rVA = {1'b0,v[7:6],v[2:0],v[5:3],c[7:3]}; // (cycles 11 and 15 load display byte)
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rVCS = 1;
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rVCS = 1;
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rVOE = !hc[0];
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rVOE = !hc[0];
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rVWE = 0;
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rVWE = 0;
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end
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end
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else if (Border_n && hc[3:0]==4'b0000) begin
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else if (Border_n && hc[3:0]==0) begin
|
rVA = a[13:0];
|
rVA = a[13:0];
|
rVCS = 0;
|
rVCS = 0;
|
rVOE = 0;
|
rVOE = 0;
|
rVWE = 0;
|
rVWE = 0;
|
end
|
end
|
else begin // when VRAM is not in use by ULA, give it to CPU
|
else begin // when VRAM is not in use by ULA, give it to CPU
|
rVA = a[13:0];
|
|
rVCS = !a[15] & a[14] & !mreq_n;
|
|
rVOE = !rd_n;
|
|
rVWE = !wr_n;
|
|
end
|
end
|
end
|
end
|
|
|
|
// RAS/CAS/DRAMWE generation
|
|
reg rRAS_n = 1;
|
|
reg rCAS_n = 1;
|
|
reg rDRAMWE_n = 1;
|
|
wire [5:0] RCycle = {hc[3:0],clk28div};
|
|
always @(posedge clk28) begin
|
|
|
|
|
|
|
|
|
// ULA+ : palette RAM address and control bus multiplexing
|
// ULA+ : palette RAM address and control bus multiplexing
|
always @(*) begin
|
always @(*) begin
|
if (Border_n && (hc[3:0]==10 || hc[3:0]==14)) begin // present address of paper to palette RAM
|
if (Border_n && (hc[3:0]==10 || hc[3:0]==14)) begin // present address of paper to palette RAM
|
palettewe = 0;
|
palettewe = 0;
|
paletteaddr = { AttrReg[7:6],1'b1,AttrReg[5:3] };
|
paletteaddr = { AttrReg[7:6],1'b1,AttrReg[5:3] };
|
end
|
end
|
else if (Border_n && (hc[3:0]==11 || hc[3:0]==15)) begin // present address of ink to palette RAM
|
else if (Border_n && (hc[3:0]==11 || hc[3:0]==15)) begin // present address of ink to palette RAM
|
palettewe = 0;
|
palettewe = 0;
|
paletteaddr = { AttrReg[7:6],1'b0,AttrReg[2:0] };
|
paletteaddr = { AttrReg[7:6],1'b0,AttrReg[2:0] };
|
end
|
end
|
else if (dataportsel) begin // if CPU requests access, give it palette control
|
else if (dataportsel) begin // if CPU requests access, give it palette control
|
paletteaddr = ULAPlusAddrReg[5:0];
|
paletteaddr = ULAPlusAddrReg[5:0];
|
palettewe = cpu_writes_palette;
|
palettewe = cpu_writes_palette;
|
end
|
end
|
else begin // if palette RAM is not being used to display pixels, and the CPU doesn't need it, put the border color address
|
else begin // if palette RAM is not being used to display pixels, and the CPU doesn't need it, put the border color address
|
palettewe = 0; // blocking assignment, so we will first deassert WE at palette RAM...
|
palettewe = 0; // blocking assignment, so we will first deassert WE at palette RAM...
|
paletteaddr = {3'b001, BorderColor}; // ... then, we can change the palette RAM address
|
paletteaddr = {3'b001, BorderColor}; // ... then, we can change the palette RAM address
|
end
|
end
|
end
|
end
|
|
|
//ULA+ : palette reading and attribute generation
|
//ULA+ : palette reading and attribute generation
|
// First buffers for paper and ink
|
// First buffers for paper and ink
|
reg [7:0] ULAPlusPaper = 0;
|
reg [7:0] ULAPlusPaper = 0;
|
reg [7:0] ULAPlusInk = 0;
|
reg [7:0] ULAPlusInk = 0;
|
reg [7:0] ULAPlusBorder = 0;
|
reg [7:0] ULAPlusBorder = 0;
|
wire ULAPlusPixel = SRegister[7];
|
wire ULAPlusPixel = SRegister[7];
|
always @(negedge clk14) begin
|
always @(negedge clk14) begin
|
if (Border_n && (hc[3:0]==10 || hc[3:0]==14) && !clk7) // this happens 1/2 clk7 after address is settled
|
if (Border_n && (hc[3:0]==10 || hc[3:0]==14) && !clk7) // this happens 1/2 clk7 after address is settled
|
ULAPlusPaper <= palettedout;
|
ULAPlusPaper <= palettedout;
|
else if (Border_n && (hc[3:0]==11 || hc[3:0]==15) && !clk7) // this happens 1/2 clk7 after address is settled
|
else if (Border_n && (hc[3:0]==11 || hc[3:0]==15) && !clk7) // this happens 1/2 clk7 after address is settled
|
ULAPlusInk <= palettedout;
|
ULAPlusInk <= palettedout;
|
else if (hc[3:0]==12 && !dataportsel) // On cycle 12, palette RAM is not used to retrieve ink/paper color. If CPU is not reclaiming it...
|
else if (hc[3:0]==12 && !dataportsel) // On cycle 12, palette RAM is not used to retrieve ink/paper color. If CPU is not reclaiming it...
|
ULAPlusBorder <= palettedout; //... take the chance to update the BorderColor register by reading the palette RAM. The address
|
ULAPlusBorder <= palettedout; //... take the chance to update the BorderColor register by reading the palette RAM. The address
|
end // presented at the palette RAM address bus will be 001BBB, where BBB is the border color code.
|
end // presented at the palette RAM address bus will be 001BBB, where BBB is the border color code.
|
// Second buffers for paper and ink
|
// Second buffers for paper and ink
|
reg [7:0] ULAPlusPaperOut = 0;
|
reg [7:0] ULAPlusPaperOut = 0;
|
reg [7:0] ULAPlusInkOut = 0;
|
reg [7:0] ULAPlusInkOut = 0;
|
always @(negedge AOLatch_n) begin
|
always @(negedge AOLatch_n) begin
|
if (!VidEN_n) begin // if it's "paper time", load output buffers with current ink and paper color
|
if (!VidEN_n) begin // if it's "paper time", load output buffers with current ink and paper color
|
ULAPlusPaperOut <= ULAPlusPaper;
|
ULAPlusPaperOut <= ULAPlusPaper;
|
ULAPlusInkOut <= ULAPlusInk;
|
ULAPlusInkOut <= ULAPlusInk;
|
end
|
end
|
else begin // if not, it's "border/blanking time", so load output buffers with current border color
|
else begin // if not, it's "border/blanking time", so load output buffers with current border color
|
ULAPlusPaperOut <= ULAPlusBorder;
|
ULAPlusPaperOut <= ULAPlusBorder;
|
ULAPlusInkOut <= ULAPlusBorder;
|
ULAPlusInkOut <= ULAPlusBorder;
|
end
|
end
|
end
|
end
|
// ULA+ : final RGB generation depending on pixel value and blanking period.
|
// ULA+ : final RGB generation depending on pixel value and blanking period.
|
reg [7:0] rRGBULAPlus;
|
reg [7:0] rRGBULAPlus;
|
assign rgbulaplus = rRGBULAPlus;
|
assign rgbulaplus = rRGBULAPlus;
|
always @(*) begin
|
always @(*) begin
|
if (HBlank_n && VBlank_n)
|
if (HBlank_n && VBlank_n)
|
rRGBULAPlus = (ULAPlusPixel)? ULAPlusInkOut : ULAPlusPaperOut;
|
rRGBULAPlus = (ULAPlusPixel)? ULAPlusInkOut : ULAPlusPaperOut;
|
else
|
else
|
rRGBULAPlus = 8'h00;
|
rRGBULAPlus = 8'h00;
|
end
|
end
|
|
|
// CPU contention handler (Altwasser version)
|
// CPU contention handler (Altwasser version)
|
/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
|
reg CPUClk = 0;
|
reg CPUClk = 0;
|
assign clkcpu = !CPUClk; // will be negated again off ULA
|
assign clkcpu = !CPUClk; // will be negated again off ULA
|
reg ioreqtw3 = 0;
|
reg ioreqtw3 = 0;
|
reg mreqt23 = 0;
|
reg mreqt23 = 0;
|
wire iorequest_n = ioreq_n & ~dataportsel & ~addrportsel;
|
wire iorequest_n = ioreq_n & ~dataportsel & ~addrportsel;
|
wire Nor1 = (~(a[14] | ~iorequest_n)) |
|
wire Nor1 = (~(a[14] | ~iorequest_n)) |
|
(~(~a[15] | ~iorequest_n)) |
|
(~(~a[15] | ~iorequest_n)) |
|
(~(hc[2] | hc[3])) |
|
(~(hc[2] | hc[3])) |
|
(~Border_n | ~ioreqtw3 | ~CPUClk | ~mreqt23);
|
(~Border_n | ~ioreqtw3 | ~CPUClk | ~mreqt23);
|
wire Nor2 = (~(hc[2] | hc[3])) |
|
wire Nor2 = (~(hc[2] | hc[3])) |
|
~Border_n |
|
~Border_n |
|
~CPUClk |
|
~CPUClk |
|
iorequest_n |
|
iorequest_n |
|
~ioreqtw3;
|
~ioreqtw3;
|
wire CLKContention = ~Nor1 | ~Nor2;
|
wire CLKContention = ~Nor1 | ~Nor2;
|
|
|
always @(posedge CPUClk) begin
|
always @(posedge CPUClk) begin
|
ioreqtw3 <= iorequest_n;
|
ioreqtw3 <= iorequest_n;
|
mreqt23 <= mreq_n;
|
mreqt23 <= mreq_n;
|
end
|
end
|
/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
|
|
|
// // CPU contention handler (Chris version)
|
// // CPU contention handler (Chris version)
|
// /////////////////////////////////////////////////////////////////////
|
// /////////////////////////////////////////////////////////////////////
|
// reg CPUClk = 0;
|
// reg CPUClk = 0;
|
// assign clkcpu = CPUClk;
|
// assign clkcpu = CPUClk;
|
// wire ioreq_n = (a[0] | iorq_n) & ~dataportsel & ~addrportsel;
|
// wire ioreq_n = (a[0] | iorq_n) & ~dataportsel & ~addrportsel;
|
// reg ULANotReadingVRAM = 1;
|
// reg ULANotReadingVRAM = 1;
|
// reg CycleMayContend = 0;
|
// reg CycleMayContend = 0;
|
//
|
//
|
// always @(negedge clk7) begin
|
// always @(negedge clk7) begin
|
// ULANotReadingVRAM <= ~Border_n | (~hc[2] & ~hc[3]);
|
// ULANotReadingVRAM <= ~Border_n | (~hc[2] & ~hc[3]);
|
// end
|
// end
|
// always @(posedge CPUClk) begin
|
// always @(posedge CPUClk) begin
|
// CycleMayContend <= ioreq_n & mreq_n;
|
// CycleMayContend <= ioreq_n & mreq_n;
|
// end
|
// end
|
// wire CLKContention = ~(ULANotReadingVRAM | (((~a[14] | a[15]) & ioreq_n) | ~CycleMayContend));
|
// wire CLKContention = ~(ULANotReadingVRAM | (((~a[14] | a[15]) & ioreq_n) | ~CycleMayContend));
|
// /////////////////////////////////////////////////////////////////////
|
// /////////////////////////////////////////////////////////////////////
|
|
|
// // CPU modified contention handler for broken IO bus cycle of T80 core (Chris version)
|
// // CPU modified contention handler for broken IO bus cycle of T80 core (Chris version)
|
// /////////////////////////////////////////////////////////////////////
|
// /////////////////////////////////////////////////////////////////////
|
// reg CPUClk = 0;
|
// reg CPUClk = 0;
|
// assign clkcpu = CPUClk;
|
// assign clkcpu = CPUClk;
|
// wire ioreq_n = (a[0] | iorq_n) & ~dataportsel & ~addrportsel;
|
// wire ioreq_n = (a[0] | iorq_n) & ~dataportsel & ~addrportsel;
|
// reg ULANotReadingVRAM = 1;
|
// reg ULANotReadingVRAM = 1;
|
// reg CycleMayContend = 0;
|
// reg CycleMayContend = 0;
|
//
|
//
|
// always @(negedge clk7) begin
|
// always @(negedge clk7) begin
|
// ULANotReadingVRAM <= ~Border_n | (~hc[2] & ~hc[3]);
|
// ULANotReadingVRAM <= ~Border_n | (~hc[2] & ~hc[3]);
|
// end
|
// end
|
// always @(posedge CPUClk) begin
|
// always @(posedge CPUClk) begin
|
// CycleMayContend <= (ioreq_n | CPUClk) & mreq_n;
|
// CycleMayContend <= (ioreq_n | CPUClk) & mreq_n;
|
// end
|
// end
|
// wire CLKContention = ~(ULANotReadingVRAM | (((~a[14] | a[15]) & (ioreq_n | ~CPUClk)) | ~CycleMayContend));
|
// wire CLKContention = ~(ULANotReadingVRAM | (((~a[14] | a[15]) & (ioreq_n | ~CPUClk)) | ~CycleMayContend));
|
// /////////////////////////////////////////////////////////////////////
|
// /////////////////////////////////////////////////////////////////////
|
|
|
always @(posedge clk7) begin // change clk7 by clk14 for 7MHz CPU clock operation
|
always @(posedge clk7) begin // change clk7 by clk14 for 7MHz CPU clock operation
|
if (CPUClk && !CLKContention) // if there's no contention, the clock can go low
|
if (CPUClk && !CLKContention) // if there's no contention, the clock can go low
|
CPUClk <= 0;
|
CPUClk <= 0;
|
else
|
else
|
CPUClk <= 1;
|
CPUClk <= 1;
|
end
|
end
|
|
|
// ULA+ : palette management
|
// ULA+ : palette management
|
always @(posedge clk7 or negedge reset) begin
|
always @(posedge clk7 or negedge reset) begin
|
if (!reset_n)
|
if (!reset_n)
|
ULAPlusConfig <= 0;
|
ULAPlusConfig <= 0;
|
else begin
|
else begin
|
if (addrportsel && !wr_n)
|
if (addrportsel && !wr_n)
|
ULAPlusAddrReg <= din;
|
ULAPlusAddrReg <= din;
|
else if (dataportsel && !wr_n && ULAPlusAddrReg[7:6]==2'b01)
|
else if (dataportsel && !wr_n && ULAPlusAddrReg[7:6]==2'b01)
|
ULAPlusConfig <= din[0];
|
ULAPlusConfig <= din[0];
|
end
|
end
|
end
|
end
|
|
|
// ULA-CPU interface
|
// ULA-CPU interface
|
assign dout = (!a[15] && a[14] && !mreq_n && !rd_n)? vramdout : // CPU reads VRAM through ULA as in the +3, not directly
|
assign dout = (!a[15] && a[14] && !mreq_n && !rd_n)? vramdout : // CPU reads VRAM through ULA as in the +3, not directly
|
(!iorq_n && !a[0] && !rd_n)? {1'b1,ear,1'b1,kbcolumns} : // CPU reads keyboard and EAR state
|
(!iorq_n && !a[0] && !rd_n)? {1'b1,ear,1'b1,kbcolumns} : // CPU reads keyboard and EAR state
|
(!iorq_n && a[7:0]==8'hFF && !rd_n)? {6'b000000,TimexHiColorMode,1'b0} : // Timex hicolor config port. Only bit 1 is reported.
|
(!iorq_n && a[7:0]==8'hFF && !rd_n)? {6'b000000,TimexHiColorMode,1'b0} : // Timex hicolor config port. Only bit 1 is reported.
|
(addrportsel && !rd_n)? ULAPlusAddrReg : // ULA+ addr register
|
(addrportsel && !rd_n)? ULAPlusAddrReg : // ULA+ addr register
|
(dataportsel && !rd_n && ULAPlusAddrReg[7:6]==2'b01)? {7'b0000000, ULAPlusConfig} :
|
(dataportsel && !rd_n && ULAPlusAddrReg[7:6]==2'b01)? {7'b0000000, ULAPlusConfig} :
|
(dataportsel && !rd_n && ULAPlusAddrReg[7:6]==2'b00)? palettedout :
|
(dataportsel && !rd_n && ULAPlusAddrReg[7:6]==2'b00)? palettedout :
|
(Border_n)? AttrReg : // to emulate
|
(Border_n)? AttrReg : // to emulate
|
8'hFF; // port FF (well, cannot be actually FF anymore)
|
8'hFF; // port FF (well, cannot be actually FF anymore)
|
assign vramdin = din; // The CPU doesn't need to share the memory input data bus with the ULA
|
assign vramdin = din; // The CPU doesn't need to share the memory input data bus with the ULA
|
reg rMic = 0;
|
reg rMic = 0;
|
reg rSpk = 0;
|
reg rSpk = 0;
|
assign mic = rMic;
|
assign mic = rMic;
|
assign spk = rSpk;
|
assign spk = rSpk;
|
always @(negedge clk7 or negedge reset) begin
|
always @(negedge clk7 or negedge reset) begin
|
if (!reset_n)
|
if (!reset_n)
|
TimexHiColorMode <= 0;
|
TimexHiColorMode <= 0;
|
else if (!iorq_n && a[7:0]==8'hFF && !wr_n)
|
else if (!iorq_n && a[7:0]==8'hFF && !wr_n)
|
TimexHiColorMode <= din[1];
|
TimexHiColorMode <= din[1];
|
else if (!ioreq_n & !wr_n)
|
else if (!ioreq_n & !wr_n)
|
{rSpk,rMic,BorderColor} <= din[5:0];
|
{rSpk,rMic,BorderColor} <= din[5:0];
|
end
|
end
|
endmodule
|
endmodule
|
|
|
