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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// Company: Dept. Architecture and Computing Technology. University of Seville
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// Company: Dept. Architecture and Computing Technology. University of Seville
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// Engineer: Miguel Angel Rodriguez Jodar
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// Engineer: Miguel Angel Rodriguez Jodar. rodriguj@atc.us.es
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//
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//
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// Create Date: 19:13:39 4-Apr-2012
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// Create Date: 19:13:39 4-Apr-2012
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// Design Name: ULA
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// Design Name: ZX Spectrum
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// Module Name: ula_reference_design
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// Module Name: ula
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// Project Name:
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// Project Name:
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// Target Devices:
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// Target Devices:
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// Tool versions:
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// Tool versions:
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// Description:
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// Description:
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//
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//
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// Dependencies:
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// Dependencies:
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//
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//
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// Revision:
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// Revision:
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// Revision 0.01 - File Created
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// Revision 1.00 - File Created
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// Additional Comments:
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// Additional Comments: GPL License policies apply to the contents of this file.
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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`define cyclestart(a,b) ((a)==(b))
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`define cyclestart(a,b) ((a)==(b))
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`define cycleend(a,b) ((a)==(b+1))
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`define cycleend(a,b) ((a)==(b+1))
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// Address and control line multiplexor ULA/CPU
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// Address and control line multiplexor ULA/CPU
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always @(*) begin
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always @(*) begin
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if (Border_n && (hc[3:0]==4'b1000 || hc[3:0]==4'b1001 || hc[3:0]==4'b1100 || hc[3:0]==4'b1101)) begin // cycles 8 and 12: present display address to VRAM
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if (Border_n && (hc[3:0]==4'b1000 || hc[3:0]==4'b1001 || hc[3:0]==4'b1100 || hc[3:0]==4'b1101)) begin // cycles 8 and 12: present display address to VRAM
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rVA = {1'b0,v[7:6],v[2:0],v[5:3],c[7:3]}; // (cycles 9 and 13 load display byte)
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rVA = {1'b0,v[7:6],v[2:0],v[5:3],c[7:3]}; // (cycles 9 and 13 load display byte)
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rVCS = 1;
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rVCS = 1;
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rVOE = 1;
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rVOE = !hc[0];
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rVWE = 0;
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rVWE = 0;
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end
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end
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else if (Border_n && (hc[3:0]==4'b1010 || hc[3:0]==4'b1011 || hc[3:0]==4'b1110 || hc[3:0]==4'b1111)) begin // cycles 10 and 14: present attribute address to VRAM
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else if (Border_n && (hc[3:0]==4'b1010 || hc[3:0]==4'b1011 || hc[3:0]==4'b1110 || hc[3:0]==4'b1111)) begin // cycles 10 and 14: present attribute address to VRAM
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rVA = {4'b0110,v[7:3],c[7:3]}; // (cycles 11 and 15 load attr byte)
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rVA = {4'b0110,v[7:3],c[7:3]}; // (cycles 11 and 15 load attr byte)
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rVCS = 1;
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rVCS = 1;
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rVOE = 1;
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rVOE = !hc[0];
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rVWE = 0;
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end
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else if (Border_n && hc[3:0]==4'b0000) begin
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rVA = a[13:0];
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rVCS = 0;
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rVOE = 0;
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rVWE = 0;
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rVWE = 0;
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end
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end
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else begin // when VRAM is not in use by ULA, give it to CPU
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else begin // when VRAM is not in use by ULA, give it to CPU
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rVA = a[13:0];
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rVA = a[13:0];
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rVCS = !a[15] & a[14] & !mreq_n;
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rVCS = !a[15] & a[14] & !mreq_n;
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end
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end
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// ULA-CPU interface
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// ULA-CPU interface
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assign dout = (!a[15] & a[14] & !mreq_n)? vramdout : // CPU reads VRAM through ULA as in the +3, not directly
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assign dout = (!a[15] & a[14] & !mreq_n)? vramdout : // CPU reads VRAM through ULA as in the +3, not directly
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(!iorq_n & !a[0])? {1'b1,ear,1'b1,kbcolumns} : // CPU reads keyboard and EAR state
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(!iorq_n & !a[0])? {1'b1,ear,1'b1,kbcolumns} : // CPU reads keyboard and EAR state
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(Border_n)? vramdout : // to emulate
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(Border_n)? AttrReg : // to emulate
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8'hFF; // port FF
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8'hFF; // port FF
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assign vramdin = din; // The CPU doesn't need to share the memory input data bus with the ULA
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assign vramdin = din; // The CPU doesn't need to share the memory input data bus with the ULA
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assign kbrows = {a[11]? 1'bz : 0, // high impedance or 0, as if diodes were been placed in between
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assign kbrows = {a[11]? 1'bz : 1'b0, // high impedance or 0, as if diodes were been placed in between
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a[10]? 1'bz : 0, // if the keyboard matrix is to be implemented within the FPGA, then
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a[10]? 1'bz : 1'b0, // if the keyboard matrix is to be implemented within the FPGA, then
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a[9]? 1'bz : 0, // there's no need to do this.
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a[9]? 1'bz : 1'b0, // there's no need to do this.
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a[12]? 1'bz : 0,
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a[12]? 1'bz : 1'b0,
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a[13]? 1'bz : 0,
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a[13]? 1'bz : 1'b0,
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a[8]? 1'bz : 0,
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a[8]? 1'bz : 1'b0,
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a[14]? 1'bz : 0,
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a[14]? 1'bz : 1'b0,
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a[15]? 1'bz : 0 };
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a[15]? 1'bz : 1'b0 };
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// assign kbrows = {a[8]? 1'bz : 1'b0, // high impedance or 0, as if diodes were been placed in between
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// a[9]? 1'bz : 1'b0, // if the keyboard matrix is to be implemented within the FPGA, then
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// a[10]? 1'bz : 1'b0, // there's no need to do this.
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// a[11]? 1'bz : 1'b0,
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// a[12]? 1'bz : 1'b0,
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// a[13]? 1'bz : 1'b0,
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// a[14]? 1'bz : 1'b0,
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// a[15]? 1'bz : 1'b0 };
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reg rMic = 0;
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reg rMic = 0;
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reg rSpk = 0;
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reg rSpk = 0;
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assign mic = rMic;
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assign mic = rMic;
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assign spk = rSpk;
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assign spk = rSpk;
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always @(negedge clk7) begin
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always @(negedge clk7) begin
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