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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// Additional Comments:
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// Additional Comments:
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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module test_reference_ula;
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module test_standard_ula;
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// Inputs
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// Inputs
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reg clk14;
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reg clk14;
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wire [15:0] a;
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wire [15:0] a;
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wire [7:0] din;
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wire [7:0] din;
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always begin
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always begin
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clk14 = #35.714286 ~clk14;
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clk14 = #35.714286 ~clk14;
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end
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end
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endmodule
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endmodule
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module z80memr (
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input clk,
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output [15:0] a,
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output [7:0] d,
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output mreq,
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output rd
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);
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reg rmreq = 1;
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reg rrd = 1;
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assign mreq = rmreq;
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assign rd = rrd;
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reg [1:0] estado = 2;
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assign d = 8'bzzzzzzzz;
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reg [15:0] ra = 16'h7FFF;
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assign a = ra;
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always @(posedge clk) begin
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if (estado==2) begin
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estado <= 0;
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ra <= ~ra;
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end
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else
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estado <= estado + 1;
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end
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always @(*) begin
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if (estado==0 && clk)
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{rmreq,rrd} = 2'b11;
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else if (estado==0 && !clk)
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{rmreq,rrd} = 2'b00;
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else if (estado==1)
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{rmreq,rrd} = 2'b00;
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else if (estado==2 && clk)
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{rmreq,rrd} = 2'b00;
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else
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{rmreq,rrd} = 2'b11;
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end
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endmodule
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module z80memio (
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input clk,
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output [15:0] a,
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output [7:0] d,
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output mreq_n,
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output iorq_n,
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output wr_n,
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output rfsh_n
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);
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reg rmreq = 1;
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reg riorq = 1;
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reg rwr = 1;
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reg rrfsh = 1;
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assign mreq_n = rmreq;
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assign iorq_n = riorq;
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assign wr_n = rwr;
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assign rfsh_n = rrfsh;
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reg [1:0] estado = 0;
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reg [5:0] memioseq = 6'b011001;
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reg [5:0] io2seq = 5'b011000;
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reg [4:0] hiloseq = 5'b01010;
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wire memio = memioseq[0]; // 0 = mem, 1 = io
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wire hilo = hiloseq[0]; // 0 = access to lower RAM/Port FEh
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wire iohi = io2seq[0]; // 0 = port 00FF/00FE, 1 = port 40FE,40FF
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reg [15:0] ra;
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assign a = ra;
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reg [7:0] rd;
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assign d = rd;
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reg [7:0] iodata = 0;
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reg [7:0] memdata = 0;
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reg [15:0] memaddr = 16384;
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always @(posedge clk) begin
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if (estado==2 && !memio) begin
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estado <= 0;
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memioseq <= { memioseq[0], memioseq[5:1] };
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hiloseq <= { hiloseq[0], hiloseq[4:1] };
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io2seq <= { io2seq[0], io2seq[5:1] };
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memdata <= memdata + 1;
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if (memaddr == 23295)
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memaddr <= 16384;
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else
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memaddr <= memaddr + 1;
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end
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else if (estado==3 && memio) begin
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estado <= 0;
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memioseq <= { memioseq[0], memioseq[5:1] };
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hiloseq <= { hiloseq[0], hiloseq[4:1] };
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io2seq <= { io2seq[0], io2seq[5:1] };
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iodata <= iodata + 1;
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end
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else
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estado <= estado + 1;
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end
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always @(*) begin
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if (memio) begin // if this is an I/O bus cycle...
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case ({estado,clk})
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3'b001 : begin
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{rmreq,riorq,rwr} = 3'b111;
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ra = {1'b0, iohi, 13'b0000001111111, hilo};
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rd = 8'bzzzzzzzz;
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end
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3'b000 : begin
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{rmreq,riorq,rwr} = 3'b111;
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ra = {1'b0, iohi, 13'b0000001111111, hilo};
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rd = iodata;
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end
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3'b011,3'b010,3'b101,3'b100,3'b111 :
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begin
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{rmreq,riorq,rwr} = 3'b100;
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ra = {1'b0, iohi, 13'b0000001111111, hilo};
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rd = iodata;
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end
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3'b110 : begin
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{rmreq,riorq,rwr} = 3'b111;
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ra = {1'b0, iohi, 13'b0000001111111, hilo};
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rd = iodata;
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end
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endcase
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end
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else begin // this is a MEM bus cycle
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case ({estado,clk})
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3'b001 : begin
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{rmreq,riorq,rwr} = 3'b111;
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ra = {hilo,memaddr[14:0]};
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rd = 8'bzzzzzzzz;
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end
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3'b000,3'b011 :
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begin
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{rmreq,riorq,rwr} = 3'b011;
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ra = {hilo,memaddr[14:0]};
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rd = memdata;
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end
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3'b010,3'b101 :
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begin
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{rmreq,riorq,rwr} = 3'b010;
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ra = {hilo,memaddr[14:0]};
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rd = memdata;
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end
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3'b100 : begin
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{rmreq,riorq,rwr} = 3'b111;
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ra = {hilo,memaddr[14:0]};
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rd = memdata;
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end
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endcase
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end
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end
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endmodule
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No newline at end of file
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No newline at end of file
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