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https://opencores.org/ocsvn/System09/System09/trunk
Subversion Repositories System09
[/] [System09/] [trunk/] [rtl/] [System09_Digilent_3S200/] [System09_Digilent_3S200.ucf] - Rev 122
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#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "sys_clk" LOC = "T9" ;
#
# PUSH BUTTONS
#
NET "rst_sw" LOC = "L14" ;
NET "nmi_sw" LOC = "L13" ;
#
# LEDs
#
NET "leds<0>" LOC = "K12";
NET "leds<1>" LOC = "P14";
NET "leds<2>" LOC = "L12";
NET "leds<3>" LOC = "N14";
NET "leds<4>" LOC = "P13";
NET "leds<5>" LOC = "N12";
NET "leds<6>" LOC = "P12";
NET "leds<7>" LOC = "P11";
#
# Switches
#
NET "switches<0>" LOC = "F12";
NET "switches<1>" LOC = "G12";
NET "switches<2>" LOC = "H14";
NET "switches<3>" LOC = "H13";
NET "switches<4>" LOC = "J14";
NET "switches<5>" LOC = "J13";
NET "switches<6>" LOC = "K14";
NET "switches<7>" LOC = "K13";
#
# PS/2 KEYBOARD
#
NET "ps2c" LOC = "M16" ;
NET "ps2d" LOC = "M15" ;
#
# UART
#
NET "rxd" LOC = "T13" ;
NET "txd" LOC = "R13" ;
#
# VDU
#
NET "red" LOC = "R12" ;
NET "green" LOC = "T12" ;
NET "blue" LOC = "R11" ;
NET "hs" LOC = "R9" ;
NET "vs" LOC = "T10" ;
#
# 7 SEGMENT DISPLAY
#
NET "segments<0>" LOC = "E14";
NET "segments<1>" LOC = "G13";
NET "segments<2>" LOC = "N15";
NET "segments<3>" LOC = "P15";
NET "segments<4>" LOC = "R16";
NET "segments<5>" LOC = "F13";
NET "segments<6>" LOC = "N16";
NET "segments<7>" LOC = "P16";
NET "digits<0>" LOC = "D14";
NET "digits<1>" LOC = "G14";
NET "digits<2>" LOC = "F14";
NET "digits<3>" LOC = "E13";
#
# RAM Address bus
#
NET "ram_addr<0>" LOC = "L5" ;
NET "ram_addr<1>" LOC = "N3" ;
NET "ram_addr<2>" LOC = "M4" ;
NET "ram_addr<3>" LOC = "M3" ;
NET "ram_addr<4>" LOC = "L4" ;
NET "ram_addr<5>" LOC = "G4" ;
NET "ram_addr<6>" LOC = "F3" ;
NET "ram_addr<7>" LOC = "F4" ;
NET "ram_addr<8>" LOC = "E3" ;
NET "ram_addr<9>" LOC = "E4" ;
NET "ram_addr<10>" LOC = "G5" ;
NET "ram_addr<11>" LOC = "H3" ;
NET "ram_addr<12>" LOC = "H4" ;
NET "ram_addr<13>" LOC = "J4" ;
NET "ram_addr<14>" LOC = "J3" ;
NET "ram_addr<15>" LOC = "K3" ;
NET "ram_addr<16>" LOC = "K5" ;
NET "ram_addr<17>" LOC = "L3" ;
NET "ram_oen" LOC = "K4" ;
NET "ram_wen" LOC = "G3" ;
#
# RAM1
#
NET "ram1_cen" LOC = "P7" ;
NET "ram1_lbn" LOC = "P6" ;
NET "ram1_ubn" LOC = "T4" ;
NET "ram1_data<0>" LOC = "N7" ;
NET "ram1_data<1>" LOC = "T8" ;
NET "ram1_data<2>" LOC = "R6" ;
NET "ram1_data<3>" LOC = "T5" ;
NET "ram1_data<4>" LOC = "R5" ;
NET "ram1_data<5>" LOC = "C2" ;
NET "ram1_data<6>" LOC = "C1" ;
NET "ram1_data<7>" LOC = "B1" ;
NET "ram1_data<8>" LOC = "D3" ;
NET "ram1_data<9>" LOC = "P8" ;
NET "ram1_data<10>" LOC = "F2" ;
NET "ram1_data<11>" LOC = "H1" ;
NET "ram1_data<12>" LOC = "J2" ;
NET "ram1_data<13>" LOC = "L2" ;
NET "ram1_data<14>" LOC = "P1" ;
NET "ram1_data<15>" LOC = "R1" ;
#
# RAM2
#
NET "ram2_cen" LOC = "N5" ;
NET "ram2_lbn" LOC = "P5" ;
NET "ram2_ubn" LOC = "R4" ;
NET "ram2_data<0>" LOC = "P2" ;
NET "ram2_data<1>" LOC = "N2" ;
NET "ram2_data<2>" LOC = "M2" ;
NET "ram2_data<3>" LOC = "K1" ;
NET "ram2_data<4>" LOC = "J1" ;
NET "ram2_data<5>" LOC = "G2" ;
NET "ram2_data<6>" LOC = "E1" ;
NET "ram2_data<7>" LOC = "D1" ;
NET "ram2_data<8>" LOC = "D2" ;
NET "ram2_data<9>" LOC = "E2" ;
NET "ram2_data<10>" LOC = "G1" ;
NET "ram2_data<11>" LOC = "F5" ;
NET "ram2_data<12>" LOC = "C3" ;
NET "ram2_data<13>" LOC = "K2" ;
NET "ram2_data<14>" LOC = "M1" ;
NET "ram2_data<15>" LOC = "N1" ;
#
# Timing Constraints
#
NET "sys_clk" TNM_NET = "sys_clk";
TIMESPEC "TS_sys_clk" = PERIOD "sys_clk" 20 ns LOW 50 %;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE
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