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[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.srcs/] [sources_1/] [ip/] [axi_uartlite_module_sim/] [axi_uartlite_module_sim_stub.vhdl] - Rev 2
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-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 -- Date : Thu Jul 23 09:49:59 2020 -- Host : gigant.modulew.local running 64-bit Red Hat Enterprise Linux Server release 6.9 (Santiago) -- Command : write_vhdl -force -mode synth_stub -rename_top axi_uartlite_module_sim -prefix -- axi_uartlite_module_sim_ axi_uartlite_module_stub.vhdl -- Design : axi_uartlite_module -- Purpose : Stub declaration of top-level module interface -- Device : xc7k325tffg900-2 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity axi_uartlite_module_sim is Port ( s_axi_aclk : in STD_LOGIC; s_axi_aresetn : in STD_LOGIC; interrupt : out STD_LOGIC; s_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; rx : in STD_LOGIC; tx : out STD_LOGIC ); end axi_uartlite_module_sim; architecture stub of axi_uartlite_module_sim is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,interrupt,s_axi_awaddr[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[3:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,rx,tx"; attribute x_core_info : string; attribute x_core_info of stub : architecture is "axi_uartlite,Vivado 2017.4"; begin end;