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Subversion Repositories ahbmaster
[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [component/] [work/] [top/] [top_DataSheet.xml] - Rev 3
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<?xml version="1.0" encoding="ISO-8859-1" ?><?xml-stylesheet type="text/xsl" href="datasheet.xsl"?><datasheet><header>top</header><project-settings><fam>ProASIC3</fam><die>A3PN250</die><package>100 VQFP</package><speed-grade>STD</speed-grade><voltage>1.5</voltage><hdl-type>VHDL</hdl-type><project-description></project-description><location>C:/Actelprj/test79_AHBmaster/component/work/top</location><state>GENERATED ( Sat Jun 02 22:53:04 2018 )</state><swide-toolchain>SoftConsole workspace has not been generated</swide-toolchain></project-settings><site-map></site-map><fileset><name>HDL File(s)</name><file>C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHB2APB\1.1.101\rtl\vhdl\u\CoreAHB2APB.vhd</file><file>C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_addrdec.vhd</file><file>C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_defaultslavesm.vhd</file><file>C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd</file><file>C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd</file><file>C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_pkg.vhd</file><file>C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_slavearbiter.vhd</file><file>C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_slavestage.vhd</file><file>C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd</file><file>C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\MuxP2B.vhd</file><file>C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\components.vhd</file><file>C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd</file><file>C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Clock_gen.vhd</file><file>C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\components.vhd</file><file>C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd</file><file>C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd</file><file>C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\coreuart_pkg.vhd</file><file>C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\fifo_256x8_pa3.vhd</file><file>C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd</file><file>C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd</file><file>C:\Actelprj\test79_AHBmaster\component\work\top\top.vhd</file><file>C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd</file><file>C:\Actelprj\test79_AHBmaster\smartgen\FlashROM\FlashROM.vhd</file></fileset><io><port-name>ADDR[6]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAOUT[2]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>ADDR[1]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAOUT[24]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAIN[7]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAIN[11]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>ADDR[0]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>ADDR[23]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>ADDR[15]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAOUT[13]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAIN[25]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>ADDR[24]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>ADDR[2]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAOUT[20]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAOUT[8]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>ADDR[27]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>ADDR[18]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAIN[26]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAOUT[9]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>LWRITE</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAOUT[31]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAIN[18]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAOUT[26]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAIN[13]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAOUT[25]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAIN[12]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAIN[20]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAIN[1]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>ADDR[25]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>ADDR[28]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAOUT[3]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>ADDR[9]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAIN[27]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAOUT[27]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAIN[14]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAIN[29]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>RESP_err[1]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAOUT[10]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAOUT[14]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>RESP_err[0]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>LREAD</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAIN[8]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>ADDR[3]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAIN[3]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAIN[2]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>ADDR[16]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>ADDR[19]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>ADDR[11]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>ADDR[10]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>ADDR[4]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAOUT[22]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAIN[9]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAIN[21]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAOUT[21]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAIN[4]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAOUT[16]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAOUT[4]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAOUT[15]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>ADDR[12]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAIN[30]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>TX</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAOUT[28]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAIN[15]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAOUT[17]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>ADDR[5]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>ADDR[26]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>ADDR[21]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>ADDR[20]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAOUT[29]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAIN[16]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAIN[28]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAOUT[0]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAIN[23]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAIN[22]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>ahb_busy</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAOUT[11]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>HCLK</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAOUT[6]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>ADDR[22]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAOUT[5]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>ADDR[7]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAOUT[23]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAIN[10]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAIN[24]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAOUT[12]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAOUT[30]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAIN[17]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAOUT[7]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAIN[5]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAIN[31]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>ADDR[31]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>ADDR[13]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>HRESETn</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>ADDR[30]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAIN[6]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>ADDR[14]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>ADDR[17]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAOUT[18]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>ADDR[29]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAIN[0]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAOUT[1]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>ADDR[8]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAIN[19]</port-name><direction>IN</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><io><port-name>DATAOUT[19]</port-name><direction>OUT</direction><pin-number>-</pin-number><io-standard>LVTTL</io-standard></io><core><core-name>AHBMASTER_FIC_0</core-name></core><core type="SpiritModule"><core-exttype>IP</core-exttype><core-type>SpiritModule</core-type><core-vendor>Actel</core-vendor><core-lib>DirectCore</core-lib><core-intname>CoreAHB2APB</core-intname><core-ver>1.1.101</core-ver><core-desc>The CoreAHB2APB is an AHB slave which provides an interface (bridge) between the high- speed AHB domain and the low-power APB domain.</core-desc><core-name>CoreAHB2APB_0</core-name></core><core type="SpiritModule"><core-exttype>IP</core-exttype><core-type>SpiritModule</core-type><core-vendor>Actel</core-vendor><core-lib>DirectCore</core-lib><core-intname>CoreAHBLite</core-intname><core-ver>5.3.101</core-ver><core-desc>The CoreAHBLite component implements a multi-master AHB-Lite bus. It provides up to 4 AHB-Lite master interfaces, and up to 16 AHB-Lite slave interfaces. It is possible to allocate one or more slave slots to a "combined region" that is accessed through a further slave interface. Slave slots allocated to the combined region are not available for separate connection.</core-desc><core-param><param-name>FPGA Family:</param-name><param-value>ProASIC3</param-value><param-hdlname>FAMILY</param-hdlname><param-hdlvalue>15</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Address range seen by slave connected to huge (2GB) slot interface:</param-name><param-value>0x80000000 - 0xFFFFFFFF</param-value><param-hdlname>HADDR_SHG_CFG</param-hdlname><param-hdlvalue>1</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M0 can access slot 0:</param-name><param-value>true</param-value><param-hdlname>M0_AHBSLOT0ENABLE</param-hdlname><param-hdlvalue>1</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M0 can access slot 1:</param-name><param-value>false</param-value><param-hdlname>M0_AHBSLOT1ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M0 can access slot 2:</param-name><param-value>false</param-value><param-hdlname>M0_AHBSLOT2ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M0 can access slot 3:</param-name><param-value>false</param-value><param-hdlname>M0_AHBSLOT3ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M0 can access slot 4:</param-name><param-value>false</param-value><param-hdlname>M0_AHBSLOT4ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M0 can access slot 5:</param-name><param-value>false</param-value><param-hdlname>M0_AHBSLOT5ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M0 can access slot 6:</param-name><param-value>false</param-value><param-hdlname>M0_AHBSLOT6ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M0 can access slot 7:</param-name><param-value>false</param-value><param-hdlname>M0_AHBSLOT7ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M0 can access slot 8:</param-name><param-value>false</param-value><param-hdlname>M0_AHBSLOT8ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M0 can access slot 9:</param-name><param-value>false</param-value><param-hdlname>M0_AHBSLOT9ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M0 can access slot 10:</param-name><param-value>false</param-value><param-hdlname>M0_AHBSLOT10ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M0 can access slot 11:</param-name><param-value>false</param-value><param-hdlname>M0_AHBSLOT11ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M0 can access slot 12:</param-name><param-value>false</param-value><param-hdlname>M0_AHBSLOT12ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M0 can access slot 13:</param-name><param-value>false</param-value><param-hdlname>M0_AHBSLOT13ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M0 can access slot 14:</param-name><param-value>false</param-value><param-hdlname>M0_AHBSLOT14ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M0 can access slot 15:</param-name><param-value>false</param-value><param-hdlname>M0_AHBSLOT15ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M0 can access slot 16 (combined/huge):</param-name><param-value>false</param-value><param-hdlname>M0_AHBSLOT16ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M1 can access slot 0:</param-name><param-value>false</param-value><param-hdlname>M1_AHBSLOT0ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M1 can access slot 1:</param-name><param-value>false</param-value><param-hdlname>M1_AHBSLOT1ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M1 can access slot 2:</param-name><param-value>false</param-value><param-hdlname>M1_AHBSLOT2ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M1 can access slot 3:</param-name><param-value>false</param-value><param-hdlname>M1_AHBSLOT3ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M1 can access slot 4:</param-name><param-value>false</param-value><param-hdlname>M1_AHBSLOT4ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M1 can access slot 5:</param-name><param-value>false</param-value><param-hdlname>M1_AHBSLOT5ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M1 can access slot 6:</param-name><param-value>false</param-value><param-hdlname>M1_AHBSLOT6ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M1 can access slot 7:</param-name><param-value>false</param-value><param-hdlname>M1_AHBSLOT7ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M1 can access slot 8:</param-name><param-value>false</param-value><param-hdlname>M1_AHBSLOT8ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M1 can access slot 9:</param-name><param-value>false</param-value><param-hdlname>M1_AHBSLOT9ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M1 can access slot 10:</param-name><param-value>false</param-value><param-hdlname>M1_AHBSLOT10ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M1 can access slot 11:</param-name><param-value>false</param-value><param-hdlname>M1_AHBSLOT11ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M1 can access slot 12:</param-name><param-value>false</param-value><param-hdlname>M1_AHBSLOT12ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M1 can access slot 13:</param-name><param-value>false</param-value><param-hdlname>M1_AHBSLOT13ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M1 can access slot 14:</param-name><param-value>false</param-value><param-hdlname>M1_AHBSLOT14ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M1 can access slot 15:</param-name><param-value>false</param-value><param-hdlname>M1_AHBSLOT15ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M1 can access slot 16 (combined/huge):</param-name><param-value>false</param-value><param-hdlname>M1_AHBSLOT16ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M2 can access slot 0:</param-name><param-value>false</param-value><param-hdlname>M2_AHBSLOT0ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M2 can access slot 1:</param-name><param-value>false</param-value><param-hdlname>M2_AHBSLOT1ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M2 can access slot 2:</param-name><param-value>false</param-value><param-hdlname>M2_AHBSLOT2ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M2 can access slot 3:</param-name><param-value>false</param-value><param-hdlname>M2_AHBSLOT3ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M2 can access slot 4:</param-name><param-value>false</param-value><param-hdlname>M2_AHBSLOT4ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M2 can access slot 5:</param-name><param-value>false</param-value><param-hdlname>M2_AHBSLOT5ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M2 can access slot 6:</param-name><param-value>false</param-value><param-hdlname>M2_AHBSLOT6ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M2 can access slot 7:</param-name><param-value>false</param-value><param-hdlname>M2_AHBSLOT7ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M2 can access slot 8:</param-name><param-value>false</param-value><param-hdlname>M2_AHBSLOT8ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M2 can access slot 9:</param-name><param-value>false</param-value><param-hdlname>M2_AHBSLOT9ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M2 can access slot 10:</param-name><param-value>false</param-value><param-hdlname>M2_AHBSLOT10ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M2 can access slot 11:</param-name><param-value>false</param-value><param-hdlname>M2_AHBSLOT11ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M2 can access slot 12:</param-name><param-value>false</param-value><param-hdlname>M2_AHBSLOT12ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M2 can access slot 13:</param-name><param-value>false</param-value><param-hdlname>M2_AHBSLOT13ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M2 can access slot 14:</param-name><param-value>false</param-value><param-hdlname>M2_AHBSLOT14ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M2 can access slot 15:</param-name><param-value>false</param-value><param-hdlname>M2_AHBSLOT15ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M2 can access slot 16 (combined/huge):</param-name><param-value>false</param-value><param-hdlname>M2_AHBSLOT16ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M3 can access slot 0:</param-name><param-value>false</param-value><param-hdlname>M3_AHBSLOT0ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M3 can access slot 1:</param-name><param-value>false</param-value><param-hdlname>M3_AHBSLOT1ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M3 can access slot 2:</param-name><param-value>false</param-value><param-hdlname>M3_AHBSLOT2ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M3 can access slot 3:</param-name><param-value>false</param-value><param-hdlname>M3_AHBSLOT3ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M3 can access slot 4:</param-name><param-value>false</param-value><param-hdlname>M3_AHBSLOT4ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M3 can access slot 5:</param-name><param-value>false</param-value><param-hdlname>M3_AHBSLOT5ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M3 can access slot 6:</param-name><param-value>false</param-value><param-hdlname>M3_AHBSLOT6ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M3 can access slot 7:</param-name><param-value>false</param-value><param-hdlname>M3_AHBSLOT7ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M3 can access slot 8:</param-name><param-value>false</param-value><param-hdlname>M3_AHBSLOT8ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M3 can access slot 9:</param-name><param-value>false</param-value><param-hdlname>M3_AHBSLOT9ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M3 can access slot 10:</param-name><param-value>false</param-value><param-hdlname>M3_AHBSLOT10ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M3 can access slot 11:</param-name><param-value>false</param-value><param-hdlname>M3_AHBSLOT11ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M3 can access slot 12:</param-name><param-value>false</param-value><param-hdlname>M3_AHBSLOT12ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M3 can access slot 13:</param-name><param-value>false</param-value><param-hdlname>M3_AHBSLOT13ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M3 can access slot 14:</param-name><param-value>false</param-value><param-hdlname>M3_AHBSLOT14ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M3 can access slot 15:</param-name><param-value>false</param-value><param-hdlname>M3_AHBSLOT15ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>M3 can access slot 16 (combined/huge):</param-name><param-value>false</param-value><param-hdlname>M3_AHBSLOT16ENABLE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Memory space:</param-name><param-value>4GB addressable space apportioned into 16 slave slots, each of size 256MB</param-value><param-hdlname>MEMSPACE</param-hdlname><param-hdlvalue>1</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Slot 0:</param-name><param-value>false</param-value><param-hdlname>SC_0</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Slot 1:</param-name><param-value>false</param-value><param-hdlname>SC_1</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Slot 2:</param-name><param-value>false</param-value><param-hdlname>SC_2</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Slot 3:</param-name><param-value>false</param-value><param-hdlname>SC_3</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Slot 4:</param-name><param-value>false</param-value><param-hdlname>SC_4</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Slot 5:</param-name><param-value>false</param-value><param-hdlname>SC_5</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Slot 6:</param-name><param-value>false</param-value><param-hdlname>SC_6</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Slot 7:</param-name><param-value>false</param-value><param-hdlname>SC_7</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Slot 8:</param-name><param-value>false</param-value><param-hdlname>SC_8</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Slot 9:</param-name><param-value>false</param-value><param-hdlname>SC_9</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Slot 10:</param-name><param-value>false</param-value><param-hdlname>SC_10</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Slot 11:</param-name><param-value>false</param-value><param-hdlname>SC_11</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Slot 12:</param-name><param-value>false</param-value><param-hdlname>SC_12</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Slot 13:</param-name><param-value>false</param-value><param-hdlname>SC_13</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Slot 14:</param-name><param-value>false</param-value><param-hdlname>SC_14</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Slot 15:</param-name><param-value>false</param-value><param-hdlname>SC_15</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-name>CoreAHBLite_0</core-name></core><core type="SpiritModule"><core-exttype>IP</core-exttype><core-type>SpiritModule</core-type><core-vendor>Actel</core-vendor><core-lib>DirectCore</core-lib><core-intname>CoreAPB</core-intname><core-ver>1.1.101</core-ver><core-desc>The CoreAPB controller implements an AMBA APB fabric with the same implementation modelas the CoreAHBLite controller. The CoreAHB2APB bridge does the actual address decodingand SEL generation so primarily what this component does is the PRDATA multiplexing.There is one APB Master interface which is typically connected to the CoreAPB bridge,and 16 APB slave interfaces. There are 16 slots available each of 16MB addressablespace each.</core-desc><core-param><param-name>Slot 0:</param-name><param-value>true</param-value><param-hdlname>ApbSlot0Enable</param-hdlname><param-hdlvalue>1</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Slot 1:</param-name><param-value>false</param-value><param-hdlname>ApbSlot1Enable</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Slot 2:</param-name><param-value>false</param-value><param-hdlname>ApbSlot2Enable</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Slot 3:</param-name><param-value>false</param-value><param-hdlname>ApbSlot3Enable</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Slot 4:</param-name><param-value>false</param-value><param-hdlname>ApbSlot4Enable</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Slot 5:</param-name><param-value>false</param-value><param-hdlname>ApbSlot5Enable</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Slot 6:</param-name><param-value>false</param-value><param-hdlname>ApbSlot6Enable</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Slot 7:</param-name><param-value>false</param-value><param-hdlname>ApbSlot7Enable</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Slot 8:</param-name><param-value>false</param-value><param-hdlname>ApbSlot8Enable</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Slot 9:</param-name><param-value>false</param-value><param-hdlname>ApbSlot9Enable</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Slot 10:</param-name><param-value>false</param-value><param-hdlname>ApbSlot10Enable</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Slot 11:</param-name><param-value>false</param-value><param-hdlname>ApbSlot11Enable</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Slot 12:</param-name><param-value>false</param-value><param-hdlname>ApbSlot12Enable</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Slot 13:</param-name><param-value>false</param-value><param-hdlname>ApbSlot13Enable</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Slot 14:</param-name><param-value>false</param-value><param-hdlname>ApbSlot14Enable</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Slot 15:</param-name><param-value>false</param-value><param-hdlname>ApbSlot15Enable</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-name>CoreAPB_0</core-name></core><core type="SpiritModule"><core-exttype>IP</core-exttype><core-type>SpiritModule</core-type><core-vendor>Actel</core-vendor><core-lib>DirectCore</core-lib><core-intname>CoreUARTapb</core-intname><core-ver>5.6.102</core-ver><core-desc>CoreUARTapb is a serial communication controller with a flexible serial data interface that is intended primarily for embedded systems. The controller operates as an asynchronous (UART) with a control register interface and APB wrapper.</core-desc><core-param><param-name>Fractional Part of Baud Value:</param-name><param-value>+0.0</param-value><param-hdlname>BAUD_VAL_FRCTN</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Enable Extra Precision:</param-name><param-value>false</param-value><param-hdlname>BAUD_VAL_FRCTN_EN</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Baud Value:</param-name><param-value>1</param-value><param-hdlname>BAUD_VALUE</param-hdlname><param-hdlvalue>1</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>FPGA Family:</param-name><param-value>ProASIC3</param-value><param-hdlname>FAMILY</param-hdlname><param-hdlvalue>15</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Configuration:</param-name><param-value>Fixed</param-value><param-hdlname>FIXEDMODE</param-hdlname><param-hdlvalue>1</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Character Size:</param-name><param-value>8 bits</param-value><param-hdlname>PRG_BIT8</param-hdlname><param-hdlvalue>1</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>Parity:</param-name><param-value>Parity Disabled</param-value><param-hdlname>PRG_PARITY</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>RX FIFO:</param-name><param-value>Disable RX FIFO</param-value><param-hdlname>RX_FIFO</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>RX Legacy Mode:</param-name><param-value>Disabled</param-value><param-hdlname>RX_LEGACY_MODE</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-param><param-name>TX FIFO:</param-name><param-value>Disable TX FIFO</param-value><param-hdlname>TX_FIFO</param-hdlname><param-hdlvalue>0</param-hdlvalue><param-tag>spirit:hwParameter</param-tag></core-param><core-name>CoreUARTapb_0</core-name></core><memorysystem><title>Memory Map for top</title><description>The project contains the following subsystems:</description><subsystems><subsystem><name>AHBMASTER_FIC_0</name><master>AHBMASTER_FIC_0</master><addressNames><count>2</count><name>NoRemap</name><name>M0_SwapSlots0and1</name></addressNames><slave><name>CoreUARTapb_0</name><fullPinName>CoreUARTapb_0:APB_bif</fullPinName><remapAddress name="NoRemap">0x00000000</remapAddress><fullAddressSpace name="NoRemap">0x00000000 - 0x00FFFFFF</fullAddressSpace><remapAddress name="M0_SwapSlots0and1">0x10000000</remapAddress><fullAddressSpace name="M0_SwapSlots0and1">0x10000000 - 0x10FFFFFF</fullAddressSpace><range>0x01000000</range></slave></subsystem></subsystems></memorysystem></datasheet>