Subversion Repositories ahbmaster

#defaultlanguage:vhdl
#OPTIONS:"|-layerid|0|-orig_srs|C:\\Actelprj\\test79_AHBmaster\\synthesis\\synwork\\top_comp.srs|-top|work.top|-prodtype|synplify_pro|-nram|-fixsmult|-divnmod|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-vhdl2008|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|COREAHBLITE_LIB|-lib|COREUARTAPB_LIB|-lib|COREUARTAPB_LIB|-lib|COREUARTAPB_LIB|-lib|COREUARTAPB_LIB|-lib|COREUARTAPB_LIB|-lib|COREUARTAPB_LIB|-lib|COREUARTAPB_LIB|-lib|COREAHBLITE_LIB|-lib|COREUARTAPB_LIB|-lib|work"
#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\bin64\\c_vhdl.exe":1479949892
#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\lib\\vhd2008\\location.map":1478775588
#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\lib\\vhd2008\\std.vhd":1487912986
#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\lib\\vhd\\snps_haps_pkg.vhd":1487912854
#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\lib\\vhd2008\\std1164.vhd":1487912986
#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\lib\\vhd2008\\std_textio.vhd":1487912986
#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\lib\\vhd2008\\numeric.vhd":1487912986
#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\lib\\vhd\\umr_capim.vhd":1487912854
#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\lib\\vhd2008\\arith.vhd":1487912986
#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\lib\\vhd2008\\unsigned.vhd":1487912986
#CUR:"C:\\Microsemi\\Libero_SoC_v11.8\\SynplifyPro\\lib\\vhd\\hyperents.vhd":1487912854
#CUR:"C:\\Actelprj\\test79_AHBmaster\\hdl\\AHBMASTER_FIC.vhd":1527947376
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\Actel\\DirectCore\\CoreAHB2APB\\1.1.101\\rtl\\vhdl\\u\\CoreAHB2APB.vhd":1527947216
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\Actel\\DirectCore\\CoreAPB\\1.1.101\\rtl\\vhdl\\o\\MuxP2B.vhd":1527947216
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\Actel\\DirectCore\\CoreAPB\\1.1.101\\rtl\\vhdl\\o\\CoreAPB.vhd":1527947216
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\Actel\\DirectCore\\CoreAHBLite\\5.3.101\\rtl\\vhdl\\core\\coreahblite_addrdec.vhd":1527947216
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\Actel\\DirectCore\\CoreAHBLite\\5.3.101\\rtl\\vhdl\\core\\coreahblite_defaultslavesm.vhd":1527947216
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\Actel\\DirectCore\\CoreAHBLite\\5.3.101\\rtl\\vhdl\\core\\coreahblite_masterstage.vhd":1527947216
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\Actel\\DirectCore\\CoreAHBLite\\5.3.101\\rtl\\vhdl\\core\\coreahblite_slavearbiter.vhd":1527947216
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\Actel\\DirectCore\\CoreAHBLite\\5.3.101\\rtl\\vhdl\\core\\coreahblite_slavestage.vhd":1527947216
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\Actel\\DirectCore\\CoreAHBLite\\5.3.101\\rtl\\vhdl\\core\\coreahblite_matrix4x16.vhd":1527947216
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\Actel\\DirectCore\\CoreAHBLite\\5.3.101\\rtl\\vhdl\\core\\coreahblite_pkg.vhd":1527947216
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\CoreAHBLite_0\\rtl\\vhdl\\core\\coreahblite.vhd":1527947577
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\CoreUARTapb_0\\rtl\\vhdl\\core\\Clock_gen.vhd":1527947577
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\CoreUARTapb_0\\rtl\\vhdl\\core\\Rx_async.vhd":1527947577
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\CoreUARTapb_0\\rtl\\vhdl\\core\\Tx_async.vhd":1527947577
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\CoreUARTapb_0\\rtl\\vhdl\\core\\fifo_256x8_pa3.vhd":1527947577
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\CoreUARTapb_0\\rtl\\vhdl\\core\\coreuart_pkg.vhd":1527947577
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\CoreUARTapb_0\\rtl\\vhdl\\core\\CoreUART.vhd":1527947577
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\CoreUARTapb_0\\rtl\\vhdl\\core\\CoreUARTapb.vhd":1527947577
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\CoreAHBLite_0\\rtl\\vhdl\\core\\components.vhd":1527947577
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\CoreUARTapb_0\\rtl\\vhdl\\core\\components.vhd":1527947577
#CUR:"C:\\Actelprj\\test79_AHBmaster\\component\\work\\top\\top.vhd":1527947577
0 "C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd" vhdl
1 "C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHB2APB\1.1.101\rtl\vhdl\u\CoreAHB2APB.vhd" vhdl
2 "C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\MuxP2B.vhd" vhdl
3 "C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAPB\1.1.101\rtl\vhdl\o\CoreAPB.vhd" vhdl
4 "C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_addrdec.vhd" vhdl
5 "C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_defaultslavesm.vhd" vhdl
6 "C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_masterstage.vhd" vhdl
7 "C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_slavearbiter.vhd" vhdl
8 "C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_slavestage.vhd" vhdl
9 "C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_matrix4x16.vhd" vhdl
10 "C:\Actelprj\test79_AHBmaster\component\Actel\DirectCore\CoreAHBLite\5.3.101\rtl\vhdl\core\coreahblite_pkg.vhd" vhdl
11 "C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\coreahblite.vhd" vhdl
12 "C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Clock_gen.vhd" vhdl
13 "C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd" vhdl
14 "C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd" vhdl
15 "C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\fifo_256x8_pa3.vhd" vhdl
16 "C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\coreuart_pkg.vhd" vhdl
17 "C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd" vhdl
18 "C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd" vhdl
19 "C:\Actelprj\test79_AHBmaster\component\work\top\CoreAHBLite_0\rtl\vhdl\core\components.vhd" vhdl
20 "C:\Actelprj\test79_AHBmaster\component\work\top\CoreUARTapb_0\rtl\vhdl\core\components.vhd" vhdl
21 "C:\Actelprj\test79_AHBmaster\component\work\top\top.vhd" vhdl

# Dependency Lists (Uses list)
0 -1
1 -1
2 -1
3 2 
4 -1
5 -1
6 4 5 
7 -1
8 7 
9 6 8 
10 -1
11 9 10 
12 -1
13 -1
14 -1
15 -1
16 -1
17 12 14 13 15 16 
18 17 16 
19 -1
20 -1
21 0 1 11 3 18 19 20 

# Dependency Lists (Users Of)
0 21 
1 21 
2 3 
3 21 
4 6 
5 6 
6 9 
7 8 
8 9 
9 11 
10 11 
11 21 
12 17 
13 17 
14 17 
15 17 
16 18 17 
17 18 
18 21 
19 21 
20 21 
21 -1

# Design Unit to File Association
arch work ahbmaster_fic rtl 0
module work ahbmaster_fic 0
arch work coreahb2apb synth 1
module work coreahb2apb 1
arch work coreapb_l coreapb_li0 2
module work coreapb_l 2
arch work coreapb coreapb_o 3
module work coreapb 3
arch coreahblite_lib coreahblite_addrdec coreahblite_addrdec_arch 4
module coreahblite_lib coreahblite_addrdec 4
arch coreahblite_lib coreahblite_defaultslavesm coreahblite_defaultslavesm_arch 5
module coreahblite_lib coreahblite_defaultslavesm 5
arch coreahblite_lib coreahblite_masterstage coreahblite_masterstage_arch 6
module coreahblite_lib coreahblite_masterstage 6
arch coreahblite_lib coreahblite_slavearbiter coreahblite_slavearbiter_arch 7
module coreahblite_lib coreahblite_slavearbiter 7
arch coreahblite_lib coreahblite_slavestage trans 8
module coreahblite_lib coreahblite_slavestage 8
arch coreahblite_lib coreahblite_matrix4x16 coreahblite_matrix4x16_arch 9
module coreahblite_lib coreahblite_matrix4x16 9
arch coreahblite_lib top_coreahblite_0_coreahblite coreahblite_arch 11
module coreahblite_lib top_coreahblite_0_coreahblite 11
arch coreuartapb_lib top_coreuartapb_0_clock_gen rtl 12
module coreuartapb_lib top_coreuartapb_0_clock_gen 12
arch coreuartapb_lib top_coreuartapb_0_rx_async translated 13
module coreuartapb_lib top_coreuartapb_0_rx_async 13
arch coreuartapb_lib top_coreuartapb_0_tx_async translated 14
module coreuartapb_lib top_coreuartapb_0_tx_async 14
arch coreuartapb_lib top_coreuartapb_0_fifo_256x8_pa3 translated 15
module coreuartapb_lib top_coreuartapb_0_fifo_256x8_pa3 15
arch coreuartapb_lib top_coreuartapb_0_fifo_256x8 translated 15
module coreuartapb_lib top_coreuartapb_0_fifo_256x8 15
arch coreuartapb_lib top_coreuartapb_0_coreuart translated 17
module coreuartapb_lib top_coreuartapb_0_coreuart 17
arch coreuartapb_lib top_coreuartapb_0_coreuartapb translated 18
module coreuartapb_lib top_coreuartapb_0_coreuartapb 18
arch work top rtl 21
module work top 21