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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [boards/] [Altera/] [DE5/] [DE5.v] - Rev 48
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//======================================================= // This code is generated by Terasic System Builder //======================================================= module Top( //////////// CLOCK ////////// OSC_50_B3B, OSC_50_B3D, OSC_50_B4A, OSC_50_B4D, OSC_50_B7A, OSC_50_B7D, OSC_50_B8A, OSC_50_B8D, //////////// LED x 10 ////////// LED, LED_BRACKET, LED_RJ45_L, LED_RJ45_R, //////////// BUTTON x 4 and CPU_RESET_n ////////// BUTTON, CPU_RESET_n, //////////// SWITCH x 4 ////////// SW, //////////// 7-Segement ////////// HEX0_D, HEX0_DP, HEX1_D, HEX1_DP, //////////// Temperature ////////// TEMP_CLK, TEMP_DATA, TEMP_INT_n, TEMP_OVERT_n, //////////// Fan ////////// FAN_CTRL, //////////// RS232 ////////// RS422_DE, RS422_DIN, RS422_DOUT, RS422_RE_n, RS422_TE, //////////// Flash/MAX Address/Data Share Bus ////////// FSM_A, FSM_D, //////////// Flash Control ////////// FLASH_ADV_n, FLASH_CE_n, FLASH_CLK, FLASH_OE_n, FLASH_RDY_BSY_n, FLASH_RESET_n, FLASH_WE_n ); //======================================================= // PARAMETER declarations //======================================================= //======================================================= // PORT declarations //======================================================= //////////// CLOCK ////////// input OSC_50_B3B; input OSC_50_B3D; input OSC_50_B4A; input OSC_50_B4D; input OSC_50_B7A; input OSC_50_B7D; input OSC_50_B8A; input OSC_50_B8D; //////////// LED x 10 ////////// output [3:0] LED; output [3:0] LED_BRACKET; output LED_RJ45_L; output LED_RJ45_R; //////////// BUTTON x 4 and CPU_RESET_n ////////// input [3:0] BUTTON; input CPU_RESET_n; //////////// SWITCH x 4 ////////// input [3:0] SW; //////////// 7-Segement ////////// output [6:0] HEX0_D; output HEX0_DP; output [6:0] HEX1_D; output HEX1_DP; //////////// Temperature ////////// output TEMP_CLK; inout TEMP_DATA; input TEMP_INT_n; input TEMP_OVERT_n; //////////// Fan ////////// inout FAN_CTRL; //////////// RS232 ////////// output RS422_DE; input RS422_DIN; output RS422_DOUT; output RS422_RE_n; output RS422_TE; //////////// Flash/MAX Address/Data Share Bus ////////// output [26:0] FSM_A; inout [31:0] FSM_D; //////////// Flash Control ////////// output FLASH_ADV_n; output [1:0] FLASH_CE_n; output FLASH_CLK; output FLASH_OE_n; input [1:0] FLASH_RDY_BSY_n; output FLASH_RESET_n; output FLASH_WE_n; //======================================================= // REG/WIRE declarations //======================================================= //======================================================= // Structural coding //======================================================= endmodule