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<h1>ocs_control.v</h1> </div>
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<a href="ocs__control_8v.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="keyword">/*</span>
<a name="l00002"></a>00002 <span class="keyword"> Copyright 2010, Aleksander Osman, alfik@poczta.fm. All rights reserved.</span>
<a name="l00003"></a>00003 <span class="keyword"> </span>
<a name="l00004"></a>00004 <span class="keyword"> Redistribution and use in source and binary forms, with or without modification, are</span>
<a name="l00005"></a>00005 <span class="keyword"> permitted provided that the following conditions are met:</span>
<a name="l00006"></a>00006 <span class="keyword"> </span>
<a name="l00007"></a>00007 <span class="keyword"> 1. Redistributions of source code must retain the above copyright notice, this list of</span>
<a name="l00008"></a>00008 <span class="keyword"> conditions and the following disclaimer.</span>
<a name="l00009"></a>00009 <span class="keyword"> </span>
<a name="l00010"></a>00010 <span class="keyword"> 2. Redistributions in binary form must reproduce the above copyright notice, this list</span>
<a name="l00011"></a>00011 <span class="keyword"> of conditions and the following disclaimer in the documentation and/or other materials</span>
<a name="l00012"></a>00012 <span class="keyword"> provided with the distribution.</span>
<a name="l00013"></a>00013 <span class="keyword"> </span>
<a name="l00014"></a>00014 <span class="keyword"> THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED</span>
<a name="l00015"></a>00015 <span class="keyword"> WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND</span>
<a name="l00016"></a>00016 <span class="keyword"> FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR</span>
<a name="l00017"></a>00017 <span class="keyword"> CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR</span>
<a name="l00018"></a>00018 <span class="keyword"> CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</span>
<a name="l00019"></a>00019 <span class="keyword"> SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON</span>
<a name="l00020"></a>00020 <span class="keyword"> ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING</span>
<a name="l00021"></a>00021 <span class="keyword"> NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF</span>
<a name="l00022"></a>00022 <span class="keyword"> ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span>
<a name="l00023"></a>00023 <span class="keyword"> */</span>
<a name="l00024"></a>00024
<a name="l00025"></a>00025 <span class="keyword">/*! \file</span>
<a name="l00026"></a>00026 <span class="keyword"> \brief OCS system control implementation with WISHBONE slave interface.</span>
<a name="l00027"></a>00027 <span class="keyword"> */</span>
<a name="l00028"></a>00028
<a name="l00029"></a>00029 <span class="keyword">/*! \brief \copybrief ocs_control.v</span>
<a name="l00030"></a>00030 <span class="keyword"></span>
<a name="l00031"></a>00031 <span class="keyword">List of system control registers:</span>
<a name="l00032"></a>00032 <span class="keyword">\verbatim</span>
<a name="l00033"></a>00033 <span class="keyword">Implemented:</span>
<a name="l00034"></a>00034 <span class="keyword"> [DDFSTOP 094 W A Display bitplane data fetch stop </span>
<a name="l00035"></a>00035 <span class="keyword"> (horiz. position) write not implemented here]</span>
<a name="l00036"></a>00036 <span class="keyword"> DMACON 096 W ADP DMA control write (clear or set) write not implemented here</span>
<a name="l00037"></a>00037 <span class="keyword"> </span>
<a name="l00038"></a>00038 <span class="keyword"> DMACONR *002 R AP DMA control (and blitter status) read</span>
<a name="l00039"></a>00039 <span class="keyword"> VPOSR *004 R A( E ) Read vert most signif. bit (and frame flop)</span>
<a name="l00040"></a>00040 <span class="keyword"> VHPOSR *006 R A Read vert and horiz. position of beam</span>
<a name="l00041"></a>00041 <span class="keyword"> </span>
<a name="l00042"></a>00042 <span class="keyword"> ADKCON 09E W P Audio, disk, UART control</span>
<a name="l00043"></a>00043 <span class="keyword"> </span>
<a name="l00044"></a>00044 <span class="keyword"> ADKCONR *010 R P Audio, disk control register read</span>
<a name="l00045"></a>00045 <span class="keyword"> [POT0DAT *012 R P( E ) Pot counter pair 0 data (vert,horiz) read implemented here]</span>
<a name="l00046"></a>00046 <span class="keyword"> </span>
<a name="l00047"></a>00047 <span class="keyword"> INTENAR *01C R P Interrupt enable bits read</span>
<a name="l00048"></a>00048 <span class="keyword"> INTREQR *01E R P Interrupt request bits read</span>
<a name="l00049"></a>00049 <span class="keyword"> </span>
<a name="l00050"></a>00050 <span class="keyword"> [CLXCON 098 W D Collision control write not implemented here]</span>
<a name="l00051"></a>00051 <span class="keyword"> INTENA 09A W P Interrupt enable bits (clear or set bits) write not implemented here</span>
<a name="l00052"></a>00052 <span class="keyword"> INTREQ 09C W P Interrupt request bits (clear or set bits)</span>
<a name="l00053"></a>00053 <span class="keyword"> </span>
<a name="l00054"></a>00054 <span class="keyword">Not implemented:</span>
<a name="l00055"></a>00055 <span class="keyword"> REFPTR & *028 W A Refresh pointer </span>
<a name="l00056"></a>00056 <span class="keyword"> VPOSW *02A W A Write vert most signif. bit (and frame flop) </span>
<a name="l00057"></a>00057 <span class="keyword"> VHPOSW *02C W A Write vert and horiz position of beam</span>
<a name="l00058"></a>00058 <span class="keyword"> </span>
<a name="l00059"></a>00059 <span class="keyword"> STREQU & *038 S D Strobe for horiz sync with VB and EQU</span>
<a name="l00060"></a>00060 <span class="keyword"> STRVBL & *03A S D Strobe for horiz sync with VB (vert. blank)</span>
<a name="l00061"></a>00061 <span class="keyword"> STRHOR & *03C S DP Strobe for horiz sync</span>
<a name="l00062"></a>00062 <span class="keyword"> STRLONG & *03E S D( E ) Strobe for identification of long horiz. line.</span>
<a name="l00063"></a>00063 <span class="keyword"> </span>
<a name="l00064"></a>00064 <span class="keyword"> RESERVED 1110X</span>
<a name="l00065"></a>00065 <span class="keyword"> RESERVED 1111X</span>
<a name="l00066"></a>00066 <span class="keyword"> NO-OP(NULL) 1FE</span>
<a name="l00067"></a>00067 <span class="keyword">\endverbatim</span>
<a name="l00068"></a>00068 <span class="keyword">*/</span>
<a name="l00069"></a><a class="code" href="classocs__control.html">00069</a> <span class="vhdlkeyword">module</span> <a class="code" href="classocs__control.html">ocs_control</a>(
<a name="l00070"></a>00070 <span class="keyword">//% \name Clock and reset
</span>
<a name="l00071"></a>00071 <span class="keyword">//% @{</span>
<a name="l00072"></a><a class="code" href="classocs__control.html#a78eebaf1d7122debfc56eebb02678f7c">00072</a> <span class="vhdlkeyword">input</span> <a class="code" href="classocs__control.html#a78eebaf1d7122debfc56eebb02678f7c">clk_30</a>,
<a name="l00073"></a><a class="code" href="classocs__control.html#a246ab8bc07755c51fdd905891ec461e7">00073</a> <span class="vhdlkeyword">input</span> <a class="code" href="classocs__control.html#a246ab8bc07755c51fdd905891ec461e7">reset_n</a>,
<a name="l00074"></a>00074 <span class="keyword">//% @}</span>
<a name="l00075"></a>00075
<a name="l00076"></a>00076 <span class="keyword">//% \name WISHBONE slave
</span>
<a name="l00077"></a>00077 <span class="keyword">//% @{</span>
<a name="l00078"></a><a class="code" href="classocs__control.html#a2b96a7c9eef58084d7c25b4cda2c4ed8">00078</a> <span class="vhdlkeyword">input</span> <a class="code" href="classocs__control.html#a2b96a7c9eef58084d7c25b4cda2c4ed8">CYC_I</a>,
<a name="l00079"></a><a class="code" href="classocs__control.html#a26071b95b282cb6ff3aac96128f0737a">00079</a> <span class="vhdlkeyword">input</span> <a class="code" href="classocs__control.html#a26071b95b282cb6ff3aac96128f0737a">STB_I</a>,
<a name="l00080"></a><a class="code" href="classocs__control.html#ac7648944e0726e364b9509f1a0b81c12">00080</a> <span class="vhdlkeyword">input</span> <a class="code" href="classocs__control.html#ac7648944e0726e364b9509f1a0b81c12">WE_I</a>,
<a name="l00081"></a><a class="code" href="classocs__control.html#a5287d0f0371bd2793e15feb3e1871bbd">00081</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">2</span>] <a class="code" href="classocs__control.html#a5287d0f0371bd2793e15feb3e1871bbd">ADR_I</a>,
<a name="l00082"></a><a class="code" href="classocs__control.html#a6eb7afa02ef30b83f4553c2710cb219d">00082</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] <a class="code" href="classocs__control.html#a6eb7afa02ef30b83f4553c2710cb219d">SEL_I</a>,
<a name="l00083"></a><a class="code" href="classocs__control.html#a8a577d05f486a2b93a18f90ae5a08646">00083</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classocs__control.html#a8a577d05f486a2b93a18f90ae5a08646">slave_DAT_I</a>,
<a name="l00084"></a><a class="code" href="classocs__control.html#a4c36d95eefa6d567b8b4e8d476cd3a96">00084</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classocs__control.html#a4c36d95eefa6d567b8b4e8d476cd3a96">slave_DAT_O</a>,
<a name="l00085"></a><a class="code" href="classocs__control.html#a8f9ec718b2729125a55d8befe1f27435">00085</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> <a class="code" href="classocs__control.html#a8f9ec718b2729125a55d8befe1f27435">ACK_O</a>,
<a name="l00086"></a>00086 <span class="keyword">//% @}</span>
<a name="l00087"></a>00087
<a name="l00088"></a>00088 <span class="keyword">//% \name Not aligned register access on a 32-bit WISHBONE bus
</span>
<a name="l00089"></a>00089 <span class="keyword">//% @{</span>
<a name="l00090"></a>00090 <span class="keyword">// INTENA write not implemented here</span>
<a name="l00091"></a><a class="code" href="classocs__control.html#a0dcd453ed628f5b00f790f2ab89803db">00091</a> <span class="vhdlkeyword">input</span> <a class="code" href="classocs__control.html#a0dcd453ed628f5b00f790f2ab89803db">na_int_ena_write</a>,
<a name="l00092"></a><a class="code" href="classocs__control.html#aa45b061fb9026b2d2ea62770ba1516af">00092</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classocs__control.html#aa45b061fb9026b2d2ea62770ba1516af">na_int_ena</a>,
<a name="l00093"></a><a class="code" href="classocs__control.html#ab60aa15fd32a27bc713a6e03259b8b9c">00093</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] <a class="code" href="classocs__control.html#ab60aa15fd32a27bc713a6e03259b8b9c">na_int_ena_sel</a>,
<a name="l00094"></a>00094 <span class="keyword">// DMACON write not implemented here</span>
<a name="l00095"></a><a class="code" href="classocs__control.html#a8672e719439586f796599c61a9edf765">00095</a> <span class="vhdlkeyword">input</span> <a class="code" href="classocs__control.html#a8672e719439586f796599c61a9edf765">na_dma_con_write</a>,
<a name="l00096"></a><a class="code" href="classocs__control.html#a253a44d8f5bba8b2a5a1988e73059626">00096</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classocs__control.html#a253a44d8f5bba8b2a5a1988e73059626">na_dma_con</a>,
<a name="l00097"></a><a class="code" href="classocs__control.html#abf6f4b5c6a572ec5a8a35f4d20485566">00097</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] <a class="code" href="classocs__control.html#abf6f4b5c6a572ec5a8a35f4d20485566">na_dma_con_sel</a>,
<a name="l00098"></a>00098 <span class="keyword">// POT0DAT read implemented here</span>
<a name="l00099"></a><a class="code" href="classocs__control.html#a0e6ee6c6aa45013963dd74c65dc37bc6">00099</a> <span class="vhdlkeyword">output</span> <a class="code" href="classocs__control.html#a0e6ee6c6aa45013963dd74c65dc37bc6">na_pot0dat_read</a>,
<a name="l00100"></a><a class="code" href="classocs__control.html#aa0f199c211813332f0988a4b8a6a3a02">00100</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classocs__control.html#aa0f199c211813332f0988a4b8a6a3a02">na_pot0dat</a>,
<a name="l00101"></a>00101 <span class="keyword">//% @}</span>
<a name="l00102"></a>00102
<a name="l00103"></a>00103 <span class="keyword">//% \name Internal OCS ports: beam counters
</span>
<a name="l00104"></a>00104 <span class="keyword">//% @{</span>
<a name="l00105"></a><a class="code" href="classocs__control.html#af98b6d9d326d8dd116b3b7969a720247">00105</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> <a class="code" href="classocs__control.html#af98b6d9d326d8dd116b3b7969a720247">line_start</a>,
<a name="l00106"></a><a class="code" href="classocs__control.html#ada98b4d5917ec047013fdc76570c6a8e">00106</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> <a class="code" href="classocs__control.html#ada98b4d5917ec047013fdc76570c6a8e">line_pre_start</a>,
<a name="l00107"></a><a class="code" href="classocs__control.html#a4550e00911796d007466de7625bd0b2a">00107</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classocs__control.html#a4550e00911796d007466de7625bd0b2a">line_number</a>,
<a name="l00108"></a><a class="code" href="classocs__control.html#a91b282041c78283ad2fd1a333cf3fdc4">00108</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classocs__control.html#a91b282041c78283ad2fd1a333cf3fdc4">column_number</a>,
<a name="l00109"></a>00109 <span class="keyword">//% @}</span>
<a name="l00110"></a>00110
<a name="l00111"></a>00111 <span class="keyword">//% \name Internal OCS ports: clock pulses for CIA and audio
</span>
<a name="l00112"></a>00112 <span class="keyword">//% @{</span>
<a name="l00113"></a><a class="code" href="classocs__control.html#a0197eedf5b87ff26b0b2035e18b8c1c1">00113</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> <a class="code" href="classocs__control.html#a0197eedf5b87ff26b0b2035e18b8c1c1">pulse_709379_hz</a>,
<a name="l00114"></a><a class="code" href="classocs__control.html#ac0fa0cd71802281503990be9fd87f900">00114</a> <span class="vhdlkeyword">output</span> <a class="code" href="classocs__control.html#ac0fa0cd71802281503990be9fd87f900">pulse_color</a>,
<a name="l00115"></a>00115 <span class="keyword">//% @}</span>
<a name="l00116"></a>00116
<a name="l00117"></a>00117 <span class="keyword">//% \name Internal OCS ports: global registers and blitter signals
</span>
<a name="l00118"></a>00118 <span class="keyword">//% @{</span>
<a name="l00119"></a><a class="code" href="classocs__control.html#a2ef3aff81fd20f8ae91d3e66c046fffe">00119</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">10</span>:<span class="vhdllogic">0</span>] <a class="code" href="classocs__control.html#a2ef3aff81fd20f8ae91d3e66c046fffe">dma_con</a>,
<a name="l00120"></a><a class="code" href="classocs__control.html#ad1c254c7e4551d7f373b552e40652f5f">00120</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">14</span>:<span class="vhdllogic">0</span>] <a class="code" href="classocs__control.html#ad1c254c7e4551d7f373b552e40652f5f">adk_con</a>,
<a name="l00121"></a>00121
<a name="l00122"></a><a class="code" href="classocs__control.html#a02b5f619bee718ffca6c320ab96bda12">00122</a> <span class="vhdlkeyword">input</span> <a class="code" href="classocs__control.html#a02b5f619bee718ffca6c320ab96bda12">blitter_busy</a>,
<a name="l00123"></a><a class="code" href="classocs__control.html#aa7ea7fc799ab33140366bd1015496a8d">00123</a> <span class="vhdlkeyword">input</span> <a class="code" href="classocs__control.html#aa7ea7fc799ab33140366bd1015496a8d">blitter_zero</a>,
<a name="l00124"></a>00124 <span class="keyword">//% @}</span>
<a name="l00125"></a>00125
<a name="l00126"></a>00126 <span class="keyword">//% \name Internal OCS ports: interrupts
</span>
<a name="l00127"></a>00127 <span class="keyword">//% @{</span>
<a name="l00128"></a><a class="code" href="classocs__control.html#ae645835ecd291e80d3f61ec700e0ef83">00128</a> <span class="vhdlkeyword">input</span> <a class="code" href="classocs__control.html#ae645835ecd291e80d3f61ec700e0ef83">blitter_irq</a>,
<a name="l00129"></a><a class="code" href="classocs__control.html#a0c63e4bdbce5abb540b08a7e92f212a6">00129</a> <span class="vhdlkeyword">input</span> <a class="code" href="classocs__control.html#a0c63e4bdbce5abb540b08a7e92f212a6">cia_a_irq</a>,
<a name="l00130"></a><a class="code" href="classocs__control.html#afe3687249cafab6be582a087418a3398">00130</a> <span class="vhdlkeyword">input</span> <a class="code" href="classocs__control.html#afe3687249cafab6be582a087418a3398">cia_b_irq</a>,
<a name="l00131"></a><a class="code" href="classocs__control.html#a16bb90760ecef8bb189641ef3966630d">00131</a> <span class="vhdlkeyword">input</span> <a class="code" href="classocs__control.html#a16bb90760ecef8bb189641ef3966630d">floppy_syn_irq</a>,
<a name="l00132"></a><a class="code" href="classocs__control.html#a09d4c03109cf00edd231085ce18ab92c">00132</a> <span class="vhdlkeyword">input</span> <a class="code" href="classocs__control.html#a09d4c03109cf00edd231085ce18ab92c">floppy_blk_irq</a>,
<a name="l00133"></a><a class="code" href="classocs__control.html#a5ec8650f5638dbfa0f0672a36fad69db">00133</a> <span class="vhdlkeyword">input</span> <a class="code" href="classocs__control.html#a5ec8650f5638dbfa0f0672a36fad69db">serial_rbf_irq</a>,
<a name="l00134"></a><a class="code" href="classocs__control.html#a6ed777016a820616ed38f063c8578317">00134</a> <span class="vhdlkeyword">input</span> <a class="code" href="classocs__control.html#a6ed777016a820616ed38f063c8578317">serial_tbe_irq</a>,
<a name="l00135"></a><a class="code" href="classocs__control.html#aec4f636beb542cf2eba96883a664a736">00135</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] <a class="code" href="classocs__control.html#aec4f636beb542cf2eba96883a664a736">audio_irq</a>,
<a name="l00136"></a>00136
<a name="l00137"></a><a class="code" href="classocs__control.html#aa8d13b23544f041f1f633c8237e0ad03">00137</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classocs__control.html#aa8d13b23544f041f1f633c8237e0ad03">interrupt</a>
<a name="l00138"></a>00138 <span class="keyword">//% @}</span>
<a name="l00139"></a>00139 );
<a name="l00140"></a>00140
<a name="l00141"></a>00141 <span class="vhdlkeyword">assign</span> <a class="code" href="classocs__control.html#aa8d13b23544f041f1f633c8237e0ad03">interrupt</a> =
<a name="l00142"></a>00142 (<a class="code" href="classocs__control.html#a3525e0a8a3eada445af773a732dd0469">int_ena</a>[<span class="vhdllogic">14</span>] == <span class="vhdllogic">1'b0</span>)? <span class="vhdllogic">3'd0</span> :
<a name="l00143"></a>00143 (<a class="code" href="classocs__control.html#a3525e0a8a3eada445af773a732dd0469">int_ena</a>[<span class="vhdllogic">13</span>] == <span class="vhdllogic">1'b1</span> && <a class="code" href="classocs__control.html#a37d5b61b43de582a29e66d99937762db">int_req</a>[<span class="vhdllogic">13</span>] == <span class="vhdllogic">1'b1</span>) ? <span class="vhdllogic">3'd6</span> :
<a name="l00144"></a>00144 (<a class="code" href="classocs__control.html#a3525e0a8a3eada445af773a732dd0469">int_ena</a>[<span class="vhdllogic">12</span>] == <span class="vhdllogic">1'b1</span> && <a class="code" href="classocs__control.html#a37d5b61b43de582a29e66d99937762db">int_req</a>[<span class="vhdllogic">12</span>] == <span class="vhdllogic">1'b1</span>) ? <span class="vhdllogic">3'd5</span> :
<a name="l00145"></a>00145 (<a class="code" href="classocs__control.html#a3525e0a8a3eada445af773a732dd0469">int_ena</a>[<span class="vhdllogic">11</span>] == <span class="vhdllogic">1'b1</span> && <a class="code" href="classocs__control.html#a37d5b61b43de582a29e66d99937762db">int_req</a>[<span class="vhdllogic">11</span>] == <span class="vhdllogic">1'b1</span>) ? <span class="vhdllogic">3'd5</span> :
<a name="l00146"></a>00146 (<a class="code" href="classocs__control.html#a3525e0a8a3eada445af773a732dd0469">int_ena</a>[<span class="vhdllogic">10</span>] == <span class="vhdllogic">1'b1</span> && <a class="code" href="classocs__control.html#a37d5b61b43de582a29e66d99937762db">int_req</a>[<span class="vhdllogic">10</span>] == <span class="vhdllogic">1'b1</span>) ? <span class="vhdllogic">3'd4</span> :
<a name="l00147"></a>00147 (<a class="code" href="classocs__control.html#a3525e0a8a3eada445af773a732dd0469">int_ena</a>[<span class="vhdllogic">9</span>] == <span class="vhdllogic">1'b1</span> && <a class="code" href="classocs__control.html#a37d5b61b43de582a29e66d99937762db">int_req</a>[<span class="vhdllogic">9</span>] == <span class="vhdllogic">1'b1</span>) ? <span class="vhdllogic">3'd4</span> :
<a name="l00148"></a>00148 (<a class="code" href="classocs__control.html#a3525e0a8a3eada445af773a732dd0469">int_ena</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span> && <a class="code" href="classocs__control.html#a37d5b61b43de582a29e66d99937762db">int_req</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>) ? <span class="vhdllogic">3'd4</span> :
<a name="l00149"></a>00149 (<a class="code" href="classocs__control.html#a3525e0a8a3eada445af773a732dd0469">int_ena</a>[<span class="vhdllogic">7</span>] == <span class="vhdllogic">1'b1</span> && <a class="code" href="classocs__control.html#a37d5b61b43de582a29e66d99937762db">int_req</a>[<span class="vhdllogic">7</span>] == <span class="vhdllogic">1'b1</span>) ? <span class="vhdllogic">3'd4</span> :
<a name="l00150"></a>00150 (<a class="code" href="classocs__control.html#a3525e0a8a3eada445af773a732dd0469">int_ena</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span> && <a class="code" href="classocs__control.html#a37d5b61b43de582a29e66d99937762db">int_req</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>) ? <span class="vhdllogic">3'd3</span> :
<a name="l00151"></a>00151 (<a class="code" href="classocs__control.html#a3525e0a8a3eada445af773a732dd0469">int_ena</a>[<span class="vhdllogic">5</span>] == <span class="vhdllogic">1'b1</span> && <a class="code" href="classocs__control.html#a37d5b61b43de582a29e66d99937762db">int_req</a>[<span class="vhdllogic">5</span>] == <span class="vhdllogic">1'b1</span>) ? <span class="vhdllogic">3'd3</span> :
<a name="l00152"></a>00152 (<a class="code" href="classocs__control.html#a3525e0a8a3eada445af773a732dd0469">int_ena</a>[<span class="vhdllogic">4</span>] == <span class="vhdllogic">1'b1</span> && <a class="code" href="classocs__control.html#a37d5b61b43de582a29e66d99937762db">int_req</a>[<span class="vhdllogic">4</span>] == <span class="vhdllogic">1'b1</span>) ? <span class="vhdllogic">3'd3</span> :
<a name="l00153"></a>00153 (<a class="code" href="classocs__control.html#a3525e0a8a3eada445af773a732dd0469">int_ena</a>[<span class="vhdllogic">3</span>] == <span class="vhdllogic">1'b1</span> && <a class="code" href="classocs__control.html#a37d5b61b43de582a29e66d99937762db">int_req</a>[<span class="vhdllogic">3</span>] == <span class="vhdllogic">1'b1</span>) ? <span class="vhdllogic">3'd2</span> :
<a name="l00154"></a>00154 (<a class="code" href="classocs__control.html#a3525e0a8a3eada445af773a732dd0469">int_ena</a>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span> && <a class="code" href="classocs__control.html#a37d5b61b43de582a29e66d99937762db">int_req</a>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) ? <span class="vhdllogic">3'd1</span> :
<a name="l00155"></a>00155 (<a class="code" href="classocs__control.html#a3525e0a8a3eada445af773a732dd0469">int_ena</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span> && <a class="code" href="classocs__control.html#a37d5b61b43de582a29e66d99937762db">int_req</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) ? <span class="vhdllogic">3'd1</span> :
<a name="l00156"></a>00156 (<a class="code" href="classocs__control.html#a3525e0a8a3eada445af773a732dd0469">int_ena</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span> && <a class="code" href="classocs__control.html#a37d5b61b43de582a29e66d99937762db">int_req</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) ? <span class="vhdllogic">3'd1</span> :
<a name="l00157"></a>00157 <span class="vhdllogic">3'd0</span>;
<a name="l00158"></a>00158
<a name="l00159"></a><a class="code" href="classocs__control.html#a50bcd8b53c850440d22c18a40f5a3255">00159</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">14</span>:<span class="vhdllogic">0</span>] <a class="code" href="classocs__control.html#a50bcd8b53c850440d22c18a40f5a3255">new_int_req</a>;
<a name="l00160"></a>00160 <span class="vhdlkeyword">assign</span> <a class="code" href="classocs__control.html#a50bcd8b53c850440d22c18a40f5a3255">new_int_req</a> = {
<a name="l00161"></a>00161 <span class="vhdllogic">1'b0</span>,
<a name="l00162"></a>00162 <a class="code" href="classocs__control.html#afe3687249cafab6be582a087418a3398">cia_b_irq</a>,
<a name="l00163"></a>00163 <a class="code" href="classocs__control.html#a16bb90760ecef8bb189641ef3966630d">floppy_syn_irq</a>,
<a name="l00164"></a>00164 <a class="code" href="classocs__control.html#a5ec8650f5638dbfa0f0672a36fad69db">serial_rbf_irq</a>,
<a name="l00165"></a>00165 <a class="code" href="classocs__control.html#aec4f636beb542cf2eba96883a664a736">audio_irq</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>],
<a name="l00166"></a>00166 <a class="code" href="classocs__control.html#ae645835ecd291e80d3f61ec700e0ef83">blitter_irq</a>,
<a name="l00167"></a>00167 (<a class="code" href="classocs__control.html#af98b6d9d326d8dd116b3b7969a720247">line_start</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classocs__control.html#a4550e00911796d007466de7625bd0b2a">line_number</a> == <span class="vhdllogic">9'd0</span>),
<a name="l00168"></a>00168 <span class="vhdllogic">1'b0</span>,
<a name="l00169"></a>00169 <a class="code" href="classocs__control.html#a0c63e4bdbce5abb540b08a7e92f212a6">cia_a_irq</a>,
<a name="l00170"></a>00170 <span class="vhdllogic">1'b0</span>,
<a name="l00171"></a>00171 <a class="code" href="classocs__control.html#a09d4c03109cf00edd231085ce18ab92c">floppy_blk_irq</a>,
<a name="l00172"></a>00172 <a class="code" href="classocs__control.html#a6ed777016a820616ed38f063c8578317">serial_tbe_irq</a>
<a name="l00173"></a>00173 };
<a name="l00174"></a>00174
<a name="l00175"></a><a class="code" href="classocs__control.html#a3525e0a8a3eada445af773a732dd0469">00175</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">14</span>:<span class="vhdllogic">0</span>] <a class="code" href="classocs__control.html#a3525e0a8a3eada445af773a732dd0469">int_ena</a>;
<a name="l00176"></a><a class="code" href="classocs__control.html#a37d5b61b43de582a29e66d99937762db">00176</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">14</span>:<span class="vhdllogic">0</span>] <a class="code" href="classocs__control.html#a37d5b61b43de582a29e66d99937762db">int_req</a>;
<a name="l00177"></a><a class="code" href="classocs__control.html#a30b9ec3d0a2504a8d4ce0c4f38bbe122">00177</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">10</span>:<span class="vhdllogic">0</span>] <a class="code" href="classocs__control.html#a30b9ec3d0a2504a8d4ce0c4f38bbe122">column_counter</a>;
<a name="l00178"></a><a class="code" href="classocs__control.html#a60428caa020a8abe12a58b707c2f4dcc">00178</a> <span class="vhdlkeyword">reg</span> <a class="code" href="classocs__control.html#a60428caa020a8abe12a58b707c2f4dcc">long_frame</a>;
<a name="l00179"></a>00179
<a name="l00180"></a>00180 <span class="vhdlkeyword">assign</span> <a class="code" href="classocs__control.html#a0e6ee6c6aa45013963dd74c65dc37bc6">na_pot0dat_read</a> = (<a class="code" href="classocs__control.html#a2b96a7c9eef58084d7c25b4cda2c4ed8">CYC_I</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classocs__control.html#a26071b95b282cb6ff3aac96128f0737a">STB_I</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classocs__control.html#a8f9ec718b2729125a55d8befe1f27435">ACK_O</a> == <span class="vhdllogic">1'b0</span> && <a class="code" href="classocs__control.html#ac7648944e0726e364b9509f1a0b81c12">WE_I</a> == <span class="vhdllogic">1'b0</span> && { <a class="code" href="classocs__control.html#a5287d0f0371bd2793e15feb3e1871bbd">ADR_I</a>, <span class="vhdllogic">2'b0</span> } == <span class="vhdllogic">9'h010</span> && <a class="code" href="classocs__control.html#a6eb7afa02ef30b83f4553c2710cb219d">SEL_I</a>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] != <span class="vhdllogic">2'b00</span>);
<a name="l00181"></a>00181
<a name="l00182"></a><a class="code" href="classocs__control.html#a941900ef0da9240ac0c4925bcc5c72b0">00182</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classocs__control.html#a78eebaf1d7122debfc56eebb02678f7c">clk_30</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classocs__control.html#a246ab8bc07755c51fdd905891ec461e7">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l00183"></a>00183 <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#a246ab8bc07755c51fdd905891ec461e7">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
<a name="l00184"></a>00184 <a class="code" href="classocs__control.html#a4c36d95eefa6d567b8b4e8d476cd3a96">slave_DAT_O</a> <= <span class="vhdllogic">32'd0</span>;
<a name="l00185"></a>00185 <a class="code" href="classocs__control.html#a8f9ec718b2729125a55d8befe1f27435">ACK_O</a> <= <span class="vhdllogic">1'b0</span>;
<a name="l00186"></a>00186
<a name="l00187"></a>00187 <a class="code" href="classocs__control.html#af98b6d9d326d8dd116b3b7969a720247">line_start</a> <= <span class="vhdllogic">1'b0</span>;
<a name="l00188"></a>00188 <a class="code" href="classocs__control.html#ada98b4d5917ec047013fdc76570c6a8e">line_pre_start</a> <= <span class="vhdllogic">1'b0</span>;
<a name="l00189"></a>00189 <a class="code" href="classocs__control.html#a4550e00911796d007466de7625bd0b2a">line_number</a> <= <span class="vhdllogic">9'd0</span>;
<a name="l00190"></a>00190 <a class="code" href="classocs__control.html#a91b282041c78283ad2fd1a333cf3fdc4">column_number</a> <= <span class="vhdllogic">9'd0</span>;
<a name="l00191"></a>00191
<a name="l00192"></a>00192 <a class="code" href="classocs__control.html#a2ef3aff81fd20f8ae91d3e66c046fffe">dma_con</a> <= <span class="vhdllogic">11'd0</span>;
<a name="l00193"></a>00193 <a class="code" href="classocs__control.html#a37d5b61b43de582a29e66d99937762db">int_req</a> <= <span class="vhdllogic">15'd0</span>;
<a name="l00194"></a>00194 <a class="code" href="classocs__control.html#a3525e0a8a3eada445af773a732dd0469">int_ena</a> <= <span class="vhdllogic">15'd0</span>;
<a name="l00195"></a>00195 <a class="code" href="classocs__control.html#ad1c254c7e4551d7f373b552e40652f5f">adk_con</a> <= <span class="vhdllogic">15'd0</span>;
<a name="l00196"></a>00196 <a class="code" href="classocs__control.html#a30b9ec3d0a2504a8d4ce0c4f38bbe122">column_counter</a> <= <span class="vhdllogic">11'd0</span>;
<a name="l00197"></a>00197 <a class="code" href="classocs__control.html#a60428caa020a8abe12a58b707c2f4dcc">long_frame</a> <= <span class="vhdllogic">1'b0</span>;
<a name="l00198"></a>00198 <span class="vhdlkeyword">end</span>
<a name="l00199"></a>00199 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
<a name="l00200"></a>00200 <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#a8672e719439586f796599c61a9edf765">na_dma_con_write</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classocs__control.html#abf6f4b5c6a572ec5a8a35f4d20485566">na_dma_con_sel</a>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b11</span>) <span class="vhdlkeyword">begin</span>
<a name="l00201"></a>00201 <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#a253a44d8f5bba8b2a5a1988e73059626">na_dma_con</a>[<span class="vhdllogic">15</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classocs__control.html#a2ef3aff81fd20f8ae91d3e66c046fffe">dma_con</a> <= <a class="code" href="classocs__control.html#a2ef3aff81fd20f8ae91d3e66c046fffe">dma_con</a> | <a class="code" href="classocs__control.html#a253a44d8f5bba8b2a5a1988e73059626">na_dma_con</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">0</span>];
<a name="l00202"></a>00202 <span class="vhdlkeyword">else</span> <a class="code" href="classocs__control.html#a2ef3aff81fd20f8ae91d3e66c046fffe">dma_con</a> <= <a class="code" href="classocs__control.html#a2ef3aff81fd20f8ae91d3e66c046fffe">dma_con</a> & (~<a class="code" href="classocs__control.html#a253a44d8f5bba8b2a5a1988e73059626">na_dma_con</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">0</span>]);
<a name="l00203"></a>00203 <span class="vhdlkeyword">end</span>
<a name="l00204"></a>00204
<a name="l00205"></a>00205 <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#a0dcd453ed628f5b00f790f2ab89803db">na_int_ena_write</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classocs__control.html#ab60aa15fd32a27bc713a6e03259b8b9c">na_int_ena_sel</a>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b11</span>) <span class="vhdlkeyword">begin</span>
<a name="l00206"></a>00206 <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#aa45b061fb9026b2d2ea62770ba1516af">na_int_ena</a>[<span class="vhdllogic">15</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classocs__control.html#a3525e0a8a3eada445af773a732dd0469">int_ena</a> <= <a class="code" href="classocs__control.html#a3525e0a8a3eada445af773a732dd0469">int_ena</a> | <a class="code" href="classocs__control.html#aa45b061fb9026b2d2ea62770ba1516af">na_int_ena</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">0</span>];
<a name="l00207"></a>00207 <span class="vhdlkeyword">else</span> <a class="code" href="classocs__control.html#a3525e0a8a3eada445af773a732dd0469">int_ena</a> <= <a class="code" href="classocs__control.html#a3525e0a8a3eada445af773a732dd0469">int_ena</a> & (~<a class="code" href="classocs__control.html#aa45b061fb9026b2d2ea62770ba1516af">na_int_ena</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">0</span>]);
<a name="l00208"></a>00208 <span class="vhdlkeyword">end</span>
<a name="l00209"></a>00209
<a name="l00210"></a>00210 <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#a30b9ec3d0a2504a8d4ce0c4f38bbe122">column_counter</a> == <span class="vhdllogic">11'd1919</span>) <a class="code" href="classocs__control.html#a30b9ec3d0a2504a8d4ce0c4f38bbe122">column_counter</a> <= <span class="vhdllogic">11'd0</span>;
<a name="l00211"></a>00211 <span class="vhdlkeyword">else</span> <a class="code" href="classocs__control.html#a30b9ec3d0a2504a8d4ce0c4f38bbe122">column_counter</a> <= <a class="code" href="classocs__control.html#a30b9ec3d0a2504a8d4ce0c4f38bbe122">column_counter</a> + <span class="vhdllogic">11'd1</span>;
<a name="l00212"></a>00212
<a name="l00213"></a>00213 <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#a30b9ec3d0a2504a8d4ce0c4f38bbe122">column_counter</a> == <span class="vhdllogic">11'd1918</span>) <a class="code" href="classocs__control.html#ada98b4d5917ec047013fdc76570c6a8e">line_pre_start</a> <= <span class="vhdllogic">1'b1</span>;
<a name="l00214"></a>00214 <span class="vhdlkeyword">else</span> <a class="code" href="classocs__control.html#ada98b4d5917ec047013fdc76570c6a8e">line_pre_start</a> <= <span class="vhdllogic">1'b0</span>;
<a name="l00215"></a>00215
<a name="l00216"></a>00216 <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#a30b9ec3d0a2504a8d4ce0c4f38bbe122">column_counter</a> == <span class="vhdllogic">11'd1919</span>) <a class="code" href="classocs__control.html#af98b6d9d326d8dd116b3b7969a720247">line_start</a> <= <span class="vhdllogic">1'b1</span>;
<a name="l00217"></a>00217 <span class="vhdlkeyword">else</span> <a class="code" href="classocs__control.html#af98b6d9d326d8dd116b3b7969a720247">line_start</a> <= <span class="vhdllogic">1'b0</span>;
<a name="l00218"></a>00218
<a name="l00219"></a>00219 <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#a30b9ec3d0a2504a8d4ce0c4f38bbe122">column_counter</a> == <span class="vhdllogic">11'd1919</span>) <span class="vhdlkeyword">begin</span>
<a name="l00220"></a>00220 <a class="code" href="classocs__control.html#a91b282041c78283ad2fd1a333cf3fdc4">column_number</a> <= <span class="vhdllogic">9'd0</span>;
<a name="l00221"></a>00221
<a name="l00222"></a>00222 <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#a4550e00911796d007466de7625bd0b2a">line_number</a> == <span class="vhdllogic">9'd311</span> && <a class="code" href="classocs__control.html#a60428caa020a8abe12a58b707c2f4dcc">long_frame</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
<a name="l00223"></a>00223 <a class="code" href="classocs__control.html#a4550e00911796d007466de7625bd0b2a">line_number</a> <= <span class="vhdllogic">9'd0</span>;
<a name="l00224"></a>00224 <a class="code" href="classocs__control.html#a60428caa020a8abe12a58b707c2f4dcc">long_frame</a> <= <span class="vhdllogic">1'b1</span>;
<a name="l00225"></a>00225 <span class="vhdlkeyword">end</span>
<a name="l00226"></a>00226 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#a4550e00911796d007466de7625bd0b2a">line_number</a> == <span class="vhdllogic">9'd312</span> && <a class="code" href="classocs__control.html#a60428caa020a8abe12a58b707c2f4dcc">long_frame</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
<a name="l00227"></a>00227 <a class="code" href="classocs__control.html#a4550e00911796d007466de7625bd0b2a">line_number</a> <= <span class="vhdllogic">9'd0</span>;
<a name="l00228"></a>00228 <a class="code" href="classocs__control.html#a60428caa020a8abe12a58b707c2f4dcc">long_frame</a> <= <span class="vhdllogic">1'b0</span>;
<a name="l00229"></a>00229 <span class="vhdlkeyword">end</span>
<a name="l00230"></a>00230 <span class="vhdlkeyword">else</span> <a class="code" href="classocs__control.html#a4550e00911796d007466de7625bd0b2a">line_number</a> <= <a class="code" href="classocs__control.html#a4550e00911796d007466de7625bd0b2a">line_number</a> + <span class="vhdllogic">9'd1</span>;
<a name="l00231"></a>00231 <span class="vhdlkeyword">end</span>
<a name="l00232"></a>00232 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#a30b9ec3d0a2504a8d4ce0c4f38bbe122">column_counter</a> > <span class="vhdllogic">11'd600</span> <span class="keyword">/*time for 6 bitplain**/</span>) <span class="vhdlkeyword">begin</span>
<a name="l00233"></a>00233 <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#a30b9ec3d0a2504a8d4ce0c4f38bbe122">column_counter</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span> && <a class="code" href="classocs__control.html#a91b282041c78283ad2fd1a333cf3fdc4">column_number</a> < <span class="vhdllogic">9'd452</span> <span class="keyword">/*226*2**/</span>) <a class="code" href="classocs__control.html#a91b282041c78283ad2fd1a333cf3fdc4">column_number</a> <= <a class="code" href="classocs__control.html#a91b282041c78283ad2fd1a333cf3fdc4">column_number</a> + <span class="vhdllogic">9'd1</span>;
<a name="l00234"></a>00234 <span class="vhdlkeyword">end</span>
<a name="l00235"></a>00235
<a name="l00236"></a>00236 <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#a8f9ec718b2729125a55d8befe1f27435">ACK_O</a> == <span class="vhdllogic">1'b1</span>) <a class="code" href="classocs__control.html#a8f9ec718b2729125a55d8befe1f27435">ACK_O</a> <= <span class="vhdllogic">1'b0</span>;
<a name="l00237"></a>00237
<a name="l00238"></a>00238 <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#a2b96a7c9eef58084d7c25b4cda2c4ed8">CYC_I</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classocs__control.html#a26071b95b282cb6ff3aac96128f0737a">STB_I</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classocs__control.html#a8f9ec718b2729125a55d8befe1f27435">ACK_O</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
<a name="l00239"></a>00239 <a class="code" href="classocs__control.html#a8f9ec718b2729125a55d8befe1f27435">ACK_O</a> <= <span class="vhdllogic">1'b1</span>;
<a name="l00240"></a>00240
<a name="l00241"></a>00241 <span class="keyword">// BLTDDAT not used, DMACONR</span>
<a name="l00242"></a>00242 <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#ac7648944e0726e364b9509f1a0b81c12">WE_I</a> == <span class="vhdllogic">1'b0</span> && { <a class="code" href="classocs__control.html#a5287d0f0371bd2793e15feb3e1871bbd">ADR_I</a>, <span class="vhdllogic">2'b0</span> } == <span class="vhdllogic">9'h000</span>) <a class="code" href="classocs__control.html#a4c36d95eefa6d567b8b4e8d476cd3a96">slave_DAT_O</a> <= { <span class="vhdllogic">16'd0</span>, <span class="vhdllogic">1'b0</span>, <a class="code" href="classocs__control.html#a02b5f619bee718ffca6c320ab96bda12">blitter_busy</a>, <a class="code" href="classocs__control.html#aa7ea7fc799ab33140366bd1015496a8d">blitter_zero</a>, <span class="vhdllogic">2'b00</span>, <a class="code" href="classocs__control.html#a2ef3aff81fd20f8ae91d3e66c046fffe">dma_con</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">0</span>] };
<a name="l00243"></a>00243 <span class="keyword">// VPOSR, VHPOSR</span>
<a name="l00244"></a>00244 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#ac7648944e0726e364b9509f1a0b81c12">WE_I</a> == <span class="vhdllogic">1'b0</span> && { <a class="code" href="classocs__control.html#a5287d0f0371bd2793e15feb3e1871bbd">ADR_I</a>, <span class="vhdllogic">2'b0</span> } == <span class="vhdllogic">9'h004</span>) <a class="code" href="classocs__control.html#a4c36d95eefa6d567b8b4e8d476cd3a96">slave_DAT_O</a> <= { <a class="code" href="classocs__control.html#a60428caa020a8abe12a58b707c2f4dcc">long_frame</a>, <span class="vhdllogic">14'd0</span>, <a class="code" href="classocs__control.html#a4550e00911796d007466de7625bd0b2a">line_number</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>], <a class="code" href="classocs__control.html#a91b282041c78283ad2fd1a333cf3fdc4">column_number</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">1</span>] };
<a name="l00245"></a>00245 <span class="keyword">// INTENAR, INTREQR</span>
<a name="l00246"></a>00246 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#ac7648944e0726e364b9509f1a0b81c12">WE_I</a> == <span class="vhdllogic">1'b0</span> && { <a class="code" href="classocs__control.html#a5287d0f0371bd2793e15feb3e1871bbd">ADR_I</a>, <span class="vhdllogic">2'b0</span> } == <span class="vhdllogic">9'h01C</span>) <a class="code" href="classocs__control.html#a4c36d95eefa6d567b8b4e8d476cd3a96">slave_DAT_O</a> <= { <span class="vhdllogic">1'b0</span>, <a class="code" href="classocs__control.html#a3525e0a8a3eada445af773a732dd0469">int_ena</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">1'b0</span>, <a class="code" href="classocs__control.html#a37d5b61b43de582a29e66d99937762db">int_req</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">0</span>] };
<a name="l00247"></a>00247 <span class="keyword">// ADKCONR, POT0DAT read implemented here</span>
<a name="l00248"></a>00248 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#ac7648944e0726e364b9509f1a0b81c12">WE_I</a> == <span class="vhdllogic">1'b0</span> && { <a class="code" href="classocs__control.html#a5287d0f0371bd2793e15feb3e1871bbd">ADR_I</a>, <span class="vhdllogic">2'b0</span> } == <span class="vhdllogic">9'h010</span>) <a class="code" href="classocs__control.html#a4c36d95eefa6d567b8b4e8d476cd3a96">slave_DAT_O</a> <= { <span class="vhdllogic">1'b0</span>, <a class="code" href="classocs__control.html#ad1c254c7e4551d7f373b552e40652f5f">adk_con</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">0</span>], <a class="code" href="classocs__control.html#aa0f199c211813332f0988a4b8a6a3a02">na_pot0dat</a> };
<a name="l00249"></a>00249 <span class="keyword">// INTREQ, ADKCON</span>
<a name="l00250"></a>00250 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#ac7648944e0726e364b9509f1a0b81c12">WE_I</a> == <span class="vhdllogic">1'b1</span> && { <a class="code" href="classocs__control.html#a5287d0f0371bd2793e15feb3e1871bbd">ADR_I</a>, <span class="vhdllogic">2'b0</span> } == <span class="vhdllogic">9'h09C</span>) <span class="vhdlkeyword">begin</span>
<a name="l00251"></a>00251 <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#a6eb7afa02ef30b83f4553c2710cb219d">SEL_I</a>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b11</span>) <span class="vhdlkeyword">begin</span>
<a name="l00252"></a>00252 <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#a8a577d05f486a2b93a18f90ae5a08646">slave_DAT_I</a>[<span class="vhdllogic">15</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classocs__control.html#ad1c254c7e4551d7f373b552e40652f5f">adk_con</a> <= <a class="code" href="classocs__control.html#ad1c254c7e4551d7f373b552e40652f5f">adk_con</a> | <a class="code" href="classocs__control.html#a8a577d05f486a2b93a18f90ae5a08646">slave_DAT_I</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">0</span>];
<a name="l00253"></a>00253 <span class="vhdlkeyword">else</span> <a class="code" href="classocs__control.html#ad1c254c7e4551d7f373b552e40652f5f">adk_con</a> <= <a class="code" href="classocs__control.html#ad1c254c7e4551d7f373b552e40652f5f">adk_con</a> & (~<a class="code" href="classocs__control.html#a8a577d05f486a2b93a18f90ae5a08646">slave_DAT_I</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">0</span>]);
<a name="l00254"></a>00254 <span class="vhdlkeyword">end</span>
<a name="l00255"></a>00255 <span class="vhdlkeyword">end</span>
<a name="l00256"></a>00256 <span class="vhdlkeyword">end</span>
<a name="l00257"></a>00257
<a name="l00258"></a>00258 <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#a2b96a7c9eef58084d7c25b4cda2c4ed8">CYC_I</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classocs__control.html#a26071b95b282cb6ff3aac96128f0737a">STB_I</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classocs__control.html#a8f9ec718b2729125a55d8befe1f27435">ACK_O</a> == <span class="vhdllogic">1'b0</span> && <a class="code" href="classocs__control.html#ac7648944e0726e364b9509f1a0b81c12">WE_I</a> == <span class="vhdllogic">1'b1</span> && { <a class="code" href="classocs__control.html#a5287d0f0371bd2793e15feb3e1871bbd">ADR_I</a>, <span class="vhdllogic">2'b0</span> } == <span class="vhdllogic">9'h09C</span> && <a class="code" href="classocs__control.html#a6eb7afa02ef30b83f4553c2710cb219d">SEL_I</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">2</span>] == <span class="vhdllogic">2'b11</span>) <span class="vhdlkeyword">begin</span>
<a name="l00259"></a>00259 <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#a8a577d05f486a2b93a18f90ae5a08646">slave_DAT_I</a>[<span class="vhdllogic">31</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classocs__control.html#a37d5b61b43de582a29e66d99937762db">int_req</a> <= (<a class="code" href="classocs__control.html#a37d5b61b43de582a29e66d99937762db">int_req</a> | (<a class="code" href="classocs__control.html#a50bcd8b53c850440d22c18a40f5a3255">new_int_req</a> <span class="keyword">/*& int_ena**/</span>)) | <a class="code" href="classocs__control.html#a8a577d05f486a2b93a18f90ae5a08646">slave_DAT_I</a>[<span class="vhdllogic">30</span>:<span class="vhdllogic">16</span>];
<a name="l00260"></a>00260 <span class="vhdlkeyword">else</span> <a class="code" href="classocs__control.html#a37d5b61b43de582a29e66d99937762db">int_req</a> <= (<a class="code" href="classocs__control.html#a37d5b61b43de582a29e66d99937762db">int_req</a> | (<a class="code" href="classocs__control.html#a50bcd8b53c850440d22c18a40f5a3255">new_int_req</a> <span class="keyword">/*& int_ena**/</span>)) & (~<a class="code" href="classocs__control.html#a8a577d05f486a2b93a18f90ae5a08646">slave_DAT_I</a>[<span class="vhdllogic">30</span>:<span class="vhdllogic">16</span>]);
<a name="l00261"></a>00261 <span class="vhdlkeyword">end</span>
<a name="l00262"></a>00262 <span class="vhdlkeyword">else</span> <a class="code" href="classocs__control.html#a37d5b61b43de582a29e66d99937762db">int_req</a> <= (<a class="code" href="classocs__control.html#a37d5b61b43de582a29e66d99937762db">int_req</a> | (<a class="code" href="classocs__control.html#a50bcd8b53c850440d22c18a40f5a3255">new_int_req</a> <span class="keyword">/*& int_ena**/</span>));
<a name="l00263"></a>00263
<a name="l00264"></a>00264 <span class="vhdlkeyword">end</span>
<a name="l00265"></a>00265 <span class="vhdlkeyword">end</span>
<a name="l00266"></a>00266
<a name="l00267"></a>00267
<a name="l00268"></a>00268
<a name="l00269"></a>00269
<a name="l00270"></a>00270 <span class="keyword">// 1/10 fCPU == 1/20 color clock</span>
<a name="l00271"></a><a class="code" href="classocs__control.html#aa9b59818fff4230873e441c8a2a60849">00271</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classocs__control.html#aa9b59818fff4230873e441c8a2a60849">counter_709379_hz</a>;
<a name="l00272"></a><a class="code" href="classocs__control.html#a457e5455cd5940e951513a66fcb55270">00272</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classocs__control.html#a78eebaf1d7122debfc56eebb02678f7c">clk_30</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classocs__control.html#a246ab8bc07755c51fdd905891ec461e7">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l00273"></a>00273 <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#a246ab8bc07755c51fdd905891ec461e7">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
<a name="l00274"></a>00274 <a class="code" href="classocs__control.html#aa9b59818fff4230873e441c8a2a60849">counter_709379_hz</a> <= <span class="vhdllogic">3'd0</span>;
<a name="l00275"></a>00275 <a class="code" href="classocs__control.html#a0197eedf5b87ff26b0b2035e18b8c1c1">pulse_709379_hz</a> <= <span class="vhdllogic">1'b0</span>;
<a name="l00276"></a>00276 <span class="vhdlkeyword">end</span>
<a name="l00277"></a>00277 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#ac0fa0cd71802281503990be9fd87f900">pulse_color</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
<a name="l00278"></a>00278 <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#aa9b59818fff4230873e441c8a2a60849">counter_709379_hz</a> == <span class="vhdllogic">3'd4</span>) <span class="vhdlkeyword">begin</span>
<a name="l00279"></a>00279 <a class="code" href="classocs__control.html#a0197eedf5b87ff26b0b2035e18b8c1c1">pulse_709379_hz</a> <= <span class="vhdllogic">1'b1</span>;
<a name="l00280"></a>00280 <a class="code" href="classocs__control.html#aa9b59818fff4230873e441c8a2a60849">counter_709379_hz</a> <= <span class="vhdllogic">3'd0</span>;
<a name="l00281"></a>00281 <span class="vhdlkeyword">end</span>
<a name="l00282"></a>00282 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
<a name="l00283"></a>00283 <a class="code" href="classocs__control.html#a0197eedf5b87ff26b0b2035e18b8c1c1">pulse_709379_hz</a> <= <span class="vhdllogic">1'b0</span>;
<a name="l00284"></a>00284 <a class="code" href="classocs__control.html#aa9b59818fff4230873e441c8a2a60849">counter_709379_hz</a> <= <a class="code" href="classocs__control.html#aa9b59818fff4230873e441c8a2a60849">counter_709379_hz</a> + <span class="vhdllogic">3'd1</span>;
<a name="l00285"></a>00285 <span class="vhdlkeyword">end</span>
<a name="l00286"></a>00286 <span class="vhdlkeyword">end</span>
<a name="l00287"></a>00287 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
<a name="l00288"></a>00288 <a class="code" href="classocs__control.html#a0197eedf5b87ff26b0b2035e18b8c1c1">pulse_709379_hz</a> <= <span class="vhdllogic">1'b0</span>;
<a name="l00289"></a>00289 <span class="vhdlkeyword">end</span>
<a name="l00290"></a>00290 <span class="vhdlkeyword">end</span>
<a name="l00291"></a>00291
<a name="l00292"></a>00292 <span class="keyword">// 1/2 fCPU = 1 color clock</span>
<a name="l00293"></a>00293 <span class="keyword">// 3.546875MHz</span>
<a name="l00294"></a>00294 <span class="vhdlkeyword">assign</span> <a class="code" href="classocs__control.html#ac0fa0cd71802281503990be9fd87f900">pulse_color</a> = (<a class="code" href="classocs__control.html#a8465c5335d8e7bc89684c040e41cbd53">pulse_cpu</a> == <span class="vhdllogic">1'b1</span>) && (<a class="code" href="classocs__control.html#a4e8810952f8e3f0d2aaf70f534825718">pulse_counter</a> == <span class="vhdllogic">1'b1</span>);
<a name="l00295"></a>00295
<a name="l00296"></a><a class="code" href="classocs__control.html#a4e8810952f8e3f0d2aaf70f534825718">00296</a> <span class="vhdlkeyword">reg</span> <a class="code" href="classocs__control.html#a4e8810952f8e3f0d2aaf70f534825718">pulse_counter</a>;
<a name="l00297"></a><a class="code" href="classocs__control.html#a896ae4138df87842bae2e3beddb07953">00297</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classocs__control.html#a78eebaf1d7122debfc56eebb02678f7c">clk_30</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classocs__control.html#a246ab8bc07755c51fdd905891ec461e7">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l00298"></a>00298 <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#a246ab8bc07755c51fdd905891ec461e7">reset_n</a> == <span class="vhdllogic">1'b0</span>) <a class="code" href="classocs__control.html#a4e8810952f8e3f0d2aaf70f534825718">pulse_counter</a> <= <span class="vhdllogic">1'b0</span>;
<a name="l00299"></a>00299 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#a8465c5335d8e7bc89684c040e41cbd53">pulse_cpu</a> == <span class="vhdllogic">1'b1</span>) <a class="code" href="classocs__control.html#a4e8810952f8e3f0d2aaf70f534825718">pulse_counter</a> <= ~<a class="code" href="classocs__control.html#a4e8810952f8e3f0d2aaf70f534825718">pulse_counter</a>;
<a name="l00300"></a>00300 <span class="vhdlkeyword">end</span>
<a name="l00301"></a>00301
<a name="l00302"></a>00302 <span class="keyword">// fCPU</span>
<a name="l00303"></a>00303 <span class="keyword">// in: 30MHz, out: 7.09375MHz -> 960 - 227</span>
<a name="l00304"></a><a class="code" href="classocs__control.html#a26d607f09a884c29628f3d1fb27d2284">00304</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">10</span>:<span class="vhdllogic">0</span>] <a class="code" href="classocs__control.html#a26d607f09a884c29628f3d1fb27d2284">counter_cpu</a>;
<a name="l00305"></a><a class="code" href="classocs__control.html#a8465c5335d8e7bc89684c040e41cbd53">00305</a> <span class="vhdlkeyword">reg</span> <a class="code" href="classocs__control.html#a8465c5335d8e7bc89684c040e41cbd53">pulse_cpu</a>;
<a name="l00306"></a><a class="code" href="classocs__control.html#a42a3550bb1bca3965ecb62d3653ed6b6">00306</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classocs__control.html#a78eebaf1d7122debfc56eebb02678f7c">clk_30</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classocs__control.html#a246ab8bc07755c51fdd905891ec461e7">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l00307"></a>00307 <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#a246ab8bc07755c51fdd905891ec461e7">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
<a name="l00308"></a>00308 <a class="code" href="classocs__control.html#a26d607f09a884c29628f3d1fb27d2284">counter_cpu</a> <= <span class="vhdllogic">11'd960</span>;
<a name="l00309"></a>00309 <a class="code" href="classocs__control.html#a8465c5335d8e7bc89684c040e41cbd53">pulse_cpu</a> <= <span class="vhdllogic">1'b0</span>;
<a name="l00310"></a>00310 <span class="vhdlkeyword">end</span>
<a name="l00311"></a>00311 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#a26d607f09a884c29628f3d1fb27d2284">counter_cpu</a> <= <span class="vhdllogic">11'd114</span>) <span class="vhdlkeyword">begin</span>
<a name="l00312"></a>00312 <a class="code" href="classocs__control.html#a26d607f09a884c29628f3d1fb27d2284">counter_cpu</a> <= <a class="code" href="classocs__control.html#a26d607f09a884c29628f3d1fb27d2284">counter_cpu</a> - <span class="vhdllogic">11'd227</span> + <span class="vhdllogic">11'd960</span>;
<a name="l00313"></a>00313 <a class="code" href="classocs__control.html#a8465c5335d8e7bc89684c040e41cbd53">pulse_cpu</a> <= <span class="vhdllogic">1'b1</span>;
<a name="l00314"></a>00314 <span class="vhdlkeyword">end</span>
<a name="l00315"></a>00315 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#a26d607f09a884c29628f3d1fb27d2284">counter_cpu</a> < <span class="vhdllogic">11'd227</span>) <span class="vhdlkeyword">begin</span>
<a name="l00316"></a>00316 <a class="code" href="classocs__control.html#a26d607f09a884c29628f3d1fb27d2284">counter_cpu</a> <= <a class="code" href="classocs__control.html#a26d607f09a884c29628f3d1fb27d2284">counter_cpu</a> + <span class="vhdllogic">11'd960</span>;
<a name="l00317"></a>00317 <a class="code" href="classocs__control.html#a8465c5335d8e7bc89684c040e41cbd53">pulse_cpu</a> <= <span class="vhdllogic">1'b0</span>;
<a name="l00318"></a>00318 <span class="vhdlkeyword">end</span>
<a name="l00319"></a>00319 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classocs__control.html#a26d607f09a884c29628f3d1fb27d2284">counter_cpu</a> > <span class="vhdllogic">11'd960</span>) <span class="vhdlkeyword">begin</span>
<a name="l00320"></a>00320 <a class="code" href="classocs__control.html#a26d607f09a884c29628f3d1fb27d2284">counter_cpu</a> <= <a class="code" href="classocs__control.html#a26d607f09a884c29628f3d1fb27d2284">counter_cpu</a> - <span class="vhdllogic">11'd227</span> - <span class="vhdllogic">11'd227</span>;
<a name="l00321"></a>00321 <a class="code" href="classocs__control.html#a8465c5335d8e7bc89684c040e41cbd53">pulse_cpu</a> <= <span class="vhdllogic">1'b1</span>;
<a name="l00322"></a>00322 <span class="vhdlkeyword">end</span>
<a name="l00323"></a>00323 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
<a name="l00324"></a>00324 <a class="code" href="classocs__control.html#a26d607f09a884c29628f3d1fb27d2284">counter_cpu</a> <= <a class="code" href="classocs__control.html#a26d607f09a884c29628f3d1fb27d2284">counter_cpu</a> - <span class="vhdllogic">11'd227</span>;
<a name="l00325"></a>00325 <a class="code" href="classocs__control.html#a8465c5335d8e7bc89684c040e41cbd53">pulse_cpu</a> <= <span class="vhdllogic">1'b0</span>;
<a name="l00326"></a>00326 <span class="vhdlkeyword">end</span>
<a name="l00327"></a>00327 <span class="vhdlkeyword">end</span>
<a name="l00328"></a>00328
<a name="l00329"></a>00329 <span class="vhdlkeyword">endmodule</span>
<a name="l00330"></a>00330
</pre></div></div>
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