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[/] [artec_dongle_ii_fpga/] [trunk/] [src/] [postcode_ser/] [fifo_inst.vhd] - Rev 9
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fifo_inst : fifo PORT MAP ( aclr => aclr_sig, clock => clock_sig, data => data_sig, rdreq => rdreq_sig, wrreq => wrreq_sig, almost_full => almost_full_sig, empty => empty_sig, full => full_sig, q => q_sig, usedw => usedw_sig );