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[/] [avr_hp/] [trunk/] [ise/] [ise_v5_cm3_one/] [avr_core_cm3_top.twr] - Rev 2
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--------------------------------------------------------------------------------
Release 11.1 Trace (nt)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise
C:/EDAptability/coremultiplier/reference/avr/ise/ise_v5_cm3_one_syneda/ise_v5_cm3_one_syneda/ise_v5_cm3_one_syneda.ise
-intstyle ise -v 3 -s 3 -fastpaths -xml avr_core_cm3_top.twx
avr_core_cm3_top.ncd -o avr_core_cm3_top.twr avr_core_cm3_top.pcf -ucf
avr_core_cm3_top.ucf
Design file: avr_core_cm3_top.ncd
Physical constraint file: avr_core_cm3_top.pcf
Device,package,speed: xc5vlx50,ff324,-3 (PRODUCTION 1.64 2009-03-03, STEPPING level 0)
Report level: verbose report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
================================================================================
Timing constraint: TS_cp2 = PERIOD TIMEGRP "cp2" 4.5 ns HIGH 50%;
184139 paths analyzed, 3843 endpoints analyzed, 33 failing endpoints
33 timing errors detected. (33 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 4.819ns.
--------------------------------------------------------------------------------
Slack (setup path): -0.319ns (requirement - (data path - clock path skew + uncertainty))
Source: AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1_16 (FF)
Destination: AVR_Core_cm3_Inst/ALU_Inst/alu_n_flag_out_int_cml_2 (FF)
Requirement: 4.500ns
Data Path Delay: 4.660ns (Levels of Logic = 11)
Clock Path Skew: -0.124ns (1.023 - 1.147)
Source Clock: cp2_BUFGP rising at 0.000ns
Destination Clock: cp2_BUFGP rising at 4.500ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path: AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1_16 to AVR_Core_cm3_Inst/ALU_Inst/alu_n_flag_out_int_cml_2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X16Y32.CQ Tcko 0.346 AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1<16>
AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1_16
SLICE_X16Y32.D4 net (fanout=8) 0.429 AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1<16>
SLICE_X16Y32.D Tilo 0.080 AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1<16>
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>22
SLICE_X16Y32.B5 net (fanout=1) 0.285 AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>22
SLICE_X16Y32.B Tilo 0.080 AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1<16>
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>71
SLICE_X16Y32.A5 net (fanout=1) 0.178 AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>71
SLICE_X16Y32.A Tilo 0.080 AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1<16>
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>142
SLICE_X16Y36.A6 net (fanout=1) 0.372 AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>142
SLICE_X16Y36.A Tilo 0.080 AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1<24>
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>226
SLICE_X16Y36.B6 net (fanout=1) 0.121 AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>226
SLICE_X16Y36.B Tilo 0.080 AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1<24>
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>310
SLICE_X23Y41.A6 net (fanout=1) 0.505 AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>310
SLICE_X23Y41.A Tilo 0.080 AVR_Core_cm3_Inst/BP_Inst/reg_rd_out_cml_2<2>
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>396
SLICE_X23Y41.B6 net (fanout=1) 0.105 AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>396
SLICE_X23Y41.B Tilo 0.080 AVR_Core_cm3_Inst/BP_Inst/reg_rd_out_cml_2<2>
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>480
SLICE_X22Y41.A3 net (fanout=19) 0.491 AVR_Core_cm3_Inst/reg_rd_out<1>
SLICE_X22Y41.A Tilo 0.080 AVR_Core_cm3_Inst/ALU_Inst/neg_op_carry_cml_2<6>
AVR_Core_cm3_Inst/ALU_Inst/neg_op_carry_3_and00001
SLICE_X22Y41.D6 net (fanout=6) 0.268 AVR_Core_cm3_Inst/ALU_Inst/neg_op_carry<3>
SLICE_X22Y41.D Tilo 0.080 AVR_Core_cm3_Inst/ALU_Inst/neg_op_carry_cml_2<6>
AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_7_or000043
SLICE_X21Y42.D1 net (fanout=1) 0.624 AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_7_or000043
SLICE_X21Y42.D Tilo 0.080 AVR_Core_cm3_Inst/ALU_Inst/alu_n_flag_out_int_cml_2
AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_7_or000062
SLICE_X21Y42.C6 net (fanout=1) 0.106 AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_7_or000062
SLICE_X21Y42.CLK Tas 0.030 AVR_Core_cm3_Inst/ALU_Inst/alu_n_flag_out_int_cml_2
AVR_Core_cm3_Inst/ALU_Inst/alu_n_flag_out_int_cml_2_rstpot
AVR_Core_cm3_Inst/ALU_Inst/alu_n_flag_out_int_cml_2
------------------------------------------------- ---------------------------
Total 4.660ns (1.176ns logic, 3.484ns route)
(25.2% logic, 74.8% route)
--------------------------------------------------------------------------------
Slack (setup path): -0.286ns (requirement - (data path - clock path skew + uncertainty))
Source: AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1_18 (FF)
Destination: AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_cml_2_5 (FF)
Requirement: 4.500ns
Data Path Delay: 4.600ns (Levels of Logic = 9)
Clock Path Skew: -0.151ns (1.022 - 1.173)
Source Clock: cp2_BUFGP rising at 0.000ns
Destination Clock: cp2_BUFGP rising at 4.500ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path: AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1_18 to AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_cml_2_5
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X15Y37.AQ Tcko 0.326 AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1<26>
AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1_18
SLICE_X13Y35.A1 net (fanout=8) 0.750 AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1<18>
SLICE_X13Y35.A Tilo 0.080 AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_1_17_7
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<4>71
SLICE_X13Y35.C6 net (fanout=1) 0.226 AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<4>71
SLICE_X13Y35.C Tilo 0.080 AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_1_17_7
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<4>142
SLICE_X13Y35.D5 net (fanout=1) 0.164 AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<4>142
SLICE_X13Y35.D Tilo 0.080 AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_1_17_7
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<4>226
SLICE_X12Y37.A6 net (fanout=1) 0.224 AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<4>226
SLICE_X12Y37.A Tilo 0.080 AVR_Core_cm3_Inst/GPRF_Inst/r26h_cml_1<7>
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<4>310
SLICE_X12Y37.B6 net (fanout=1) 0.121 AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<4>310
SLICE_X12Y37.B Tilo 0.080 AVR_Core_cm3_Inst/GPRF_Inst/r26h_cml_1<7>
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<4>396
SLICE_X22Y42.C6 net (fanout=1) 0.558 AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<4>396
SLICE_X22Y42.C Tilo 0.080 AVR_Core_cm3_Inst/BP_Inst/reg_rd_out_cml_2<4>
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<4>480
SLICE_X22Y42.D5 net (fanout=19) 0.233 AVR_Core_cm3_Inst/reg_rd_out<4>
SLICE_X22Y42.D Tilo 0.080 AVR_Core_cm3_Inst/BP_Inst/reg_rd_out_cml_2<4>
AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_5_or000086
SLICE_X22Y43.B2 net (fanout=1) 0.927 AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_5_or000086
SLICE_X22Y43.B Tilo 0.080 AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_3_or000047
AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_5_or0000113
SLICE_X22Y45.B4 net (fanout=1) 0.402 AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_5_or0000113
SLICE_X22Y45.CLK Tas 0.029 AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_cml_2<5>
AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_5_or00001891
AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_cml_2_5
------------------------------------------------- ---------------------------
Total 4.600ns (0.995ns logic, 3.605ns route)
(21.6% logic, 78.4% route)
--------------------------------------------------------------------------------
Slack (setup path): -0.285ns (requirement - (data path - clock path skew + uncertainty))
Source: AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_1_18_1 (FF)
Destination: AVR_Core_cm3_Inst/ALU_Inst/alu_n_flag_out_int_cml_2 (FF)
Requirement: 4.500ns
Data Path Delay: 4.626ns (Levels of Logic = 10)
Clock Path Skew: -0.124ns (1.023 - 1.147)
Source Clock: cp2_BUFGP rising at 0.000ns
Destination Clock: cp2_BUFGP rising at 4.500ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path: AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_1_18_1 to AVR_Core_cm3_Inst/ALU_Inst/alu_n_flag_out_int_cml_2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X17Y32.BQ Tcko 0.326 AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_1_18_3
AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_1_18_1
SLICE_X16Y32.B1 net (fanout=2) 0.780 AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_1_18_1
SLICE_X16Y32.B Tilo 0.080 AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1<16>
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>71
SLICE_X16Y32.A5 net (fanout=1) 0.178 AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>71
SLICE_X16Y32.A Tilo 0.080 AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1<16>
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>142
SLICE_X16Y36.A6 net (fanout=1) 0.372 AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>142
SLICE_X16Y36.A Tilo 0.080 AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1<24>
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>226
SLICE_X16Y36.B6 net (fanout=1) 0.121 AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>226
SLICE_X16Y36.B Tilo 0.080 AVR_Core_cm3_Inst/GPRF_Inst/sg_rd_decode_cml_1<24>
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>310
SLICE_X23Y41.A6 net (fanout=1) 0.505 AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>310
SLICE_X23Y41.A Tilo 0.080 AVR_Core_cm3_Inst/BP_Inst/reg_rd_out_cml_2<2>
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>396
SLICE_X23Y41.B6 net (fanout=1) 0.105 AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>396
SLICE_X23Y41.B Tilo 0.080 AVR_Core_cm3_Inst/BP_Inst/reg_rd_out_cml_2<2>
AVR_Core_cm3_Inst/GPRF_Inst/reg_rd_out<1>480
SLICE_X22Y41.A3 net (fanout=19) 0.491 AVR_Core_cm3_Inst/reg_rd_out<1>
SLICE_X22Y41.A Tilo 0.080 AVR_Core_cm3_Inst/ALU_Inst/neg_op_carry_cml_2<6>
AVR_Core_cm3_Inst/ALU_Inst/neg_op_carry_3_and00001
SLICE_X22Y41.D6 net (fanout=6) 0.268 AVR_Core_cm3_Inst/ALU_Inst/neg_op_carry<3>
SLICE_X22Y41.D Tilo 0.080 AVR_Core_cm3_Inst/ALU_Inst/neg_op_carry_cml_2<6>
AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_7_or000043
SLICE_X21Y42.D1 net (fanout=1) 0.624 AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_7_or000043
SLICE_X21Y42.D Tilo 0.080 AVR_Core_cm3_Inst/ALU_Inst/alu_n_flag_out_int_cml_2
AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_7_or000062
SLICE_X21Y42.C6 net (fanout=1) 0.106 AVR_Core_cm3_Inst/ALU_Inst/alu_data_out_int_7_or000062
SLICE_X21Y42.CLK Tas 0.030 AVR_Core_cm3_Inst/ALU_Inst/alu_n_flag_out_int_cml_2
AVR_Core_cm3_Inst/ALU_Inst/alu_n_flag_out_int_cml_2_rstpot
AVR_Core_cm3_Inst/ALU_Inst/alu_n_flag_out_int_cml_2
------------------------------------------------- ---------------------------
Total 4.626ns (1.076ns logic, 3.550ns route)
(23.3% logic, 76.7% route)
--------------------------------------------------------------------------------
Hold Paths: TS_cp2 = PERIOD TIMEGRP "cp2" 4.5 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack (hold path): 0.289ns (requirement - (clock path skew + uncertainty - data path))
Source: AVR_Core_cm3_Inst/pm_fetch_dec_Inst/idc_rcall_cml_2 (FF)
Destination: AVR_Core_cm3_Inst/pm_fetch_dec_Inst/rcall_st1 (FF)
Requirement: 0.000ns
Data Path Delay: 0.398ns (Levels of Logic = 1)
Clock Path Skew: 0.109ns (1.150 - 1.041)
Source Clock: cp2_BUFGP rising at 4.500ns
Destination Clock: cp2_BUFGP rising at 4.500ns
Clock Uncertainty: 0.000ns
Minimum Data Path: AVR_Core_cm3_Inst/pm_fetch_dec_Inst/idc_rcall_cml_2 to AVR_Core_cm3_Inst/pm_fetch_dec_Inst/rcall_st1
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X9Y60.BQ Tcko 0.300 AVR_Core_cm3_Inst/pm_fetch_dec_Inst/idc_rcall_cml_2
AVR_Core_cm3_Inst/pm_fetch_dec_Inst/idc_rcall_cml_2
SLICE_X11Y59.A6 net (fanout=21) 0.228 AVR_Core_cm3_Inst/pm_fetch_dec_Inst/idc_rcall_cml_2
SLICE_X11Y59.CLK Tah (-Th) 0.130 AVR_Core_cm3_Inst/pm_fetch_dec_Inst/icall_st2
AVR_Core_cm3_Inst/pm_fetch_dec_Inst/rcall_st1_mux00011
AVR_Core_cm3_Inst/pm_fetch_dec_Inst/rcall_st1
------------------------------------------------- ---------------------------
Total 0.398ns (0.170ns logic, 0.228ns route)
(42.7% logic, 57.3% route)
--------------------------------------------------------------------------------
Slack (hold path): 0.305ns (requirement - (clock path skew + uncertainty - data path))
Source: AVR_Core_cm3_Inst/GPRF_Inst/r26h_cml_2_0 (FF)
Destination: AVR_Core_cm3_Inst/GPRF_Inst/r26h_0 (FF)
Requirement: 0.000ns
Data Path Delay: 0.357ns (Levels of Logic = 1)
Clock Path Skew: 0.052ns (0.511 - 0.459)
Source Clock: cp2_BUFGP rising at 4.500ns
Destination Clock: cp2_BUFGP rising at 4.500ns
Clock Uncertainty: 0.000ns
Minimum Data Path: AVR_Core_cm3_Inst/GPRF_Inst/r26h_cml_2_0 to AVR_Core_cm3_Inst/GPRF_Inst/r26h_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X11Y37.AQ Tcko 0.300 AVR_Core_cm3_Inst/GPRF_Inst/r26h_cml_2<3>
AVR_Core_cm3_Inst/GPRF_Inst/r26h_cml_2_0
SLICE_X8Y37.A6 net (fanout=1) 0.208 AVR_Core_cm3_Inst/GPRF_Inst/r26h_cml_2<0>
SLICE_X8Y37.CLK Tah (-Th) 0.151 AVR_Core_cm3_Inst/GPRF_Inst/r26h<3>
AVR_Core_cm3_Inst/GPRF_Inst/r26h_mux0003<0>1
AVR_Core_cm3_Inst/GPRF_Inst/r26h_0
------------------------------------------------- ---------------------------
Total 0.357ns (0.149ns logic, 0.208ns route)
(41.7% logic, 58.3% route)
--------------------------------------------------------------------------------
Slack (hold path): 0.308ns (requirement - (clock path skew + uncertainty - data path))
Source: AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_1_25_1 (FF)
Destination: AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_2_25_1 (FF)
Requirement: 0.000ns
Data Path Delay: 0.357ns (Levels of Logic = 0)
Clock Path Skew: 0.049ns (0.443 - 0.394)
Source Clock: cp2_BUFGP rising at 4.500ns
Destination Clock: cp2_BUFGP rising at 4.500ns
Clock Uncertainty: 0.000ns
Minimum Data Path: AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_1_25_1 to AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_2_25_1
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X23Y33.BQ Tcko 0.300 AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_1_25_3
AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_1_25_1
SLICE_X21Y33.BX net (fanout=2) 0.224 AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_1_25_1
SLICE_X21Y33.CLK Tckdi (-Th) 0.167 AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_2_25_3
AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_2_25_1
------------------------------------------------- ---------------------------
Total 0.357ns (0.133ns logic, 0.224ns route)
(37.3% logic, 62.7% route)
--------------------------------------------------------------------------------
Component Switching Limit Checks: TS_cp2 = PERIOD TIMEGRP "cp2" 4.5 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 3.300ns (period - (min low pulse limit / (low pulse / period)))
Period: 4.500ns
Low pulse: 2.250ns
Low pulse limit: 0.600ns (Twpl)
Physical resource: AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_2_0_7/CLK
Logical resource: AVR_Core_cm3_Inst/GPRF_Inst/Mshreg_register_file_cml_2_0_4/CLK
Location pin: SLICE_X0Y21.CLK
Clock network: cp2_BUFGP
--------------------------------------------------------------------------------
Slack: 3.300ns (period - (min high pulse limit / (high pulse / period)))
Period: 4.500ns
High pulse: 2.250ns
High pulse limit: 0.600ns (Twph)
Physical resource: AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_2_0_7/CLK
Logical resource: AVR_Core_cm3_Inst/GPRF_Inst/Mshreg_register_file_cml_2_0_4/CLK
Location pin: SLICE_X0Y21.CLK
Clock network: cp2_BUFGP
--------------------------------------------------------------------------------
Slack: 3.300ns (period - (min low pulse limit / (low pulse / period)))
Period: 4.500ns
Low pulse: 2.250ns
Low pulse limit: 0.600ns (Twpl)
Physical resource: AVR_Core_cm3_Inst/GPRF_Inst/register_file_cml_2_0_7/CLK
Logical resource: AVR_Core_cm3_Inst/GPRF_Inst/Mshreg_register_file_cml_2_0_5/CLK
Location pin: SLICE_X0Y21.CLK
Clock network: cp2_BUFGP
--------------------------------------------------------------------------------
1 constraint not met.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock to Setup on destination clock cp2
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
cp2 | 4.819| | | |
---------------+---------+---------+---------+---------+
Timing summary:
---------------
Timing errors: 33 Score: 3958 (Setup/Max: 3958, Hold: 0)
Constraints cover 184139 paths, 0 nets, and 8330 connections
Design statistics:
Minimum period: 4.819ns{1} (Maximum frequency: 207.512MHz)
------------------------------------Footnotes-----------------------------------
1) The minimum period statistic assumes all single cycle delays.
Analysis completed Wed Oct 06 16:53:13 2010
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 271 MB