Subversion Repositories axi_vga

`define ram_dep (1024 * 1024)  //2^12
 
module vga_test (
         reset_n   ,
         pixel_clk ,
         hsync     ,
         vsync			,
         de				 ,
         r8        ,
         g8        ,
         b8        
   );
input reset_n, pixel_clk, hsync,vsync,de;
input [7:0] r8, g8, b8;
 
reg	[63:0] ram [`ram_dep-1:0];
initial begin
$readmemh("test.txt", ram);
end
 
reg vsync_d, hsync_d;
reg [15:0] countX, countY, count_de;
reg [23:0] count_data;
reg [7:0] r8_d, g8_d, b8_d;
wire vsync_high_puls = vsync & !vsync_d;
wire hsync_high_puls = hsync & !hsync_d;
always @(negedge reset_n or posedge pixel_clk) begin
       if (!reset_n) count_de <= 0;
       else if (de)  count_de <= count_de +1;
       else          count_de <= 0;
end       
wire active_line_err = (count_de > 800);
always @(negedge reset_n or posedge pixel_clk) begin
       if (!reset_n)               count_data <= 0;
       else if (vsync_high_puls)   count_data <= 0;
       else if (de)  count_data <= count_data +1;
end       
always @(posedge pixel_clk) vsync_d <= vsync;
always @(posedge pixel_clk) hsync_d <= hsync;
 
reg data_err;
always @(posedge pixel_clk) if (de) r8_d <= r8;
always @(posedge pixel_clk) if (de) g8_d <= g8;
always @(posedge pixel_clk) if (de) b8_d <= b8;
wire [63:0] data_in = {8'h0, r8,g8,b8, 8'h0,r8_d,g8_d,b8_d};
wire [63:0] data_check = ram[count_data[23:1]];
always @(negedge reset_n or posedge pixel_clk) begin
       if (!reset_n) data_err <= 0;
       else if (de)  begin
            if (count_data[0]) begin
                  data_err <= (data_in != data_check);        
            end
            else data_err <= 0;
       end
       else data_err <= 0;
end       
 
always @(negedge reset_n or posedge pixel_clk) begin
       if (!reset_n)               countY <= 0;
       else if (vsync_high_puls)   countY <= 0;
       else if (hsync_high_puls)   countY <= countY +1;
end
reg [15:0] line_no;
always @(negedge reset_n or posedge pixel_clk) begin
       if (!reset_n)               line_no <= 0;
       else if (vsync_high_puls)   line_no <= countY;
end
always @(negedge reset_n or posedge pixel_clk) begin
       if (!reset_n)               countX <= 0;
       else if (hsync_high_puls)   countX <= 0;
       else              countX <= countX +1; 
end
reg [15:0] pixel_no;
always @(negedge reset_n or posedge pixel_clk) begin
       if (!reset_n)               pixel_no <= 0;
       else if (hsync_high_puls)   pixel_no <= countX;
end
 
 
endmodule