OpenCores
URL https://opencores.org/ocsvn/blue/blue/trunk

Subversion Repositories blue

[/] [blue/] [trunk/] [blue8/] [transcript] - Rev 2

Compare with Previous | Blame | View Log

# Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 
# do tbuart.fdo 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE III vlog 6.1e Compiler 2006.03 Mar  8 2006
# -- Compiling module rcvr
# 
# Top level modules:
#       rcvr
# Model Technology ModelSim XE III vlog 6.1e Compiler 2006.03 Mar  8 2006
# -- Compiling module txmit
# 
# Top level modules:
#       txmit
# Model Technology ModelSim XE III vlog 6.1e Compiler 2006.03 Mar  8 2006
# -- Compiling module uart
# 
# Top level modules:
#       uart
# Model Technology ModelSim XE III vlog 6.1e Compiler 2006.03 Mar  8 2006
# -- Compiling module tbuart
# 
# Top level modules:
#       tbuart
# Model Technology ModelSim XE III vlog 6.1e Compiler 2006.03 Mar  8 2006
# -- Compiling module glbl
# 
# Top level modules:
#       glbl
# vsim -L xilinxcorelib_ver -L unisims_ver -lib work -t 1ps tbuart glbl 
# Loading work.tbuart
# Loading work.uart
# ** Warning: (vsim-3009) [TSCALE] - Module 'uart' does not have a `timescale directive in effect, but previous modules do.
#         Region: /tbuart/UUT
# Loading work.rcvr
# Loading work.txmit
# Loading work.glbl
# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.wf
# .main_pane.workspace
# .main_pane.signals.interior.cs
do C:/blue71/wave.do
run -all
# No errors or warnings.
# Break at tbuart.tfw line 73
run -all
# Break key hit 
# Break at tbuart.tfw line 45

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.