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[/] [bu_pacman/] [tags/] [arelease/] [Display_Controller_map.map] - Rev 4
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Release 10.1 Map K.31 (nt)
Xilinx Map Application Log File for Design 'Display_Controller'
Design Information
------------------
Command Line : map -ise X:/Display_Controller/Display_Controller.ise -intstyle
ise -p xc3s1000-ft256-4 -cm area -pr off -k 4 -c 100 -o
Display_Controller_map.ncd Display_Controller.ngd Display_Controller.pcf
Target Device : xc3s1000
Target Package : ft256
Target Speed : -4
Mapper Version : spartan3 -- $Revision: 1.1.1.1 $
Mapped Date : Sun Nov 23 21:12:37 2008
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 1
Logic Utilization:
Total Number Slice Registers: 267 out of 15,360 1%
Number used as Flip Flops: 266
Number used as Latches: 1
Number of 4 input LUTs: 248 out of 15,360 1%
Logic Distribution:
Number of occupied Slices: 235 out of 7,680 3%
Number of Slices containing only related logic: 235 out of 235 100%
Number of Slices containing unrelated logic: 0 out of 235 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 311 out of 15,360 2%
Number used as logic: 248
Number used as a route-thru: 63
Number of bonded IOBs: 44 out of 173 25%
Number of RAMB16s: 15 out of 24 62%
Number of BUFGMUXs: 3 out of 8 37%
Peak Memory Usage: 139 MB
Total REAL time to MAP completion: 13 secs
Total CPU time to MAP completion: 2 secs
NOTES:
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
Mapping completed.
See MAP report file "Display_Controller_map.mrp" for details.
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