Subversion Repositories cpu6502_true_cycle

v1.4 2018/09/15
FUNCTIONALITY:
 no errata reported/opened

TIMING:
 no errata reported/opened

SIGNALING:
 no errata reported/opened


v1.4 BETA 2013/07/24
FUNCTIONALITY:
- ADC and SBC in decimal mode (all op codes -
  seems to use a formula different from a real R6502.

TIMING:
- All Branch Instructions 
  (BCC, BCS, BEQ, BNE, BPL, BMI, BVC, BVS)
  4 cycles if branch forward occur and the branch
  instruction lies on a xxFEh location.
  Must be 3 cycles.

SIGNALING:
- Hardware Interrupts NMI & IRQ - NO "SYNC" 
- RESET generates NO SYNC