Subversion Repositories csa

# Copyright (C) 1991-2008 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#               csa_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#               assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY Cyclone
set_global_assignment -name DEVICE EP1C6Q240C8
set_global_assignment -name TOP_LEVEL_ENTITY csa_fpga
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:03:51  APRIL 15, 2009"
set_global_assignment -name LAST_QUARTUS_VERSION 8.1
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -entity csa -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -entity csa -section_id "Root Region"
set_global_assignment -name VERILOG_FILE ../rtl/sbox1.v
set_global_assignment -name VERILOG_FILE ../rtl/sbox2.v
set_global_assignment -name VERILOG_FILE ../rtl/sbox3.v
set_global_assignment -name VERILOG_FILE ../rtl/sbox4.v
set_global_assignment -name VERILOG_FILE ../rtl/sbox5.v
set_global_assignment -name VERILOG_FILE ../rtl/sbox6.v
set_global_assignment -name VERILOG_FILE ../rtl/sbox7.v
set_global_assignment -name VERILOG_FILE ../rtl/sboxes.v
set_global_assignment -name VERILOG_FILE ../rtl/stream_iteration.v
set_global_assignment -name VERILOG_FILE ../rtl/stream_byte.v
set_global_assignment -name VERILOG_FILE ../rtl/stream_8bytes.v
set_global_assignment -name VERILOG_FILE ../rtl/key_perm.v
set_global_assignment -name VERILOG_FILE ../rtl/block_perm.v
set_global_assignment -name VERILOG_FILE ../rtl/block_sbox.v
set_global_assignment -name VERILOG_FILE ../rtl/stream_cypher.v
set_global_assignment -name VERILOG_FILE ../rtl/key_schedule.v
set_global_assignment -name VERILOG_FILE ../rtl/block_decypher.v
set_global_assignment -name VERILOG_FILE ../rtl/decrypt.v
set_global_assignment -name VERILOG_FILE csa_fpga.v