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URL https://opencores.org/ocsvn/darkriscv/darkriscv/trunk

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[/] [darkriscv/] [trunk/] [rtl/] [README.md] - Rev 2

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## Verilog Sources

Description of current Verilog files:

- darkriscv.v: the DarkRISCV core
- darksocv.v: a primitive system on-chip w/ the DarkRISCV core wired to ROM and RAM memories and IO
- darkuart.v: a small full-duplex UART w/ programmable baud-rate
- config.vh: configuration file!

TODO:

- add a cache controller
- add a SDRAM controller
- add a SPI controller 
- add a GbE controller

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