Subversion Repositories funbase_ip_library

<?xml version="1.0" encoding="UTF-8"?>
<system name="udp2hibi_demo_cpu">
 <parameter name="bonusData"><![CDATA[bonusData 
{
   element jtag_uart_0.avalon_jtag_slave
   {
      datum baseAddress
      {
         value = "53792";
         type = "long";
      }
   }
   element n2h2_chan_0.avalon_slave_0
   {
      datum baseAddress
      {
         value = "53248";
         type = "long";
      }
   }
   element clk_0
   {
      datum _sortIndex
      {
         value = "5";
         type = "int";
      }
   }
   element cpu_0
   {
      datum _sortIndex
      {
         value = "4";
         type = "int";
      }
      datum megawizard_uipreferences
      {
         value = "{output_language=VHDL, output_directory=D:\\user\\alhonena\\daci_ip\\trunk\\soc\\upd2hibi_example\\1.0\\quartus}";
         type = "String";
      }
   }
   element cpu_0.jtag_debug_module
   {
      datum baseAddress
      {
         value = "51200";
         type = "long";
      }
   }
   element jtag_uart_0
   {
      datum _sortIndex
      {
         value = "0";
         type = "int";
      }
      datum megawizard_uipreferences
      {
         value = "{}";
         type = "String";
      }
   }
   element n2h2_chan_0
   {
      datum _sortIndex
      {
         value = "6";
         type = "int";
      }
   }
   element onchip_memory2_0
   {
      datum _sortIndex
      {
         value = "1";
         type = "int";
      }
      datum megawizard_uipreferences
      {
         value = "{}";
         type = "String";
      }
   }
   element pin
   {
      datum _sortIndex
      {
         value = "3";
         type = "int";
      }
      datum megawizard_uipreferences
      {
         value = "{}";
         type = "String";
      }
   }
   element pout
   {
      datum _sortIndex
      {
         value = "2";
         type = "int";
      }
      datum megawizard_uipreferences
      {
         value = "{output_language=VHDL, output_directory=D:\\user\\alhonena\\daci_ip\\trunk\\soc\\upd2hibi_example\\1.0\\quartus}";
         type = "String";
      }
   }
   element shared_mem.s1
   {
      datum baseAddress
      {
         value = "32768";
         type = "long";
      }
   }
   element pout.s1
   {
      datum baseAddress
      {
         value = "53760";
         type = "long";
      }
   }
   element pin.s1
   {
      datum baseAddress
      {
         value = "53776";
         type = "long";
      }
   }
   element onchip_memory2_0.s1
   {
      datum baseAddress
      {
         value = "16384";
         type = "long";
      }
   }
   element shared_mem.s2
   {
      datum baseAddress
      {
         value = "32768";
         type = "long";
      }
   }
   element shared_mem
   {
      datum _sortIndex
      {
         value = "7";
         type = "int";
      }
   }
   element udp2hibi_demo_cpu
   {
   }
}
]]></parameter>
 <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
 <parameter name="deviceFamily" value="CYCLONEII" />
 <parameter name="fabricMode" value="SOPC" />
 <parameter name="generateLegacySim" value="false" />
 <parameter name="generationId" value="0" />
 <parameter name="globalResetBus" value="true" />
 <parameter name="hdlLanguage" value="VHDL" />
 <parameter name="maxAdditionalLatency" value="0" />
 <parameter name="projectName">udp2hibi_example.qpf</parameter>
 <parameter name="sopcBorderPoints" value="true" />
 <parameter name="systemHash" value="-16509751738" />
 <parameter name="timeStamp" value="1329121082031" />
 <module kind="clock_source" version="10.1" enabled="1" name="clk_0">
  <parameter name="clockFrequency" value="50000000" />
  <parameter name="clockFrequencyKnown" value="true" />
  <parameter name="inputClockFrequency" value="0" />
  <parameter name="resetSynchronousEdges" value="NONE" />
 </module>
 <module
   kind="altera_avalon_jtag_uart"
   version="10.1"
   enabled="1"
   name="jtag_uart_0">
  <parameter name="allowMultipleConnections" value="false" />
  <parameter name="hubInstanceID" value="0" />
  <parameter name="readBufferDepth" value="64" />
  <parameter name="readIRQThreshold" value="8" />
  <parameter name="simInputCharacterStream" value="" />
  <parameter name="simInteractiveOptions">INTERACTIVE_ASCII_OUTPUT</parameter>
  <parameter name="useRegistersForReadBuffer" value="false" />
  <parameter name="useRegistersForWriteBuffer" value="false" />
  <parameter name="useRelativePathForSimFile" value="false" />
  <parameter name="writeBufferDepth" value="64" />
  <parameter name="writeIRQThreshold" value="8" />
 </module>
 <module
   kind="altera_avalon_onchip_memory2"
   version="10.1"
   enabled="1"
   name="onchip_memory2_0">
  <parameter name="allowInSystemMemoryContentEditor" value="false" />
  <parameter name="blockType" value="AUTO" />
  <parameter name="dataWidth" value="32" />
  <parameter name="deviceFamily" value="Cyclone II" />
  <parameter name="dualPort" value="false" />
  <parameter name="initMemContent" value="true" />
  <parameter name="initializationFileName" value="onchip_memory2_0" />
  <parameter name="instanceID" value="NONE" />
  <parameter name="memorySize" value="16384" />
  <parameter name="readDuringWriteMode" value="DONT_CARE" />
  <parameter name="simAllowMRAMContentsFile" value="false" />
  <parameter name="slave1Latency" value="1" />
  <parameter name="slave2Latency" value="1" />
  <parameter name="useNonDefaultInitFile" value="false" />
  <parameter name="useShallowMemBlocks" value="false" />
  <parameter name="writable" value="true" />
 </module>
 <module kind="altera_avalon_pio" version="10.1" enabled="1" name="pout">
  <parameter name="bitClearingEdgeCapReg" value="false" />
  <parameter name="bitModifyingOutReg" value="false" />
  <parameter name="captureEdge" value="false" />
  <parameter name="clockRate" value="50000000" />
  <parameter name="direction" value="Output" />
  <parameter name="edgeType" value="RISING" />
  <parameter name="generateIRQ" value="false" />
  <parameter name="irqType" value="LEVEL" />
  <parameter name="resetValue" value="0" />
  <parameter name="simDoTestBenchWiring" value="false" />
  <parameter name="simDrivenValue" value="0" />
  <parameter name="width" value="8" />
 </module>
 <module kind="altera_avalon_pio" version="10.1" enabled="1" name="pin">
  <parameter name="bitClearingEdgeCapReg" value="false" />
  <parameter name="bitModifyingOutReg" value="false" />
  <parameter name="captureEdge" value="false" />
  <parameter name="clockRate" value="50000000" />
  <parameter name="direction" value="Input" />
  <parameter name="edgeType" value="RISING" />
  <parameter name="generateIRQ" value="false" />
  <parameter name="irqType" value="LEVEL" />
  <parameter name="resetValue" value="0" />
  <parameter name="simDoTestBenchWiring" value="false" />
  <parameter name="simDrivenValue" value="0" />
  <parameter name="width" value="8" />
 </module>
 <module kind="altera_nios2" version="10.1" enabled="1" name="cpu_0">
  <parameter name="userDefinedSettings" value="" />
  <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
  <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
  <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
  <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
  <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
  <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
  <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
  <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
  <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
  <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
  <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
  <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
  <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
  <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
  <parameter name="setting_showUnpublishedSettings" value="false" />
  <parameter name="setting_showInternalSettings" value="false" />
  <parameter name="setting_shadowRegisterSets" value="0" />
  <parameter name="setting_preciseSlaveAccessErrorException" value="false" />
  <parameter name="setting_preciseIllegalMemAccessException" value="false" />
  <parameter name="setting_preciseDivisionErrorException" value="false" />
  <parameter name="setting_performanceCounter" value="false" />
  <parameter name="setting_perfCounterWidth" value="_32" />
  <parameter name="setting_interruptControllerType" value="Internal" />
  <parameter name="setting_illegalMemAccessDetection" value="false" />
  <parameter name="setting_illegalInstructionsTrap" value="false" />
  <parameter name="setting_fullWaveformSignals" value="false" />
  <parameter name="setting_extraExceptionInfo" value="false" />
  <parameter name="setting_exportPCB" value="false" />
  <parameter name="setting_debugSimGen" value="false" />
  <parameter name="setting_clearXBitsLDNonBypass" value="true" />
  <parameter name="setting_branchPredictionType" value="Automatic" />
  <parameter name="setting_bit31BypassDCache" value="true" />
  <parameter name="setting_bigEndian" value="false" />
  <parameter name="setting_bhtPtrSz" value="_8" />
  <parameter name="setting_bhtIndexPcOnly" value="false" />
  <parameter name="setting_avalonDebugPortPresent" value="false" />
  <parameter name="setting_alwaysEncrypt" value="true" />
  <parameter name="setting_allowFullAddressRange" value="false" />
  <parameter name="setting_activateTrace" value="true" />
  <parameter name="setting_activateTestEndChecker" value="false" />
  <parameter name="setting_activateMonitors" value="true" />
  <parameter name="setting_activateModelChecker" value="false" />
  <parameter name="setting_HDLSimCachesCleared" value="true" />
  <parameter name="setting_HBreakTest" value="false" />
  <parameter name="resetSlave" value="onchip_memory2_0.s1" />
  <parameter name="resetOffset" value="0" />
  <parameter name="muldiv_multiplierType" value="EmbeddedMulFast" />
  <parameter name="muldiv_divider" value="false" />
  <parameter name="mpu_useLimit" value="false" />
  <parameter name="mpu_numOfInstRegion" value="8" />
  <parameter name="mpu_numOfDataRegion" value="8" />
  <parameter name="mpu_minInstRegionSize" value="_12" />
  <parameter name="mpu_minDataRegionSize" value="_12" />
  <parameter name="mpu_enabled" value="false" />
  <parameter name="mmu_uitlbNumEntries" value="_4" />
  <parameter name="mmu_udtlbNumEntries" value="_6" />
  <parameter name="mmu_tlbPtrSz" value="_7" />
  <parameter name="mmu_tlbNumWays" value="_16" />
  <parameter name="mmu_processIDNumBits" value="_8" />
  <parameter name="mmu_enabled" value="false" />
  <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
  <parameter name="mmu_TLBMissExcSlave" value="" />
  <parameter name="mmu_TLBMissExcOffset" value="0" />
  <parameter name="manuallyAssignCpuID" value="false" />
  <parameter name="internalIrqMaskSystemInfo" value="3" />
  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='onchip_memory2_0.s1' start='0x4000' end='0x8000' /><slave name='cpu_0.jtag_debug_module' start='0xC800' end='0xD000' /></address-map>]]></parameter>
  <parameter name="instAddrWidth" value="16" />
  <parameter name="impl" value="Fast" />
  <parameter name="icache_size" value="_4096" />
  <parameter name="icache_ramBlockType" value="Automatic" />
  <parameter name="icache_numTCIM" value="_0" />
  <parameter name="icache_burstType" value="None" />
  <parameter name="exceptionSlave" value="onchip_memory2_0.s1" />
  <parameter name="exceptionOffset" value="32" />
  <parameter name="deviceFeaturesSystemInfo">M512_MEMORY 0 M4K_MEMORY 1 M9K_MEMORY 0 M20K_MEMORY 0 M144K_MEMORY 0 MRAM_MEMORY 0 MLAB_MEMORY 0 ESB 0 EPCS 1 DSP 0 EMUL 1 HARDCOPY 0 LVDS_IO 0 ADDRESS_STALL 1 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 DSP_SHIFTER_BLOCK 0</parameter>
  <parameter name="deviceFamilyName" value="Cyclone II" />
  <parameter name="debug_triggerArming" value="true" />
  <parameter name="debug_level" value="Level1" />
  <parameter name="debug_jtagInstanceID" value="0" />
  <parameter name="debug_embeddedPLL" value="true" />
  <parameter name="debug_debugReqSignals" value="false" />
  <parameter name="debug_assignJtagInstanceID" value="false" />
  <parameter name="debug_OCIOnchipTrace" value="_128" />
  <parameter name="dcache_size" value="_2048" />
  <parameter name="dcache_ramBlockType" value="Automatic" />
  <parameter name="dcache_omitDataMaster" value="false" />
  <parameter name="dcache_numTCDM" value="_0" />
  <parameter name="dcache_lineSize" value="_32" />
  <parameter name="dcache_bursts" value="false" />
  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='onchip_memory2_0.s1' start='0x4000' end='0x8000' /><slave name='shared_mem.s2' start='0x8000' end='0xC000' /><slave name='cpu_0.jtag_debug_module' start='0xC800' end='0xD000' /><slave name='n2h2_chan_0.avalon_slave_0' start='0xD000' end='0xD200' /><slave name='pout.s1' start='0xD200' end='0xD210' /><slave name='pin.s1' start='0xD210' end='0xD220' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xD220' end='0xD228' /></address-map>]]></parameter>
  <parameter name="dataAddrWidth" value="16" />
  <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
  <parameter name="cpuReset" value="false" />
  <parameter name="cpuID" value="0" />
  <parameter name="clockFrequency" value="50000000" />
  <parameter name="breakSlave">cpu_0.jtag_debug_module</parameter>
  <parameter name="breakOffset" value="32" />
 </module>
 <module kind="n2h2_chan" version="1.0" enabled="1" name="n2h2_chan_0">
  <parameter name="data_width_g" value="32" />
  <parameter name="addr_width_g" value="32" />
  <parameter name="amount_width_g" value="16" />
  <parameter name="n_chans_g" value="8" />
  <parameter name="n_chans_bits_g" value="3" />
  <parameter name="hibi_addr_cmp_lo_g" value="8" />
  <parameter name="hibi_addr_cmp_hi_g" value="31" />
  <parameter name="AUTO_CLOCK_SINK_CLOCK_RATE" value="50000000" />
  <parameter name="AUTO_CLOCK_SINK_1_CLOCK_RATE" value="50000000" />
  <parameter name="AUTO_CLOCK_SINK_2_CLOCK_RATE" value="50000000" />
 </module>
 <module
   kind="altera_avalon_onchip_memory2"
   version="10.1"
   enabled="1"
   name="shared_mem">
  <parameter name="allowInSystemMemoryContentEditor" value="false" />
  <parameter name="blockType" value="AUTO" />
  <parameter name="dataWidth" value="32" />
  <parameter name="deviceFamily" value="Cyclone II" />
  <parameter name="dualPort" value="true" />
  <parameter name="initMemContent" value="true" />
  <parameter name="initializationFileName" value="shared_mem" />
  <parameter name="instanceID" value="NONE" />
  <parameter name="memorySize" value="16384" />
  <parameter name="readDuringWriteMode" value="DONT_CARE" />
  <parameter name="simAllowMRAMContentsFile" value="false" />
  <parameter name="slave1Latency" value="1" />
  <parameter name="slave2Latency" value="1" />
  <parameter name="useNonDefaultInitFile" value="false" />
  <parameter name="useShallowMemBlocks" value="false" />
  <parameter name="writable" value="true" />
 </module>
 <connection kind="clock" version="10.1" start="clk_0.clk" end="jtag_uart_0.clk" />
 <connection
   kind="clock"
   version="10.1"
   start="clk_0.clk"
   end="onchip_memory2_0.clk1" />
 <connection kind="clock" version="10.1" start="clk_0.clk" end="pout.clk" />
 <connection kind="clock" version="10.1" start="clk_0.clk" end="pin.clk" />
 <connection kind="clock" version="10.1" start="clk_0.clk" end="cpu_0.clk" />
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.instruction_master"
   end="cpu_0.jtag_debug_module">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0xc800" />
 </connection>
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.data_master"
   end="cpu_0.jtag_debug_module">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0xc800" />
 </connection>
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.instruction_master"
   end="onchip_memory2_0.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x4000" />
 </connection>
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.data_master"
   end="jtag_uart_0.avalon_jtag_slave">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0xd220" />
 </connection>
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.data_master"
   end="onchip_memory2_0.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x4000" />
 </connection>
 <connection kind="avalon" version="10.1" start="cpu_0.data_master" end="pout.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0xd200" />
 </connection>
 <connection kind="avalon" version="10.1" start="cpu_0.data_master" end="pin.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0xd210" />
 </connection>
 <connection
   kind="interrupt"
   version="10.1"
   start="cpu_0.d_irq"
   end="jtag_uart_0.irq">
  <parameter name="irqNumber" value="0" />
 </connection>
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.data_master"
   end="n2h2_chan_0.avalon_slave_0">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0xd000" />
 </connection>
 <connection
   kind="clock"
   version="10.1"
   start="clk_0.clk"
   end="n2h2_chan_0.clock_sink" />
 <connection
   kind="clock"
   version="10.1"
   start="clk_0.clk"
   end="n2h2_chan_0.clock_sink_1" />
 <connection
   kind="clock"
   version="10.1"
   start="clk_0.clk"
   end="n2h2_chan_0.clock_sink_2" />
 <connection
   kind="interrupt"
   version="10.1"
   start="cpu_0.d_irq"
   end="n2h2_chan_0.interrupt_sender">
  <parameter name="irqNumber" value="1" />
 </connection>
 <connection kind="clock" version="10.1" start="clk_0.clk" end="shared_mem.clk1" />
 <connection kind="clock" version="10.1" start="clk_0.clk" end="shared_mem.clk2" />
 <connection
   kind="avalon"
   version="10.1"
   start="cpu_0.data_master"
   end="shared_mem.s2">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x8000" />
 </connection>
 <connection
   kind="avalon"
   version="10.1"
   start="n2h2_chan_0.avalon_master"
   end="shared_mem.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x8000" />
 </connection>
 <connection
   kind="avalon"
   version="10.1"
   start="n2h2_chan_0.avalon_master_1"
   end="shared_mem.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x8000" />
 </connection>
</system>