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[/] [funbase_ip_library/] [trunk/] [TUT/] [soc/] [udp_flood_example_dm9000a/] [1.0/] [ip_xact/] [udp_flood_example_dm9000a.1.0.xml] - Rev 157
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Created by Kactus2 - Open source IP-Xact toolset -->
<!-- http://sourceforge.net/projects/kactus2/ -->
<!-- Date: 18.01.2013 -->
<!-- Time: 12:46:25 -->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>soc</spirit:library>
<spirit:name>udp_flood_example_dm9000a</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:description>Simple example to test the connection FPGA -> PC.
Flooder unit sends all the time, UDP/IP block transfers them to PC. Designer can use netstat, netcat, wireshark or similar to catch the packet at the PC's end.</spirit:description>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>DM9000A</spirit:name>
<spirit:description>Connection to DM9000A chip (Ethernet PHY) found e.g. in DE2 board. Expects 25 MHz clock.</spirit:description>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="ethernet_dm9000a" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="ethernet_dm9000a.absDef" spirit:version="1.0"/>
<spirit:master/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>eth_chip_sel_out</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>DM9000A_eth_chip_sel_out</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>eth_clk_out</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>DM9000A_eth_clk_out</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>eth_cmd_out</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>DM9000A_eth_cmd_out</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>eth_data_inout</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>DM9000A_eth_data_inout</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>eth_interrupt_in</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>DM9000A_eth_interrupt_in</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>eth_read_out</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>DM9000A_eth_read_out</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>eth_reset_out</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>DM9000A_eth_reset_out</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>eth_write_out</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>DM9000A_eth_write_out</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>link_up_out</spirit:name>
<spirit:description>1-bit status</spirit:description>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="gpio_1bit" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="gpio_1bit.absDef" spirit:version="1.0"/>
<spirit:master/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>gpio_out</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>link_up_out_gpio_out</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>rst_n</spirit:name>
<spirit:description>Active-low reset</spirit:description>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="reset.busdef" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="reset.absDef" spirit:version="1.0"/>
<spirit:slave/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RESETn</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>rst_n_RESETn</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>clk_in</spirit:name>
<spirit:description>Clock input.</spirit:description>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.busdef" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.absDef" spirit:version="1.0"/>
<spirit:slave/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>clk_in_CLK</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>kactusHierarchical</spirit:name>
<spirit:envIdentifier></spirit:envIdentifier>
<spirit:hierarchyRef spirit:vendor="TUT" spirit:library="soc" spirit:name="udp_flood_example_dm9000a.designcfg" spirit:version="1.0"/>
<spirit:vendorExtensions>
<kactus2:topLevelViewRef>rtl</kactus2:topLevelViewRef>
</spirit:vendorExtensions>
</spirit:view>
<spirit:view>
<spirit:name>rtl</spirit:name>
<spirit:envIdentifier>VHDL::</spirit:envIdentifier>
<spirit:language spirit:strict="false">vhdl</spirit:language>
<spirit:modelName>udp_flood_example_dm9000a(top_level)</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>vhdlSource</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>DM9000A_eth_chip_sel_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>kactusHierarchical</spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>DM9000A_eth_clk_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>kactusHierarchical</spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>DM9000A_eth_cmd_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>kactusHierarchical</spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>DM9000A_eth_data_inout</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>inout</spirit:direction>
<spirit:vector>
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>kactusHierarchical</spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>DM9000A_eth_interrupt_in</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>kactusHierarchical</spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>DM9000A_eth_read_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>kactusHierarchical</spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>DM9000A_eth_reset_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>kactusHierarchical</spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>DM9000A_eth_write_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>kactusHierarchical</spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>clk_in_CLK</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>kactusHierarchical</spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>link_up_out_gpio_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>kactusHierarchical</spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>rst_n_RESETn</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>kactusHierarchical</spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue>Active-low</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
</spirit:ports>
</spirit:model>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>vhdlSource</spirit:name>
<spirit:description>Top-level vhd generated by Kactus.</spirit:description>
<spirit:group>sourceFiles</spirit:group>
<spirit:file>
<spirit:name>../vhd/udp_flood_example_dm9000a.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">true</spirit:isIncludeFile>
<spirit:logicalName spirit:default="false">work</spirit:logicalName>
<spirit:buildCommand>
<spirit:command>vcom</spirit:command>
<spirit:flags>-quiet -check_synthesis -work work</spirit:flags>
<spirit:replaceDefaultFlags>true</spirit:replaceDefaultFlags>
</spirit:buildCommand>
</spirit:file>
<spirit:defaultFileBuilder>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:command>vcom</spirit:command>
<spirit:flags>-work work -quiet -check_synthesis</spirit:flags>
<spirit:replaceDefaultFlags>false</spirit:replaceDefaultFlags>
</spirit:defaultFileBuilder>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>quartusFiles</spirit:name>
<spirit:description>Pin map settings that will be used by Quartus genrator.</spirit:description>
<spirit:file>
<spirit:name>../../../../ip.hwp.interface/udp_ip/1.0/syn/udp_ip_dm9000a_de2_assignments.qsf</spirit:name>
<spirit:userFileType>quartusPinmap</spirit:userFileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>simulation</spirit:name>
<spirit:file>
<spirit:name>../sim/sim.do</spirit:name>
<spirit:userFileType>modelsimScript</spirit:userFileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
<spirit:description>Executes simulation. Uses force commands to create clock and reset.
Note that PLL requires simulation resolution of 1 ps.</spirit:description>
</spirit:file>
<spirit:file>
<spirit:name>../sim/all_waves.do</spirit:name>
<spirit:userFileType>modelsimScript</spirit:userFileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
<spirit:description>Adds the necessary signals to wave window and formats them. Called by sim.do.</spirit:description>
</spirit:file>
<spirit:file>
<spirit:name>../sim/compile_all.do</spirit:name>
<spirit:userFileType>modelsimScript</spirit:userFileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
<spirit:description>Compile "all" VHDL files (except Altera's simulation models).
</spirit:description>
</spirit:file>
<spirit:file>
<spirit:name>../sim/compile_altera.do</spirit:name>
<spirit:userFileType>modelsimScript</spirit:userFileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
<spirit:description>Compiles Altera's simulation models.
Please edit the path definitions to match your Quartus installation directory.</spirit:description>
</spirit:file>
<spirit:defaultFileBuilder>
<spirit:userFileType>modelsimScript</spirit:userFileType>
<spirit:command>do <scriptname.do></spirit:command>
<spirit:replaceDefaultFlags>false</spirit:replaceDefaultFlags>
</spirit:defaultFileBuilder>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>doc</spirit:name>
<spirit:file>
<spirit:name>../doc/setup.pptx</spirit:name>
<spirit:userFileType>powerPoint</spirit:userFileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:vendorExtensions>
<kactus2:extensions>
<kactus2:kts_attributes>
<kactus2:kts_productHier>Global</kactus2:kts_productHier>
<kactus2:kts_firmness>Mutable</kactus2:kts_firmness>
</kactus2:kts_attributes>
</kactus2:extensions>
</spirit:vendorExtensions>
</spirit:component>