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--Nama file : count5x.fsm
--Deskripsi : counter 5 bit
--Author    : Mas Adit
--Tanggal  : 31 Agustus 2001

entity count5x is
port (
        clk : in bit;
        rst : in bit;
       q : out bit_vector(4 downto 0);
       vdd : in bit;
       vss : in bit
      );
end count5x;

architecture STATE_MACHINE of count5x is

type STATE_TYPE IS (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, S31);

-- pragma CLOCK clk
-- pragma CURRENT_STATE CURRENT_STATE
-- pragma NEXT_STATE NEXT_STATE

signal CURRENT_STATE, NEXT_STATE: STATE_TYPE;

begin
  process ( CURRENT_STATE, rst )
    begin
      if ( rst = '1' ) then
          NEXT_STATE <= S0;
          q <= "00000";
      else
          case CURRENT_STATE IS
             when S0 =>
                q <= "00000";
                NEXT_STATE <= S1;
         when S1 =>
                q <= "00001";
                NEXT_STATE <= S2;
             when S2 =>
                q <= "00010";
                NEXT_STATE <= S3;
         when S3 =>
                q <= "00011";
                NEXT_STATE <= S4;
             when S4 =>
                q <= "00100";
                NEXT_STATE <= S5;
             when S5 =>
                q <= "00101";
                NEXT_STATE <= S6;
             when S6 =>
                q <= "00110";
                NEXT_STATE <= S7;
             when S7 =>
                q <= "00111";
                NEXT_STATE <= S8;
             when S8 =>
                q <= "01000";
                NEXT_STATE <= S9;
             when S9 =>
                q <= "01001";
                NEXT_STATE <= S10;
             when S10 =>
                q <= "01010";
                NEXT_STATE <= S11;
         when S11 =>
                q <= "01011";
                NEXT_STATE <= S12;
         when S12 =>
                q <= "01100";
                NEXT_STATE <= S13;
         when S13 =>
                q <= "01101";
                NEXT_STATE <= S14;
             when S14 =>
                q <= "01110";
                NEXT_STATE <= S15;
             when S15 =>
                q <= "01111";
                NEXT_STATE <= S16;
             when S16 =>
                q <= "10000";
                NEXT_STATE <= S17;
             when S17 =>
                q <= "10001";
                NEXT_STATE <= S18;
             when S18 =>
                q <= "10010";
                NEXT_STATE <= S19;
             when S19 =>
                q <= "10011";
                NEXT_STATE <= S20;
             when S20 =>
                q <= "10100";
                NEXT_STATE <= S21;
         when S21 =>
                q <= "10101";
                NEXT_STATE <= S22;
         when S22 =>
                q <= "10110";
                NEXT_STATE <= S23;
         when S23 =>
                q <= "10111";
                NEXT_STATE <= S24;
             when S24 =>
                q <= "11000";
                NEXT_STATE <= S25;
             when S25 =>
                q <= "11001";
                NEXT_STATE <= S26;
             when S26 =>
                q <= "11010";
                NEXT_STATE <= S27;
             when S27 =>
                q <= "11011";
                NEXT_STATE <= S28;
             when S28 =>
                q <= "11100";
                NEXT_STATE <= S29;
             when S29 =>
                q <= "11101";
                NEXT_STATE <= S30;
              when S30 =>
                q <= "11110";
                NEXT_STATE <= S31;
         when S31 =>
                q <= "11111";
                NEXT_STATE <= S0;
             when OTHERS =>
                assert ( '1' )
                report "Illegal State";

          end case;
      end if;
end process;

process (clk)
  begin
    if ((clk = '1') and not (clk'STABLE)) then
         CURRENT_STATE <= NEXT_STATE;
    end if;
end process;

end STATE_MACHINE;