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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [byteNegator.v] - Rev 3
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`include "timescale.v" `include "defines.v" module byteNegator (byteIn, byteN, byteOut); input [7:0] byteIn; input byteN; output [7:0] byteOut; reg [7:0] byteOut; always @ (byteIn or byteN) begin if (byteN) begin byteOut = ~ byteIn; end else begin byteOut = byteIn; end end endmodule
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