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https://opencores.org/ocsvn/instruction_list_pipelined_processor_with_peripherals/instruction_list_pipelined_processor_with_peripherals/trunk
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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [ramByte.v] - Rev 3
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`include "timescale.v" `include "defines.v" module byteRam (clk, reset, byteRamEn, byteRamRw, byteRamIn, byteRamAddr, byteRamOut); input clk, reset, byteRamEn, byteRamRw; input [`byteRamLen-1:0] byteRamIn; input [`byteRamAddrLen-1:0] byteRamAddr; output [`byteRamLen-1:0] byteRamOut; reg [`byteRamLen-1:0] byteRam [`byteRamDepth-1:0]; reg [`byteRamLen-1:0] byteRamOut; always @ (posedge clk or posedge reset) begin if (reset) begin byteRamOut = `byteRamLen'b0; $write (" module byteRam is reset "); end else begin if (byteRamEn) begin if (byteRamRw) // read operation begin byteRamOut = byteRam[byteRamAddr]; $write (" reading byte RAM : module byteRam "); end else // write operation begin byteRam[byteRamAddr] = byteRamIn; $write (" writing to byte RAM : module byteRam "); end end else // if Enable = 0 begin byteRamOut = `byteRamLen'bz; end end // end else of reset end // end always endmodule
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