Subversion Repositories loadbalancer

-- Quartus II VHDL Template
-- Simple Dual-Port RAM with different read/write addresses but
-- single read/write clock
 
library ieee;
use ieee.std_logic_1164.all;
 
entity ram_256x48 is
 
	generic 
	(
		DATA_WIDTH : natural := 48;
		ADDR_WIDTH : natural := 12
	);
 
	port 
	(
		clk		: in std_logic;
		raddr	: in natural range 0 to 2**ADDR_WIDTH - 1;
		waddr	: in natural range 0 to 2**ADDR_WIDTH - 1;
		data	: in std_logic_vector((DATA_WIDTH-1) downto 0);
		we		: in std_logic := '1';
		q		: out std_logic_vector((DATA_WIDTH -1) downto 0)
	);
 
end ram_256x48;
 
architecture rtl of ram_256x48 is
 
	-- Build a 2-D array type for the RAM
	subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
	type memory_t is array(2**ADDR_WIDTH - 1 downto 0) of word_t;
 
	-- Declare the RAM signal.	
	signal ram : memory_t;
 
begin
 
	process(clk)
	begin
	if(rising_edge(clk)) then 
		if(we = '1') then
			ram(waddr) <= data;
		end if;
 
		-- On a read during a write to the same address, the read will
		-- return the OLD data at the address
		q <= ram(raddr);
	end if;
 
	end process;
 
end rtl;