Subversion Repositories mblite

Design: core
Description: The memory organization is as follows
core
|
`- imem
|
`- dmem

The dmem output is tied to the testbench for debugging
purposes.

The memory is preloaded with the hello world program

- MAKE SURE THE SIMULATOR IS SET TO TIME RESOLUTION OF 1 PS
- REPLACE mblite_soc_*.vhd WITH THE GENERATED VHDL NETLIST
- OPTIONALLY LOAD THE STANDARD DELAY FORMAT FILE IN MODELSIM
- THE TOOL mblite/sw/util/bin2rom CAN BE USED TO GENERATE
  THE INTIALIZATION ASSIGNMENT FROM A BINARY FORMAT