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[/] [mblite/] [trunk/] [designs/] [core_syn/] [sram_4en_init.vhd] - Rev 7

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----------------------------------------------------------------------------------------------
--
--      Input file         : sram_4en_init.vhd
--      Design name        : sram_4en_init
--      Author             : Tamar Kranenburg
--      Company            : Delft University of Technology
--                         : Faculty EEMCS, Department ME&CE
--                         : Systems and Circuits group
--
--      Description        : Single Port Synchronous Random Access Memory with 4 write enable
--                           ports.
--                           Initialized with hello world program
--
----------------------------------------------------------------------------------------------
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
 
LIBRARY mblite;
USE mblite.std_Pkg.ALL;
 
ENTITY sram_4en_init IS GENERIC
(
    WIDTH : integer := 32;
    SIZE  : integer := 11
);
PORT
(
    dat_o                   : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
    dat_i                   : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
    adr_i                   : IN std_logic_vector(SIZE - 1 DOWNTO 0);
    wre_i                   : IN std_logic_vector(3 DOWNTO 0);
    ena_i                   : IN std_logic;
    clk_i                   : IN std_logic
);
END sram_4en_init;
 
ARCHITECTURE arch OF sram_4en_init IS
  TYPE ram_type IS array (0 TO 2 ** SIZE - 1) OF std_logic_vector(WIDTH - 1 DOWNTO 0);
  SIGNAL ram : ram_type := (
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    X"B8080730",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
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    X"30630004",X"B0000000",X"30600000",X"BC030010",X"30A01020",X"99FC1800",X"80000000",X"30600001",
    X"F0601028",X"E9E10000",X"B60F0008",X"3021001C",X"B0000000",X"30600000",X"3021FFE4",X"F9E10000",
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    SIGNAL di0, di1, di2, di3 : std_logic_vector(WIDTH/4 - 1 DOWNTO 0);
BEGIN
    process(wre_i, dat_i, adr_i)
    begin
       if wre_i(0) = '1' then
          di0 <= dat_i(WIDTH/4 - 1 DOWNTO 0);
       else
          di0 <= ram(my_conv_integer(adr_i))(WIDTH/4 - 1 DOWNTO 0);
       end if;
 
       if wre_i(1) = '1' then
          di1 <= dat_i(WIDTH/2 - 1 DOWNTO WIDTH/4);
       else
          di1 <= ram(my_conv_integer(adr_i))(WIDTH/2 - 1 DOWNTO WIDTH/4);
       end if;
 
       if wre_i(2) = '1' then
          di2 <= dat_i(3*WIDTH/4 - 1 DOWNTO WIDTH/2);
       else
          di2 <= ram(my_conv_integer(adr_i))(3*WIDTH/4 - 1 DOWNTO WIDTH/2);
       end if;
 
       if wre_i(3) = '1' then
          di3 <= dat_i(WIDTH-1 DOWNTO 3*WIDTH/4);
       else
          di3 <= ram(my_conv_integer(adr_i))(WIDTH-1 DOWNTO 3*WIDTH/4);
       end if;
    end process;
 
    process(clk_i)
    begin
       if rising_edge(clk_i) then
          if (ena_i = '1') then
             ram(my_conv_integer(adr_i)) <= di3 & di2 & di1 & di0;
          end if;
          dat_o <= ram(my_conv_integer(adr_i));
       end if;
    end process;
END arch;

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