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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-digilent-xc3s1000/] [testbench.vhd] - Rev 2
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----------------------------------------------------------------------------- -- LEON3 Demonstration design test bench -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library gaisler; use gaisler.libdcom.all; use gaisler.sim.all; library techmap; use techmap.gencomp.all; use work.debug.all; use work.config.all; -- configuration entity testbench is generic ( fabtech : integer := CFG_FABTECH; memtech : integer := CFG_MEMTECH; padtech : integer := CFG_PADTECH; clktech : integer := CFG_CLKTECH; disas : integer := CFG_DISAS; -- Enable disassembly to console dbguart : integer := CFG_DUART; -- Print UART on console pclow : integer := CFG_PCLOW; clkperiod : integer := 20; -- system clock period romwidth : integer := 32; -- rom data width (8/32) romdepth : integer := 16; -- rom address depth sramwidth : integer := 32; -- ram data width (8/16/32) sramdepth : integer := 18; -- ram address depth srambanks : integer := 2 -- number of ram banks ); end; architecture behav of testbench is constant promfile : string := "prom.srec"; -- rom contents constant sramfile : string := "sram.srec"; -- ram contents constant sdramfile : string := "sdram.srec"; -- sdram contents signal clk : std_logic := '0'; signal Rst : std_logic := '0'; -- Reset constant ct : integer := clkperiod/2; signal address : std_logic_vector(19 downto 0); signal data : std_logic_vector(31 downto 0); signal mben : std_logic_vector(3 downto 0); signal pio : std_logic_vector(17 downto 0); signal ramsn : std_logic_vector(1 downto 0); signal oen : std_ulogic; signal writen : std_ulogic; signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic; signal dsurst : std_ulogic; signal GND : std_ulogic := '0'; signal VCC : std_ulogic := '1'; signal NC : std_ulogic := 'Z'; signal clk2 : std_ulogic := '1'; signal txd1, rxd1 : std_logic; signal txd2, rxd2 : std_logic; signal errorn : std_logic; signal ps2clk : std_logic; signal ps2data : std_logic; signal vid_hsync : std_ulogic; signal vid_vsync : std_ulogic; signal vid_r : std_logic; signal vid_g : std_logic; signal vid_b : std_logic; signal switch : std_logic_vector(7 downto 0); -- switches signal button : std_logic_vector(2 downto 0); constant lresp : boolean := false; begin -- clock and reset clk <= not clk after ct * 1 ns; rst <= dsurst; dsuen <= '1'; dsubre <= '0'; rxd1 <= 'H'; ps2clk <= 'H'; ps2data <= 'H'; pio(4) <= pio(5); pio(1) <= pio(2); pio <= (others => 'H'); address(1 downto 0) <= "00"; cpu : entity work.leon3mp generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow) port map (rst, clk, errorn, address(19 downto 2), data, ramsn, mben, oen, writen, dsubre, dsuact, txd1, rxd1, pio, --switch, button, ps2clk, ps2data, vid_hsync, vid_vsync, vid_r, vid_g, vid_b ); sram0 : for i in 0 to 1 generate sr0 : sram16 generic map (index => i*2, abits => 18, fname => sdramfile) port map (address(19 downto 2), data(31-i*16 downto 16-i*16), mben(i*2), mben(i*2+1), ramsn(i), writen, oen); end generate; iuerr : process begin wait for 5000 ns; if to_x01(errorn) = '0' then wait on errorn; end if; assert (to_x01(errorn) = '0') report "*** IU in error mode, simulation halted ***" severity failure ; end process; data <= buskeep(data), (others => 'H') after 250 ns; dsucom : process procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is variable w32 : std_logic_vector(31 downto 0); variable c8 : std_logic_vector(7 downto 0); constant txp : time := 320 * 1 ns; begin dsutx <= '1'; dsurst <= '1'; wait for 2500 ns; dsurst <= '0'; wait; wait for 5000 ns; txc(dsutx, 16#55#, txp); -- sync uart txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp); txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp); wait for 25000 ns; txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp); txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp); txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp); txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp); txc(dsutx, 16#80#, txp); txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp); wait; txc(dsutx, 16#c0#, txp); txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp); txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp); txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp); txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp); txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp); txc(dsutx, 16#80#, txp); txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp); rxi(dsurx, w32, txp, lresp); txc(dsutx, 16#a0#, txp); txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp); rxi(dsurx, w32, txp, lresp); end; begin dsucfg(txd2, rxd2); wait; end process; end ;