URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk
Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-gr-xc3s-1500/] [mips.txt] - Rev 2

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Scanning libraries
  grlib: stdlib util sparc modgen amba
  unisim: vcomponents simprims
  dw02: comp
  synplify: sim
  techmap: gencomp inferred dw02 unisim maps
  spw: comp wrapper
  eth: comp core wrapper
  opencores: occomp can i2c spi ata ac97
  gaisler: arith memctrl leon3 can misc net uart sim jtag greth spacewire usb ata vlog
  esa: memoryctrl
  micron: sdram
  work: debug
testbench.mpf
leon3mp.xst
rm -rf xst
xst -ifn compile.xst
Release 11.1 - xst L.33 (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/grlib/stdlib/version.vhd" in Library grlib.
Package <version> compiled.


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.14 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/grlib/stdlib/stdlib.vhd" in Library grlib.
Package <stdlib> compiled.
WARNING:HDLParsers:3534 - "../../lib/grlib/stdlib/stdlib.vhd" Line 186. In the function *, not all control paths contain a return statement.
WARNING:HDLParsers:3534 - "../../lib/grlib/stdlib/stdlib.vhd" Line 200. In the function signed_mul, not all control paths contain a return statement.
WARNING:HDLParsers:3534 - "../../lib/grlib/stdlib/stdlib.vhd" Line 216. In the function +, not all control paths contain a return statement.
WARNING:HDLParsers:3534 - "../../lib/grlib/stdlib/stdlib.vhd" Line 227. In the function +, not all control paths contain a return statement.
WARNING:HDLParsers:3534 - "../../lib/grlib/stdlib/stdlib.vhd" Line 238. In the function +, not all control paths contain a return statement.
WARNING:HDLParsers:3534 - "../../lib/grlib/stdlib/stdlib.vhd" Line 251. In the function +, not all control paths contain a return statement.
WARNING:HDLParsers:3534 - "../../lib/grlib/stdlib/stdlib.vhd" Line 267. In the function -, not all control paths contain a return statement.
WARNING:HDLParsers:3534 - "../../lib/grlib/stdlib/stdlib.vhd" Line 278. In the function -, not all control paths contain a return statement.
WARNING:HDLParsers:3534 - "../../lib/grlib/stdlib/stdlib.vhd" Line 289. In the function -, not all control paths contain a return statement.
WARNING:HDLParsers:3534 - "../../lib/grlib/stdlib/stdlib.vhd" Line 302. In the function -, not all control paths contain a return statement.
Package body <stdlib> compiled.


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.19 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/grlib/sparc/sparc.vhd" in Library grlib.
Package <sparc> compiled.


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.20 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/grlib/modgen/multlib.vhd" in Library grlib.
Package <multlib> compiled.


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.22 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/grlib/modgen/leaves.vhd" in Library grlib.
Package <blocks> compiled.
Entity <FLIPFLOP> compiled.
Entity <FLIPFLOP> (Architecture <FLIPFLOP>) compiled.
Entity <PP_LOW> compiled.
Entity <PP_LOW> (Architecture <PP_LOW>) compiled.
Entity <PP_MIDDLE> compiled.
Entity <PP_MIDDLE> (Architecture <PP_MIDDLE>) compiled.
Entity <PP_HIGH> compiled.
Entity <PP_HIGH> (Architecture <PP_HIGH>) compiled.
Entity <R_GATE> compiled.
Entity <R_GATE> (Architecture <R_GATE>) compiled.
Entity <DECODER> compiled.
Entity <DECODER> (Architecture <DECODER>) compiled.
Entity <FULL_ADDER> compiled.
Entity <FULL_ADDER> (Architecture <FULL_ADDER>) compiled.
Entity <HALF_ADDER> compiled.
Entity <HALF_ADDER> (Architecture <HALF_ADDER>) compiled.
Entity <INVBLOCK> compiled.
Entity <INVBLOCK> (Architecture <INVBLOCK_regular>) compiled.
Entity <XXOR1> compiled.
Entity <XXOR1> (Architecture <XXOR_regular>) compiled.
Entity <BLOCK0> compiled.
Entity <BLOCK0> (Architecture <BLOCK0_regular>) compiled.
Entity <BLOCK1> compiled.
Entity <BLOCK1> (Architecture <BLOCK1_regular>) compiled.
Entity <BLOCK2> compiled.
Entity <BLOCK2> (Architecture <BLOCK2_regular>) compiled.
Entity <BLOCK1A> compiled.
Entity <BLOCK1A> (Architecture <BLOCK1A_regular>) compiled.
Entity <BLOCK2A> compiled.
Entity <BLOCK2A> (Architecture <BLOCK2A_regular>) compiled.
Entity <PRESTAGE_64> compiled.
Entity <PRESTAGE_64> (Architecture <PRESTAGE>) compiled.
Entity <DBLC_0_64> compiled.
Entity <DBLC_0_64> (Architecture <DBLC_0>) compiled.
Entity <DBLC_1_64> compiled.
Entity <DBLC_1_64> (Architecture <DBLC_1>) compiled.
Entity <DBLC_2_64> compiled.
Entity <DBLC_2_64> (Architecture <DBLC_2>) compiled.
Entity <DBLC_3_64> compiled.
Entity <DBLC_3_64> (Architecture <DBLC_3>) compiled.
Entity <DBLC_4_64> compiled.
Entity <DBLC_4_64> (Architecture <DBLC_4>) compiled.
Entity <DBLC_5_64> compiled.
Entity <DBLC_5_64> (Architecture <DBLC_5>) compiled.
Entity <XORSTAGE_64> compiled.
Entity <XORSTAGE_64> (Architecture <XORSTAGE>) compiled.
Entity <DBLCTREE_64> compiled.
Entity <DBLCTREE_64> (Architecture <DBLCTREE>) compiled.
Entity <DBLCADDER_64_64> compiled.
Entity <DBLCADDER_64_64> (Architecture <DBLCADDER>) compiled.
Entity <XXOR2> compiled.
Entity <XXOR2> (Architecture <XXOR_true>) compiled.
Entity <DBLC_0_32> compiled.
Entity <DBLC_0_32> (Architecture <DBLC_0>) compiled.
Entity <DBLC_1_32> compiled.
Entity <DBLC_1_32> (Architecture <DBLC_1>) compiled.
Entity <DBLC_2_32> compiled.
Entity <DBLC_2_32> (Architecture <DBLC_2>) compiled.
Entity <DBLC_3_32> compiled.
Entity <DBLC_3_32> (Architecture <DBLC_3>) compiled.
Entity <DBLC_4_32> compiled.
Entity <DBLC_4_32> (Architecture <DBLC_4>) compiled.
Entity <XORSTAGE_32> compiled.
Entity <XORSTAGE_32> (Architecture <XORSTAGE>) compiled.
Entity <PRESTAGE_32> compiled.
Entity <PRESTAGE_32> (Architecture <PRESTAGE>) compiled.
Entity <DBLCTREE_32> compiled.
Entity <DBLCTREE_32> (Architecture <DBLCTREE>) compiled.
Entity <DBLCADDER_32_32> compiled.
Entity <DBLCADDER_32_32> (Architecture <DBLCADDER>) compiled.
Entity <PRESTAGE_128> compiled.
Entity <PRESTAGE_128> (Architecture <PRESTAGE>) compiled.
Entity <DBLC_0_128> compiled.
Entity <DBLC_0_128> (Architecture <DBLC_0>) compiled.
Entity <DBLC_1_128> compiled.
Entity <DBLC_1_128> (Architecture <DBLC_1>) compiled.
Entity <DBLC_2_128> compiled.
Entity <DBLC_2_128> (Architecture <DBLC_2>) compiled.
Entity <DBLC_3_128> compiled.
Entity <DBLC_3_128> (Architecture <DBLC_3>) compiled.
Entity <DBLC_4_128> compiled.
Entity <DBLC_4_128> (Architecture <DBLC_4>) compiled.
Entity <DBLC_5_128> compiled.
Entity <DBLC_5_128> (Architecture <DBLC_5>) compiled.
Entity <DBLC_6_128> compiled.
Entity <DBLC_6_128> (Architecture <DBLC_6>) compiled.
Entity <XORSTAGE_128> compiled.
Entity <XORSTAGE_128> (Architecture <XORSTAGE>) compiled.
Entity <DBLCTREE_128> compiled.
Entity <DBLCTREE_128> (Architecture <DBLCTREE>) compiled.
Entity <DBLCADDER_128_128> compiled.
Entity <DBLCADDER_128_128> (Architecture <DBLCADDER>) compiled.
Entity <BOOTHCODER_18_18> compiled.
Entity <BOOTHCODER_18_18> (Architecture <BOOTHCODER>) compiled.
Entity <WALLACE_18_18> compiled.
Entity <WALLACE_18_18> (Architecture <WALLACE>) compiled.
Entity <MULTIPLIER_18_18> compiled.
Entity <MULTIPLIER_18_18> (Architecture <MULTIPLIER>) compiled.
Entity <BOOTHCODER_34_10> compiled.
Entity <BOOTHCODER_34_10> (Architecture <BOOTHCODER>) compiled.
Entity <WALLACE_34_10> compiled.
Entity <WALLACE_34_10> (Architecture <WALLACE>) compiled.
Entity <MULTIPLIER_34_10> compiled.
Entity <MULTIPLIER_34_10> (Architecture <MULTIPLIER>) compiled.
Entity <MUL_33_9> compiled.
Entity <MUL_33_9> (Architecture <A>) compiled.
Entity <BOOTHCODER_34_18> compiled.
Entity <BOOTHCODER_34_18> (Architecture <BOOTHCODER>) compiled.
Entity <WALLACE_34_18> compiled.
Entity <WALLACE_34_18> (Architecture <WALLACE>) compiled.
Entity <MULTIPLIER_34_18> compiled.
Entity <MULTIPLIER_34_18> (Architecture <MULTIPLIER>) compiled.
Entity <MUL_33_17> compiled.
Entity <MUL_33_17> (Architecture <A>) compiled.
Entity <BOOTHCODER_34_34> compiled.
Entity <BOOTHCODER_34_34> (Architecture <BOOTHCODER>) compiled.
Entity <WALLACE_34_34> compiled.
Entity <WALLACE_34_34> (Architecture <WALLACE>) compiled.
Entity <MULTIPLIER_34_34> compiled.
Entity <MULTIPLIER_34_34> (Architecture <MULTIPLIER>) compiled.
Entity <MUL_33_33> compiled.
Entity <MUL_33_33> (Architecture <A>) compiled.
Entity <ADD32> compiled.
Entity <ADD32> (Architecture <A>) compiled.
Entity <MUL_17_17> compiled.
Entity <MUL_17_17> (Architecture <A>) compiled.


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.77 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/grlib/amba/amba.vhd" in Library grlib.
Package <amba> compiled.
Package body <amba> compiled.


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.83 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/grlib/amba/devices.vhd" in Library grlib.
Package <devices> compiled.


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.87 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/grlib/amba/defmst.vhd" in Library grlib.
Entity <ahbdefmst> compiled.
Entity <ahbdefmst> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.91 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/grlib/amba/apbctrl.vhd" in Library grlib.
Entity <apbctrl> compiled.
Entity <apbctrl> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.95 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/grlib/amba/ahbctrl.vhd" in Library grlib.
Entity <ahbctrl> compiled.
Entity <ahbctrl> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 1.05 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/grlib/amba/dma2ahb_pkg.vhd" in Library grlib.
Package <DMA2AHB_Package> compiled.


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 1.08 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/grlib/amba/dma2ahb.vhd" in Library grlib.
Entity <DMA2AHB> compiled.
Entity <DMA2AHB> (Architecture <RTL>) compiled.


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 1.12 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/gencomp/gencomp.vhd" in Library techmap.
Package <gencomp> compiled.


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 1.19 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/gencomp/netcomp.vhd" in Library techmap.
Package <netcomp> compiled.


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 1.25 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/inferred/memory_inferred.vhd" in Library techmap.
Entity <generic_syncram> compiled.
Entity <generic_syncram> (Architecture <behavioral>) compiled.
Entity <generic_syncram_2p> compiled.
Entity <generic_syncram_2p> (Architecture <behav>) compiled.
Entity <generic_regfile_3p> compiled.
Entity <generic_regfile_3p> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 1.30 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/inferred/ddr_inferred.vhd" in Library techmap.
Entity <gen_iddr_reg> compiled.
Entity <gen_iddr_reg> (Architecture <rtl>) compiled.
Entity <gen_oddr_reg> compiled.
Entity <gen_oddr_reg> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 1.33 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/inferred/mul_inferred.vhd" in Library techmap.
Entity <gen_mul_61x61> compiled.
Entity <gen_mul_61x61> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 1.36 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/inferred/ddr_phy_inferred.vhd" in Library techmap.
Entity <gen_ddr_phy_oreg> compiled.
Entity <gen_ddr_phy_oreg> (Architecture <rtl>) compiled.
Entity <gen_ddr_phy_ireg> compiled.
Entity <gen_ddr_phy_ireg> (Architecture <rtl>) compiled.
Entity <gen_ddr_phy_reg> compiled.
Entity <gen_ddr_phy_reg> (Architecture <rtl>) compiled.
Entity <generic_ddr_phy> compiled.
Entity <generic_ddr_phy> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 1.42 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/unisim/memory_unisim.vhd" in Library techmap.
Entity <virtex_syncram> compiled.
Entity <virtex_syncram> (Architecture <behav>) compiled.
Entity <virtex_syncram_dp> compiled.
Entity <virtex_syncram_dp> (Architecture <behav>) compiled.
Entity <virtex2_syncram> compiled.
Entity <virtex2_syncram> (Architecture <behav>) compiled.
Entity <virtex2_syncram_dp> compiled.
Entity <virtex2_syncram_dp> (Architecture <behav>) compiled.
Entity <virtex2_syncram_2p> compiled.
Entity <virtex2_syncram_2p> (Architecture <behav>) compiled.
Entity <virtex2_syncram64> compiled.
Entity <virtex2_syncram64> (Architecture <behav>) compiled.


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 1.50 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/unisim/buffer_unisim.vhd" in Library techmap.
Entity <clkbuf_xilinx> compiled.
Entity <clkbuf_xilinx> (Architecture <rtl>) compiled.
Entity <clkmux_xilinx> compiled.
Entity <clkmux_xilinx> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 1.55 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/unisim/pads_unisim.vhd" in Library techmap.
Entity <virtex_inpad> compiled.
Entity <virtex_inpad> (Architecture <rtl>) compiled.
Entity <virtex_iopad> compiled.
Entity <virtex_iopad> (Architecture <rtl>) compiled.
Entity <virtex_outpad> compiled.
Entity <virtex_outpad> (Architecture <rtl>) compiled.
Entity <virtex_toutpad> compiled.
Entity <virtex_toutpad> (Architecture <rtl>) compiled.
Entity <virtex_skew_outpad> compiled.
Entity <virtex_skew_outpad> (Architecture <rtl>) compiled.
Entity <virtex_clkpad> compiled.
Entity <virtex_clkpad> (Architecture <rtl>) compiled.
Entity <virtex_outpad_ds> compiled.
Entity <virtex_outpad_ds> (Architecture <rtl>) compiled.
Entity <virtex_inpad_ds> compiled.
Entity <virtex_inpad_ds> (Architecture <rtl>) compiled.
Entity <virtex_clkpad_ds> compiled.
Entity <virtex_clkpad_ds> (Architecture <rtl>) compiled.
Entity <virtex4_inpad_ds> compiled.
Entity <virtex4_inpad_ds> (Architecture <rtl>) compiled.
Entity <virtex4_clkpad_ds> compiled.
Entity <virtex4_clkpad_ds> (Architecture <rtl>) compiled.
Entity <virtex5_iopad_ds> compiled.
Entity <virtex5_iopad_ds> (Architecture <rtl>) compiled.
Entity <virtex5_outpad_ds> compiled.
Entity <virtex5_outpad_ds> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 2.00 secs
Total CPU time to Xst completion: 1.62 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/unisim/clkgen_unisim.vhd" in Library techmap.
Entity <clkgen_virtex2> compiled.
Entity <clkgen_virtex2> (Architecture <struct>) compiled.
Entity <clkgen_virtex> compiled.
Entity <clkgen_virtex> (Architecture <rtl>) compiled.
Entity <clkmul_virtex2> compiled.
Entity <clkmul_virtex2> (Architecture <struct>) compiled.
Entity <clkgen_spartan3> compiled.
Entity <clkgen_spartan3> (Architecture <struct>) compiled.
Entity <clkgen_virtex5> compiled.
Entity <clkgen_virtex5> (Architecture <struct>) compiled.
Entity <clkand_unisim> compiled.
Entity <clkand_unisim> (Architecture <rtl>) compiled.
Entity <clkmux_unisim> compiled.
Entity <clkmux_unisim> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 2.00 secs
Total CPU time to Xst completion: 1.69 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/unisim/tap_unisim.vhd" in Library techmap.
Entity <virtex_tap> compiled.
Entity <virtex_tap> (Architecture <rtl>) compiled.
Entity <virtex2_tap> compiled.
Entity <virtex2_tap> (Architecture <rtl>) compiled.
Entity <spartan3_tap> compiled.
Entity <spartan3_tap> (Architecture <rtl>) compiled.
Entity <virtex4_tap> compiled.
Entity <virtex4_tap> (Architecture <rtl>) compiled.
Entity <virtex5_tap> compiled.
Entity <virtex5_tap> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 2.00 secs
Total CPU time to Xst completion: 1.73 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/unisim/ddr_unisim.vhd" in Library techmap.
Entity <unisim_iddr_reg> compiled.
Entity <unisim_iddr_reg> (Architecture <rtl>) compiled.
Entity <unisim_oddr_reg> compiled.
Entity <unisim_oddr_reg> (Architecture <rtl>) compiled.
Entity <oddrv2> compiled.
Entity <oddrv2> (Architecture <rtl>) compiled.
Entity <oddrc3e> compiled.
Entity <oddrc3e> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 2.00 secs
Total CPU time to Xst completion: 1.79 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/unisim/ddr_phy_unisim.vhd" in Library techmap.
Entity <virtex4_ddr_phy> compiled.
Entity <virtex4_ddr_phy> (Architecture <rtl>) compiled.
Entity <virtex2_ddr_phy> compiled.
Entity <virtex2_ddr_phy> (Architecture <rtl>) compiled.
Entity <spartan3e_ddr_phy> compiled.
Entity <spartan3e_ddr_phy> (Architecture <rtl>) compiled.
Entity <virtex5_ddr2_phy> compiled.
Entity <virtex5_ddr2_phy> (Architecture <rtl>) compiled.
Entity <spartan3a_ddr2_phy> compiled.
Entity <spartan3a_ddr2_phy> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 2.00 secs
Total CPU time to Xst completion: 1.92 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/unisim/grspwc_unisim.vhd" in Library techmap.
Entity <grspwc_unisim> compiled.
Entity <grspwc_unisim> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 2.00 secs
Total CPU time to Xst completion: 1.97 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/unisim/grfpw_unisim.vhd" in Library techmap.
Entity <grfpw_unisim> compiled.
Entity <grfpw_unisim> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 2.00 secs
Total CPU time to Xst completion: 2.03 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/unisim/grusbhc_unisimpkg.vhd" in Library techmap.
Package <grusbhc_unisimpkg> compiled.
Package body <grusbhc_unisimpkg> compiled.


Total REAL time to Xst completion: 2.00 secs
Total CPU time to Xst completion: 2.11 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/unisim/grusbhc_unisim.vhd" in Library techmap.
Entity <grusbhc_unisim> compiled.
Entity <grusbhc_unisim> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 2.00 secs
Total CPU time to Xst completion: 2.17 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/unisim/ssrctrl_unisim.vhd" in Library techmap.
Entity <ssrctrl_unisim> compiled.
Entity <ssrctrl_unisim_netlist> compiled.
Entity <ssrctrl_unisim_netlist> (Architecture <beh>) compiled.
Entity <ssrctrl_unisim> (Architecture <beh>) compiled.


Total REAL time to Xst completion: 2.00 secs
Total CPU time to Xst completion: 2.42 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/allclkgen.vhd" in Library techmap.
Package <allclkgen> compiled.


Total REAL time to Xst completion: 2.00 secs
Total CPU time to Xst completion: 2.48 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/allddr.vhd" in Library techmap.
Package <allddr> compiled.


Total REAL time to Xst completion: 2.00 secs
Total CPU time to Xst completion: 2.56 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/allmem.vhd" in Library techmap.
Package <allmem> compiled.


Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 2.62 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/allpads.vhd" in Library techmap.
Package <allpads> compiled.


Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 2.68 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/alltap.vhd" in Library techmap.
Package <alltap> compiled.


Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 2.75 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/clkgen.vhd" in Library techmap.
Entity <clkgen> compiled.
Entity <clkgen> (Architecture <struct>) compiled.


Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 2.81 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/clkmux.vhd" in Library techmap.
Entity <clkmux> compiled.
Entity <clkmux> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 2.89 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/clkand.vhd" in Library techmap.
Entity <clkand> compiled.
Entity <clkand> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 2.95 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/ddr_ireg.vhd" in Library techmap.
Entity <ddr_ireg> compiled.
Entity <ddr_ireg> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 3.01 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/ddr_oreg.vhd" in Library techmap.
Entity <ddr_oreg> compiled.
Entity <ddr_oreg> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 3.09 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/ddrphy.vhd" in Library techmap.
Entity <ddrphy> compiled.
Entity <ddrphy> (Architecture <rtl>) compiled.
Entity <ddr2phy> compiled.
Entity <ddr2phy> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 3.17 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/syncram.vhd" in Library techmap.
Entity <syncram> compiled.
Entity <syncram> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 3.23 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/syncram64.vhd" in Library techmap.
Entity <syncram64> compiled.
Entity <syncram64> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 3.31 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/syncram_2p.vhd" in Library techmap.
Entity <syncram_2p> compiled.
Entity <syncram_2p> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 3.37 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/syncram_dp.vhd" in Library techmap.
Entity <syncram_dp> compiled.
Entity <syncram_dp> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 3.45 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/syncfifo.vhd" in Library techmap.
Entity <syncfifo> compiled.
Entity <syncfifo> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 3.53 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/regfile_3p.vhd" in Library techmap.
Entity <regfile_3p> compiled.
Entity <regfile_3p> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 3.60 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/tap.vhd" in Library techmap.
Entity <tap> compiled.
Entity <tap> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 3.67 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/techbuf.vhd" in Library techmap.
Entity <techbuf> compiled.
Entity <techbuf> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 3.74 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/clkpad.vhd" in Library techmap.
Entity <clkpad> compiled.
Entity <clkpad> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 3.81 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/clkpad_ds.vhd" in Library techmap.
Entity <clkpad_ds> compiled.
Entity <clkpad_ds> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 3.88 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/inpad.vhd" in Library techmap.
Entity <inpad> compiled.
Entity <inpad> (Architecture <rtl>) compiled.
Entity <inpadv> compiled.
Entity <inpadv> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 3.96 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/inpad_ds.vhd" in Library techmap.
Entity <inpad_ds> compiled.
Entity <inpad_ds> (Architecture <rtl>) compiled.
Entity <inpad_dsv> compiled.
Entity <inpad_dsv> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 4.03 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/iodpad.vhd" in Library techmap.
Entity <iodpad> compiled.
Entity <iodpad> (Architecture <rtl>) compiled.
Entity <iodpadv> compiled.
Entity <iodpadv> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 4.10 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/iopad.vhd" in Library techmap.
Entity <iopad> compiled.
Entity <iopad> (Architecture <rtl>) compiled.
Entity <iopadv> compiled.
Entity <iopadv> (Architecture <rtl>) compiled.
Entity <iopadvv> compiled.
Entity <iopadvv> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 4.18 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/iopad_ds.vhd" in Library techmap.
Entity <iopad_ds> compiled.
Entity <iopad_ds> (Architecture <rtl>) compiled.
Entity <iopad_dsv> compiled.
Entity <iopad_dsv> (Architecture <rtl>) compiled.
Entity <iopad_dsvv> compiled.
Entity <iopad_dsvv> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 4.26 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/lvds_combo.vhd" in Library techmap.
Entity <lvds_combo> compiled.
Entity <lvds_combo> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 4.34 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/odpad.vhd" in Library techmap.
Entity <odpad> compiled.
Entity <odpad> (Architecture <rtl>) compiled.
Entity <odpadv> compiled.
Entity <odpadv> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 4.43 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/outpad.vhd" in Library techmap.
Entity <outpad> compiled.
Entity <outpad> (Architecture <rtl>) compiled.
Entity <outpadv> compiled.
Entity <outpadv> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 4.51 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/outpad_ds.vhd" in Library techmap.
Entity <outpad_ds> compiled.
Entity <outpad_ds> (Architecture <rtl>) compiled.
Entity <outpad_dsv> compiled.
Entity <outpad_dsv> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 4.59 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/toutpad.vhd" in Library techmap.
Entity <toutpad> compiled.
Entity <toutpad> (Architecture <rtl>) compiled.
Entity <toutpadv> compiled.
Entity <toutpadv> (Architecture <rtl>) compiled.
Entity <toutpadvv> compiled.
Entity <toutpadvv> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 4.67 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/skew_outpad.vhd" in Library techmap.
Entity <skew_outpad> compiled.
Entity <skew_outpad> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 4.74 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/grspwc_net.vhd" in Library techmap.
Entity <grspwc_net> compiled.
Entity <grspwc_net> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 4.84 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/grlfpw_net.vhd" in Library techmap.
Entity <grlfpw_net> compiled.
Entity <grlfpw_net> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 4.91 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/grfpw_net.vhd" in Library techmap.
Entity <grfpw_net> compiled.
Entity <grfpw_net> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 4.99 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/mul_61x61.vhd" in Library techmap.
Entity <mul_61x61> compiled.
Entity <mul_61x61> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 5.07 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/cpu_disas_net.vhd" in Library techmap.
Entity <cpu_disas_net> compiled.
Entity <cpu_disas_net> (Architecture <behav>) compiled.
Entity <fpu_disas_net> compiled.
Entity <fpu_disas_net> (Architecture <behav>) compiled.


Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 5.15 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/grusbhc_net.vhd" in Library techmap.
Entity <grusbhc_net> compiled.
Entity <grusbhc_net> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 5.26 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/ringosc.vhd" in Library techmap.
Entity <ringosc> compiled.
Entity <ringosc> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 5.34 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/techmap/maps/ssrctrl_net.vhd" in Library techmap.
Entity <ssrctrl_net> compiled.
Entity <ssrctrl_net> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 5.43 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/spw/comp/spwcomp.vhd" in Library spw.
Package <spwcomp> compiled.


Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 5.45 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/spw/wrapper/grspw_gen.vhd" in Library spw.
Entity <grspw_gen> compiled.
Entity <grspw_gen> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 5.52 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/eth/comp/ethcomp.vhd" in Library eth.
Package <ethcomp> compiled.


Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 5.55 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/eth/core/greth_pkg.vhd" in Library eth.
Package <grethpkg> compiled.
Package body <grethpkg> compiled.


Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 5.60 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/eth/core/eth_rstgen.vhd" in Library eth.
Entity <eth_rstgen> compiled.
Entity <eth_rstgen> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 5.63 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/eth/core/eth_ahb_mst.vhd" in Library eth.
Entity <eth_ahb_mst> compiled.
Entity <eth_ahb_mst> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 5.68 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/eth/core/greth_tx.vhd" in Library eth.
Entity <greth_tx> compiled.
Entity <greth_tx> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 5.74 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/eth/core/greth_rx.vhd" in Library eth.
Entity <greth_rx> compiled.
Entity <greth_rx> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 5.79 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/eth/core/grethc.vhd" in Library eth.
Entity <grethc> compiled.
Entity <grethc> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 6.02 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/eth/wrapper/greth_gen.vhd" in Library eth.
Entity <greth_gen> compiled.
Entity <greth_gen> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 6.10 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/eth/wrapper/greth_gbit_gen.vhd" in Library eth.
Entity <greth_gbit_gen> compiled.
Entity <greth_gbit_gen> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 6.18 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/opencores/occomp/occomp.vhd" in Library opencores.
Package <occomp> compiled.


Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 6.19 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/opencores/can/cancomp.vhd" in Library opencores.
Package <cancomp> compiled.


Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 6.21 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/opencores/can/can_top.vhd" in Library opencores.
Entity <can_acf> compiled.
Entity <can_acf> (Architecture <RTL>) compiled.
Entity <can_btl> compiled.
Entity <can_btl> (Architecture <RTL>) compiled.
Entity <can_fifo> compiled.
Entity <can_fifo> (Architecture <RTL>) compiled.
Entity <can_crc> compiled.
Entity <can_crc> (Architecture <RTL>) compiled.
Entity <can_ibo> compiled.
Entity <can_ibo> (Architecture <RTL>) compiled.
Entity <can_bsp> compiled.
Entity <can_bsp> (Architecture <RTL>) compiled.
Entity <can_register> compiled.
Entity <can_register> (Architecture <RTL>) compiled.
Entity <can_register_asyn> compiled.
Entity <can_register_asyn> (Architecture <RTL>) compiled.
Entity <can_register_asyn_syn> compiled.
Entity <can_register_asyn_syn> (Architecture <RTL>) compiled.
Entity <can_register_syn> compiled.
Entity <can_register_syn> (Architecture <RTL>) compiled.
Entity <can_registers> compiled.
Entity <can_registers> (Architecture <RTL>) compiled.
Entity <can_top> compiled.
Entity <can_top> (Architecture <RTL>) compiled.


Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 6.47 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/opencores/can/can_top_core_sync.vhd" in Library opencores.
Entity <can_btl_core_sync> compiled.
Entity <can_btl_core_sync> (Architecture <RTL>) compiled.
Entity <can_crc_core_sync> compiled.
Entity <can_crc_core_sync> (Architecture <RTL>) compiled.
Entity <can_ibo_core_sync> compiled.
Entity <can_ibo_core_sync> (Architecture <RTL>) compiled.
Entity <can_bsp_core_sync> compiled.
Entity <can_bsp_core_sync> (Architecture <RTL>) compiled.
Entity <can_top_core_sync> compiled.
Entity <can_top_core_sync> (Architecture <RTL>) compiled.


Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 6.63 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/opencores/i2c/i2c_master_bit_ctrl.vhd" in Library opencores.
Entity <i2c_master_bit_ctrl> compiled.
Entity <i2c_master_bit_ctrl> (Architecture <structural>) compiled.


Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 6.68 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/opencores/i2c/i2c_master_byte_ctrl.vhd" in Library opencores.
Entity <i2c_master_byte_ctrl> compiled.
Entity <i2c_master_byte_ctrl> (Architecture <structural>) compiled.


Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 6.72 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/opencores/i2c/i2coc.vhd" in Library opencores.
Package <i2coc> compiled.


Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 6.77 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "../../lib/opencores/spi/simple_spi_top.v" in library opencores
Module <fifo4> compiled
Module <simple_spi_top> compiled


Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 6.79 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/opencores/ata/ud_cnt.vhd" in Library opencores.
Entity <ud_cnt> compiled.
Entity <ud_cnt> (Architecture <structural>) compiled.


Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 6.83 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/opencores/ata/ro_cnt.vhd" in Library opencores.
Entity <ro_cnt> compiled.
Entity <ro_cnt> (Architecture <structural>) compiled.


Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 6.86 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/opencores/ata/atahost_dma_fifo.vhd" in Library opencores.
Entity <atahost_dma_fifo> compiled.
Entity <atahost_dma_fifo> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 6.94 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/opencores/ata/atahost_dma_actrl.vhd" in Library opencores.
Entity <atahost_dma_actrl> compiled.
Entity <atahost_dma_actrl> (Architecture <structural>) compiled.


Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 7.04 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/opencores/ata/atahost_dma_tctrl.vhd" in Library opencores.
Entity <atahost_dma_tctrl> compiled.
Entity <atahost_dma_tctrl> (Architecture <structural>) compiled.


Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 7.13 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/opencores/ata/atahost_pio_tctrl.vhd" in Library opencores.
Entity <atahost_pio_tctrl> compiled.
Entity <atahost_pio_tctrl> (Architecture <structural>) compiled.


Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 7.21 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/opencores/ata/atahost_pio_actrl.vhd" in Library opencores.
Entity <atahost_pio_actrl> compiled.
Entity <atahost_pio_actrl> (Architecture <structural>) compiled.


Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 7.30 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/opencores/ata/atahost_controller.vhd" in Library opencores.
Entity <atahost_controller> compiled.
Entity <atahost_controller> (Architecture <structural>) compiled.


Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 7.38 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/opencores/ata/atahost_pio_controller.vhd" in Library opencores.
Entity <atahost_pio_controller> compiled.
Entity <atahost_pio_controller> (Architecture <structural>) compiled.


Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 7.47 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/opencores/ata/ocidec2_controller.vhd" in Library opencores.
Entity <ocidec2_controller> compiled.
Entity <ocidec2_controller> (Architecture <structural>) compiled.


Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 7.55 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "../../lib/opencores/ac97/ac97_top.v" in library opencores
Module <ac97_cra> compiled
Module <ac97_dma_if> compiled
Module <ac97_dma_req> compiled
Module <ac97_fifo_ctrl> compiled
Module <ac97_in_fifo> compiled
Module <ac97_int> compiled
Module <ac97_out_fifo> compiled
Module <ac97_prc> compiled
Module <ac97_rf> compiled
Module <ac97_rst> compiled
Module <ac97_sin> compiled
Module <ac97_soc> compiled
Module <ac97_sout> compiled
Module <ac97_wb_if> compiled
Module <ac97_top> compiled


Total REAL time to Xst completion: 8.00 secs
Total CPU time to Xst completion: 7.61 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/arith/arith.vhd" in Library gaisler.
Package <arith> compiled.
Package body <arith> compiled.


Total REAL time to Xst completion: 8.00 secs
Total CPU time to Xst completion: 7.63 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/arith/mul32.vhd" in Library gaisler.
Entity <mul32> compiled.
Entity <mul32> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 8.00 secs
Total CPU time to Xst completion: 7.69 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/arith/div32.vhd" in Library gaisler.
Entity <div32> compiled.
Entity <div32> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 8.00 secs
Total CPU time to Xst completion: 7.72 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/memctrl/memctrl.vhd" in Library gaisler.
Package <memctrl> compiled.


Total REAL time to Xst completion: 8.00 secs
Total CPU time to Xst completion: 7.82 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/memctrl/sdctrl.vhd" in Library gaisler.
Entity <sdctrl> compiled.
Entity <sdctrl> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 8.00 secs
Total CPU time to Xst completion: 7.99 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/memctrl/sdmctrl.vhd" in Library gaisler.
Entity <sdmctrl> compiled.
Entity <sdmctrl> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 8.00 secs
Total CPU time to Xst completion: 8.14 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/memctrl/srctrl.vhd" in Library gaisler.
Entity <srctrl> compiled.
Entity <srctrl> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 8.00 secs
Total CPU time to Xst completion: 8.27 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/memctrl/spimctrl.vhd" in Library gaisler.
Entity <spimctrl> compiled.
Entity <spimctrl> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 8.00 secs
Total CPU time to Xst completion: 8.42 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/leon3.vhd" in Library gaisler.
Package <leon3> compiled.


Total REAL time to Xst completion: 8.00 secs
Total CPU time to Xst completion: 8.52 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/mmuconfig.vhd" in Library gaisler.
Package <mmuconfig> compiled.


Total REAL time to Xst completion: 9.00 secs
Total CPU time to Xst completion: 8.61 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/mmuiface.vhd" in Library gaisler.
Package <mmuiface> compiled.


Total REAL time to Xst completion: 9.00 secs
Total CPU time to Xst completion: 8.69 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/libmmu.vhd" in Library gaisler.
Package <libmmu> compiled.
Package body <libmmu> compiled.


Total REAL time to Xst completion: 9.00 secs
Total CPU time to Xst completion: 8.78 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/libiu.vhd" in Library gaisler.
Package <libiu> compiled.


Total REAL time to Xst completion: 9.00 secs
Total CPU time to Xst completion: 8.88 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/libcache.vhd" in Library gaisler.
Package <libcache> compiled.
Package body <libcache> compiled.


Total REAL time to Xst completion: 9.00 secs
Total CPU time to Xst completion: 9.03 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/libproc3.vhd" in Library gaisler.
Package <libproc3> compiled.


Total REAL time to Xst completion: 9.00 secs
Total CPU time to Xst completion: 9.14 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/cachemem.vhd" in Library gaisler.
Entity <cachemem> compiled.
Entity <cachemem> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 9.00 secs
Total CPU time to Xst completion: 9.30 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/mmu_icache.vhd" in Library gaisler.
Entity <mmu_icache> compiled.
Entity <mmu_icache> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 9.00 secs
Total CPU time to Xst completion: 9.50 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/mmu_dcache.vhd" in Library gaisler.
Entity <mmu_dcache> compiled.
Entity <mmu_dcache> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 10.00 secs
Total CPU time to Xst completion: 9.94 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/mmu_acache.vhd" in Library gaisler.
Entity <mmu_acache> compiled.
Entity <mmu_acache> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 10.00 secs
Total CPU time to Xst completion: 10.11 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/mmutlbcam.vhd" in Library gaisler.
Entity <mmutlbcam> compiled.
Entity <mmutlbcam> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 10.00 secs
Total CPU time to Xst completion: 10.23 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/mmulrue.vhd" in Library gaisler.
Entity <mmulrue> compiled.
Entity <mmulrue> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 10.00 secs
Total CPU time to Xst completion: 10.34 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/mmulru.vhd" in Library gaisler.
Entity <mmulru> compiled.
Entity <mmulru> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 10.00 secs
Total CPU time to Xst completion: 10.47 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/mmutlb.vhd" in Library gaisler.
Entity <mmutlb> compiled.
Entity <mmutlb> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 11.00 secs
Total CPU time to Xst completion: 10.65 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/mmutw.vhd" in Library gaisler.
Entity <mmutw> compiled.
Entity <mmutw> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 11.00 secs
Total CPU time to Xst completion: 10.78 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/mmu.vhd" in Library gaisler.
Entity <mmu> compiled.
Entity <mmu> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 11.00 secs
Total CPU time to Xst completion: 10.89 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/mmu_cache.vhd" in Library gaisler.
Entity <mmu_cache> compiled.
Entity <mmu_cache> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 11.00 secs
Total CPU time to Xst completion: 11.00 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/acache.vhd" in Library gaisler.
Entity <acache> compiled.
Entity <acache> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 11.00 secs
Total CPU time to Xst completion: 11.15 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/dcache.vhd" in Library gaisler.
Entity <dcache> compiled.
Entity <dcache> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 11.00 secs
Total CPU time to Xst completion: 11.44 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/icache.vhd" in Library gaisler.
Entity <icache> compiled.
Entity <icache> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 12.00 secs
Total CPU time to Xst completion: 11.62 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/cache.vhd" in Library gaisler.
Entity <cache> compiled.
Entity <cache> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 12.00 secs
Total CPU time to Xst completion: 11.73 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/cpu_disasx.vhd" in Library gaisler.
Entity <cpu_disasx> compiled.
Entity <cpu_disasx> (Architecture <behav>) compiled.


Total REAL time to Xst completion: 12.00 secs
Total CPU time to Xst completion: 11.81 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/grfpwx.vhd" in Library gaisler.
Entity <grfpwx> compiled.
Entity <grfpwx> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 12.00 secs
Total CPU time to Xst completion: 11.92 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/mfpwx.vhd" in Library gaisler.
Entity <mfpwx> compiled.
Entity <mfpwx> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 12.00 secs
Total CPU time to Xst completion: 12.01 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/grlfpwx.vhd" in Library gaisler.
Entity <grlfpwx> compiled.
Entity <grlfpwx> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 12.00 secs
Total CPU time to Xst completion: 12.12 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/tbufmem.vhd" in Library gaisler.
Entity <tbufmem> compiled.
Entity <tbufmem> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 12.00 secs
Total CPU time to Xst completion: 12.22 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/dsu3x.vhd" in Library gaisler.
Entity <dsu3x> compiled.
Entity <dsu3x> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 12.00 secs
Total CPU time to Xst completion: 12.42 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/dsu3.vhd" in Library gaisler.
Entity <dsu3> compiled.
Entity <dsu3> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 12.00 secs
Total CPU time to Xst completion: 12.53 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/proc3.vhd" in Library gaisler.
Entity <proc3> compiled.
Entity <proc3> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 13.00 secs
Total CPU time to Xst completion: 12.65 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/leon3s.vhd" in Library gaisler.
Entity <leon3s> compiled.
Entity <leon3s> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 13.00 secs
Total CPU time to Xst completion: 12.76 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/leon3cg.vhd" in Library gaisler.
Entity <leon3cg> compiled.
Entity <leon3cg> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 13.00 secs
Total CPU time to Xst completion: 12.89 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/irqmp.vhd" in Library gaisler.
Entity <irqmp> compiled.
Entity <irqmp> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 13.00 secs
Total CPU time to Xst completion: 13.04 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/grfpwxsh.vhd" in Library gaisler.
Entity <grfpwxsh> compiled.
Entity <grfpwxsh> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 13.00 secs
Total CPU time to Xst completion: 13.15 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/grfpushwx.vhd" in Library gaisler.
Entity <grfpushwx> compiled.
Entity <grfpushwx> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 13.00 secs
Total CPU time to Xst completion: 13.29 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/leon3sh.vhd" in Library gaisler.
Entity <leon3sh> compiled.
Entity <leon3sh> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 13.00 secs
Total CPU time to Xst completion: 13.42 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/my_mux.vhd" in Library gaisler.
Entity <my_mux> compiled.
Entity <my_mux> (Architecture <RTL>) compiled.


Total REAL time to Xst completion: 13.00 secs
Total CPU time to Xst completion: 13.51 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/leon3/top.vhd" in Library gaisler.
Entity <top> compiled.
Entity <top> (Architecture <Behavioral>) compiled.


Total REAL time to Xst completion: 14.00 secs
Total CPU time to Xst completion: 13.62 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/can/can.vhd" in Library gaisler.
Package <can> compiled.


Total REAL time to Xst completion: 14.00 secs
Total CPU time to Xst completion: 13.73 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/can/can_mod.vhd" in Library gaisler.
Entity <can_mod> compiled.
Entity <can_mod> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 14.00 secs
Total CPU time to Xst completion: 13.84 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/can/can_oc.vhd" in Library gaisler.
Entity <can_oc> compiled.
Entity <can_oc> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 14.00 secs
Total CPU time to Xst completion: 13.98 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/can/can_mc.vhd" in Library gaisler.
Entity <can_mc> compiled.
Entity <can_mc> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 14.00 secs
Total CPU time to Xst completion: 14.10 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/can/canmux.vhd" in Library gaisler.
Entity <canmux> compiled.
Entity <canmux> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 14.00 secs
Total CPU time to Xst completion: 14.20 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/can/can_rd.vhd" in Library gaisler.
Entity <can_rd> compiled.
Entity <can_rd> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 14.00 secs
Total CPU time to Xst completion: 14.32 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/misc/misc.vhd" in Library gaisler.
Package <misc> compiled.
Package body <misc> compiled.


Total REAL time to Xst completion: 14.00 secs
Total CPU time to Xst completion: 14.48 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/misc/rstgen.vhd" in Library gaisler.
Entity <rstgen> compiled.
Entity <rstgen> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 15.00 secs
Total CPU time to Xst completion: 14.59 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/misc/gptimer.vhd" in Library gaisler.
Entity <gptimer> compiled.
Entity <gptimer> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 15.00 secs
Total CPU time to Xst completion: 14.73 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/misc/ahbram.vhd" in Library gaisler.
Entity <ahbram> compiled.
Entity <ahbram> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 15.00 secs
Total CPU time to Xst completion: 14.85 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/misc/ahbtrace.vhd" in Library gaisler.
Entity <ahbtrace> compiled.
Entity <ahbtrace> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 15.00 secs
Total CPU time to Xst completion: 14.99 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/misc/ahbmst.vhd" in Library gaisler.
Entity <ahbmst> compiled.
Entity <ahbmst> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 15.00 secs
Total CPU time to Xst completion: 15.12 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/misc/grgpio.vhd" in Library gaisler.
Entity <grgpio> compiled.
Entity <grgpio> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 15.00 secs
Total CPU time to Xst completion: 15.26 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/misc/ahbstat.vhd" in Library gaisler.
Entity <ahbstat> compiled.
Entity <ahbstat> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 15.00 secs
Total CPU time to Xst completion: 15.38 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/misc/logan.vhd" in Library gaisler.
Entity <logan> compiled.
Entity <logan> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 15.00 secs
Total CPU time to Xst completion: 15.54 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/misc/apbps2.vhd" in Library gaisler.
Entity <apbps2> compiled.
Entity <apbps2> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 16.00 secs
Total CPU time to Xst completion: 15.68 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/misc/charrom_package.vhd" in Library gaisler.
Package <charrom_package> compiled.


Total REAL time to Xst completion: 16.00 secs
Total CPU time to Xst completion: 15.79 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/misc/charrom.vhd" in Library gaisler.
Entity <charrom> compiled.
Entity <charrom> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 16.00 secs
Total CPU time to Xst completion: 16.01 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/misc/apbvga.vhd" in Library gaisler.
Entity <apbvga> compiled.
Entity <apbvga> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 16.00 secs
Total CPU time to Xst completion: 16.15 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/misc/ahbdma.vhd" in Library gaisler.
Entity <ahbdma> compiled.
Entity <ahbdma> (Architecture <struct>) compiled.


Total REAL time to Xst completion: 16.00 secs
Total CPU time to Xst completion: 16.29 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/misc/svgactrl.vhd" in Library gaisler.
Entity <svgactrl> compiled.
Entity <svgactrl> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 16.00 secs
Total CPU time to Xst completion: 16.46 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/misc/i2cmst.vhd" in Library gaisler.
Entity <i2cmst> compiled.
Entity <i2cmst> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 17.00 secs
Total CPU time to Xst completion: 16.60 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/misc/spictrl.vhd" in Library gaisler.
Entity <spictrl> compiled.
Entity <spictrl> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 17.00 secs
Total CPU time to Xst completion: 16.82 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/misc/i2cslv.vhd" in Library gaisler.
Entity <i2cslv> compiled.
Entity <i2cslv> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 17.00 secs
Total CPU time to Xst completion: 16.97 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/misc/wild.vhd" in Library gaisler.
Package <Wild> compiled.


Total REAL time to Xst completion: 17.00 secs
Total CPU time to Xst completion: 17.08 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/misc/wild2ahb.vhd" in Library gaisler.
Entity <Wild2AHB> compiled.
Entity <Wild2AHB> (Architecture <RTL>) compiled.


Total REAL time to Xst completion: 17.00 secs
Total CPU time to Xst completion: 17.22 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/net/net.vhd" in Library gaisler.
Package <net> compiled.


Total REAL time to Xst completion: 17.00 secs
Total CPU time to Xst completion: 17.35 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/uart/uart.vhd" in Library gaisler.
Package <uart> compiled.


Total REAL time to Xst completion: 17.00 secs
Total CPU time to Xst completion: 17.47 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/uart/libdcom.vhd" in Library gaisler.
Package <libdcom> compiled.


Total REAL time to Xst completion: 18.00 secs
Total CPU time to Xst completion: 17.60 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/uart/apbuart.vhd" in Library gaisler.
Entity <apbuart> compiled.
Entity <apbuart> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 18.00 secs
Total CPU time to Xst completion: 17.75 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/uart/dcom.vhd" in Library gaisler.
Entity <dcom> compiled.
Entity <dcom> (Architecture <struct>) compiled.


Total REAL time to Xst completion: 18.00 secs
Total CPU time to Xst completion: 17.88 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/uart/dcom_uart.vhd" in Library gaisler.
Entity <dcom_uart> compiled.
Entity <dcom_uart> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 18.00 secs
Total CPU time to Xst completion: 18.03 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/uart/ahbuart.vhd" in Library gaisler.
Entity <ahbuart> compiled.
Entity <ahbuart> (Architecture <struct>) compiled.


Total REAL time to Xst completion: 18.00 secs
Total CPU time to Xst completion: 18.17 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/jtag/jtag.vhd" in Library gaisler.
Package <jtag> compiled.


Total REAL time to Xst completion: 18.00 secs
Total CPU time to Xst completion: 18.30 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/jtag/libjtagcom.vhd" in Library gaisler.
Package <libjtagcom> compiled.


Total REAL time to Xst completion: 18.00 secs
Total CPU time to Xst completion: 18.42 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/jtag/jtagcom.vhd" in Library gaisler.
Entity <jtagcom> compiled.
Entity <jtagcom> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 19.00 secs
Total CPU time to Xst completion: 18.58 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/jtag/ahbjtag.vhd" in Library gaisler.
Entity <ahbjtag> compiled.
Entity <ahbjtag> (Architecture <struct>) compiled.


Total REAL time to Xst completion: 19.00 secs
Total CPU time to Xst completion: 18.72 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/jtag/ahbjtag_bsd.vhd" in Library gaisler.
Entity <ahbjtag_bsd> compiled.
Entity <ahbjtag_bsd> (Architecture <struct>) compiled.


Total REAL time to Xst completion: 19.00 secs
Total CPU time to Xst completion: 18.86 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/greth/ethernet_mac.vhd" in Library gaisler.
Package <ethernet_mac> compiled.


Total REAL time to Xst completion: 19.00 secs
Total CPU time to Xst completion: 19.00 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/greth/greth.vhd" in Library gaisler.
Entity <greth> compiled.
Entity <greth> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 19.00 secs
Total CPU time to Xst completion: 19.16 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/greth/greth_gbit.vhd" in Library gaisler.
Entity <greth_gbit> compiled.
Entity <greth_gbit> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 19.00 secs
Total CPU time to Xst completion: 19.31 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/greth/grethm.vhd" in Library gaisler.
Entity <grethm> compiled.
Entity <grethm> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 19.00 secs
Total CPU time to Xst completion: 19.47 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/spacewire/spacewire.vhd" in Library gaisler.
Package <spacewire> compiled.


Total REAL time to Xst completion: 20.00 secs
Total CPU time to Xst completion: 19.63 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/spacewire/grspw.vhd" in Library gaisler.
Entity <grspw> compiled.
Entity <grspw> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 20.00 secs
Total CPU time to Xst completion: 19.78 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/spacewire/grspw2.vhd" in Library gaisler.
Entity <grspw2> compiled.
Entity <grspw2> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 20.00 secs
Total CPU time to Xst completion: 19.95 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/spacewire/grspwm.vhd" in Library gaisler.
Entity <grspwm> compiled.
Entity <grspwm> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 20.00 secs
Total CPU time to Xst completion: 20.09 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/usb/grusb.vhd" in Library gaisler.
Package <grusb> compiled.


Total REAL time to Xst completion: 20.00 secs
Total CPU time to Xst completion: 20.25 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/ata/ata.vhd" in Library gaisler.
Package <ata> compiled.


Total REAL time to Xst completion: 20.00 secs
Total CPU time to Xst completion: 20.39 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/ata/ata_inf.vhd" in Library gaisler.
Package <ata_inf> compiled.


Total REAL time to Xst completion: 20.00 secs
Total CPU time to Xst completion: 20.53 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/ata/atahost_amba_slave.vhd" in Library gaisler.
Entity <atahost_amba_slave> compiled.
Entity <atahost_amba_slave> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 21.00 secs
Total CPU time to Xst completion: 20.73 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/ata/atahost_ahbmst.vhd" in Library gaisler.
Entity <atahost_ahbmst> compiled.
Entity <atahost_ahbmst> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 21.00 secs
Total CPU time to Xst completion: 20.89 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/ata/ocidec2_amba_slave.vhd" in Library gaisler.
Entity <ocidec2_amba_slave> compiled.
Entity <ocidec2_amba_slave> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 21.00 secs
Total CPU time to Xst completion: 21.08 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/ata/atactrl_nodma.vhd" in Library gaisler.
Entity <atactrl_nodma> compiled.
Entity <atactrl_nodma> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 21.00 secs
Total CPU time to Xst completion: 21.25 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/ata/atactrl_dma.vhd" in Library gaisler.
Entity <atactrl_dma> compiled.
Entity <atactrl_dma> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 21.00 secs
Total CPU time to Xst completion: 21.42 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/gaisler/ata/atactrl.vhd" in Library gaisler.
Entity <atactrl> compiled.
Entity <atactrl> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 22.00 secs
Total CPU time to Xst completion: 21.59 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "../../lib/gaisler/vlog/decode_pipe1.v" in library gaisler
Compiling verilog include file "..\..\lib\gaisler\vlog/mips789_defs.v"
Module <decoder> compiled
Module <pipelinedregs> compiled
Module <decode_pipe> compiled


Total REAL time to Xst completion: 22.00 secs
Total CPU time to Xst completion: 21.62 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "../../lib/gaisler/vlog/EXEC_stage.v" in library gaisler
Compiling verilog include file "..\..\lib\gaisler\vlog/mips789_defs.v"
Module <exec_stage> compiled
Module <mips_alu> compiled
Module <alu_muxa> compiled
Module <alu_muxb> compiled
Module <alu> compiled
Module <shifter_ff> compiled
Module <shifter_tak> compiled
Module <muldiv> compiled
Module <muldiv_ff> compiled


Total REAL time to Xst completion: 22.00 secs
Total CPU time to Xst completion: 21.65 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "../../lib/gaisler/vlog/ulit.v" in library gaisler
Compiling verilog include file "..\..\lib\gaisler\vlog/mips789_defs.v"
Module <cal_cpi> compiled
Module <add32> compiled
Module <jack> compiled
Module <wb_mux> compiled
Module <or32> compiled
Module <rd_sel> compiled
Module <ext_ctl_reg_clr_cls> compiled
Module <rd_sel_reg_clr_cls> compiled
Module <cmp_ctl_reg_clr_cls> compiled
Module <pc_gen_ctl_reg_clr_cls> compiled
Module <fsm_ctl_reg_clr_cls> compiled
Module <muxa_ctl_reg_clr_cls> compiled
Module <muxb_ctl_reg_clr_cls> compiled
Module <alu_func_reg_clr_cls> compiled
Module <alu_we_reg_clr_cls> compiled
Module <dmem_ctl_reg_clr_cls> compiled
Module <wb_mux_ctl_reg_clr_cls> compiled
Module <wb_we_reg_clr_cls> compiled
Module <ins_reg_clr_cls> compiled
Module <pc_reg_clr_cls> compiled
Module <spc_reg_clr_cls> compiled
Module <r1_reg_clr_cls> compiled
Module <r2_reg_clr_cls> compiled
Module <r3_reg_clr_cls> compiled
Module <r4_reg_clr_cls> compiled
Module <r5_reg_clr_cls> compiled
Module <r32_reg_clr_cls> compiled
Module <ext_ctl_reg_clr> compiled
Module <rd_sel_reg_clr> compiled
Module <cmp_ctl_reg_clr> compiled
Module <pc_gen_ctl_reg_clr> compiled
Module <fsm_ctl_reg_clr> compiled
Module <muxa_ctl_reg_clr> compiled
Module <muxb_ctl_reg_clr> compiled
Module <alu_func_reg_clr> compiled
Module <alu_we_reg_clr> compiled
Module <dmem_ctl_reg_clr> compiled
Module <wb_mux_ctl_reg_clr> compiled
Module <wb_we_reg_clr> compiled
Module <ins_reg_clr> compiled
Module <pc_reg_clr> compiled
Module <spc_reg_clr> compiled
Module <r1_reg_clr> compiled
Module <r2_reg_clr> compiled
Module <r3_reg_clr> compiled
Module <r4_reg_clr> compiled
Module <r5_reg_clr> compiled
Module <r32_reg_clr> compiled
Module <ext_ctl_reg> compiled
Module <rd_sel_reg> compiled
Module <cmp_ctl_reg> compiled
Module <pc_gen_ctl_reg> compiled
Module <fsm_ctl_reg> compiled
Module <muxa_ctl_reg> compiled
Module <muxb_ctl_reg> compiled
Module <alu_func_reg> compiled
Module <alu_we_reg> compiled
Module <dmem_ctl_reg> compiled
Module <wb_mux_ctl_reg> compiled
Module <wb_we_reg> compiled
Module <ins_reg> compiled
Module <pc_reg> compiled
Module <spc_reg> compiled
Module <r1_reg> compiled
Module <r2_reg> compiled
Module <r3_reg> compiled
Module <r4_reg> compiled
Module <r5_reg> compiled
Module <r32_reg> compiled
Module <r32_inst_reg> compiled
Module <r32_data_reg> compiled
Module <ext_ctl_reg_cls> compiled
Module <rd_sel_reg_cls> compiled
Module <cmp_ctl_reg_cls> compiled
Module <pc_gen_ctl_reg_cls> compiled
Module <fsm_ctl_reg_cls> compiled
Module <muxa_ctl_reg_cls> compiled
Module <muxb_ctl_reg_cls> compiled
Module <alu_func_reg_cls> compiled
Module <alu_we_reg_cls> compiled
Module <dmem_ctl_reg_cls> compiled
Module <wb_mux_ctl_reg_cls> compiled
Module <wb_we_reg_cls> compiled
Module <ins_reg_cls> compiled
Module <pc_reg_cls> compiled
Module <spc_reg_cls> compiled
Module <r1_reg_cls> compiled
Module <r2_reg_cls> compiled
Module <r3_reg_cls> compiled
Module <r4_reg_cls> compiled
Module <r5_reg_cls> compiled
Module <r32_reg_cls> compiled


Total REAL time to Xst completion: 22.00 secs
Total CPU time to Xst completion: 21.81 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "../../lib/gaisler/vlog/ctl_fsm1.v" in library gaisler
Compiling verilog include file "..\..\lib\gaisler\vlog/mips789_defs.v"
Module <ctl_FSM> compiled


Total REAL time to Xst completion: 22.00 secs
Total CPU time to Xst completion: 21.82 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "../../lib/gaisler/vlog/RF_stage1.v" in library gaisler
Compiling verilog include file "..\..\lib\gaisler\vlog/mips789_defs.v"
Module <rf_stage> compiled


Total REAL time to Xst completion: 22.00 secs
Total CPU time to Xst completion: 21.82 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "../../lib/gaisler/vlog/RF_components1.v" in library gaisler
Compiling verilog include file "..\..\lib\gaisler\vlog/mips789_defs.v"
Module <ext> compiled
Module <compare> compiled
Module <pc_gen> compiled
Module <reg_array> compiled


Total REAL time to Xst completion: 22.00 secs
Total CPU time to Xst completion: 21.84 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "../../lib/gaisler/vlog/forward.v" in library gaisler
Compiling verilog include file "..\..\lib\gaisler\vlog/mips789_defs.v"
Module <fw_latch5> compiled
Module <fw_latch1> compiled
Module <forward_node> compiled
Module <fwd_mux> compiled
Module <forward> compiled


Total REAL time to Xst completion: 22.00 secs
Total CPU time to Xst completion: 21.86 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "../../lib/gaisler/vlog/mips789_defs.v" in library gaisler


Total REAL time to Xst completion: 22.00 secs
Total CPU time to Xst completion: 21.86 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "../../lib/gaisler/vlog/hazard_unit.v" in library gaisler
Module <hazard_unit> compiled


Total REAL time to Xst completion: 22.00 secs
Total CPU time to Xst completion: 21.87 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "../../lib/gaisler/vlog/forward.v" in library gaisler
Compiling verilog include file "..\..\lib\gaisler\vlog/mips789_defs.v"
Module <fw_latch5> compiled
Module <fw_latch1> compiled
Module <forward_node> compiled
Module <fwd_mux> compiled
Module <forward> compiled


Total REAL time to Xst completion: 22.00 secs
Total CPU time to Xst completion: 21.87 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "../../lib/gaisler/vlog/core1.v" in library gaisler
Compiling verilog include file "..\..\lib\gaisler\vlog/mips789_defs.v"
Module <mips_core> compiled


Total REAL time to Xst completion: 22.00 secs
Total CPU time to Xst completion: 21.90 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/esa/memoryctrl/memoryctrl.vhd" in Library esa.
Package <memoryctrl> compiled.


Total REAL time to Xst completion: 22.00 secs
Total CPU time to Xst completion: 22.04 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "../../lib/esa/memoryctrl/mctrl.vhd" in Library esa.
Entity <mctrl> compiled.
Entity <mctrl> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 22.00 secs
Total CPU time to Xst completion: 22.31 secs
 
--> 

Total memory usage is 580472 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   10 (   0 filtered)
Number of infos    :    0 (   0 filtered)

xst -ifn leon3mp.xst
Release 11.1 - xst L.33 (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "config.vhd" in Library work.
Package <config> compiled.


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.19 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "ahbrom.vhd" in Library work.
Entity <ahbrom> compiled.
Entity <ahbrom> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.28 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "vga_clkgen.vhd" in Library work.
Entity <vga_clkgen> compiled.
Entity <vga_clkgen> (Architecture <struct>) compiled.


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.36 secs
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "leon3mp.vhd" in Library work.
Entity <leon3mp> compiled.
Entity <leon3mp> (Architecture <rtl>) compiled.


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.58 secs
 
--> 
TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
        9.1) Device utilization summary
        9.2) Partition Resource Summary
        9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "leon3mp.vhd"
Input Format                       : vhdl

---- Target Parameters
Target Device                      : xc3s1500-fg456-4
Output File Name                   : "leon3mp"

---- Source Options
Automatic FSM Extraction           : no

---- Target Options
Pack IO Registers into IOBs        : true

---- General Options
Read Cores                         : yes
Bus Delimiter                      : ()

---- Other Options
Cores Search Directories           : ../../netlists/xilinx/spartan3/xst

=========================================================================

WARNING:Xst:29 - Optimization Effort not specified
The following parameters have been added:
Optimization Goal                  : SPEED

=========================================================================

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "leon3mp.vhd" in Library work.
Architecture rtl of Entity leon3mp is up to date.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <leon3mp> in library <work> (architecture <rtl>) with generics.
        clktech = 11
        dbguart = 0
        disas = 0
        fabtech = 11
        memtech = 11
        padtech = 11
        pclow = 2

Analyzing hierarchy for entity <clkpad> in library <techmap> (architecture <rtl>) with generics.
        arch = 0
        hf = 0
        level = 0
        tech = 11
        voltage = 3

Analyzing hierarchy for entity <inpad> in library <techmap> (architecture <rtl>) with generics.
        filter = 0
        level = 0
        strength = 0
        tech = 11
        voltage = 3

Analyzing hierarchy for entity <clkgen> in library <techmap> (architecture <struct>) with generics.
        clk2xen = 0
        clk_div = 5
        clk_mul = 4
        clk_odiv = 0
        clksel = 0
        freq = 50000
        noclkfb = 0
        pcidll = 0
        pcien = 0
        pcisysclk = 0
        sdramen = 1
        tech = 11

Analyzing hierarchy for entity <outpad> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        slew = 1
        strength = 24
        tech = 11
        voltage = 3

Analyzing hierarchy for entity <rstgen> in library <gaisler> (architecture <rtl>) with generics.
        acthigh = 0
        scanen = 0
        syncrst = 0

Analyzing hierarchy for entity <ahbctrl> in library <grlib> (architecture <rtl>) with generics.
        arbdisable = 0
        asserterr = 0
        assertwarn = 0
        cfgaddr = 4080
        cfgmask = 4080
        debug = 2
        defmast = 0
        devid = 0
        disirq = 0
        enbusmon = 0
        enebterm = 0
        fixbrst = 0
        fpnpen = 0
        hmstdisable = 0
        hslvdisable = 0
        icheck = 1
        ioaddr = 4095
        ioen = 0
        iomask = 4095
        mprio = 0
        nahbm = 3
        nahbs = 8
        rrobin = 1
        split = 0
        timeout = 0

Analyzing hierarchy for entity <leon3s> in library <gaisler> (architecture <rtl>) with generics.
        cached = 0
        cp = 0
        dcen = 1
        disas = 0
        dlinesize = 4
        dlram = 0
        dlramsize = 1
        dlramstart = 143
        drepl = 0
        dsetlock = 0
        dsets = 1
        dsetsize = 4
        dsnoop = 1
        dsu = 1
        dtlbnum = 2
        fabtech = 11
        fpu = 0
        hindex = 0
        icen = 1
        ilinesize = 8
        ilram = 0
        ilramsize = 1
        ilramstart = 142
        irepl = 0
        isetlock = 0
        isets = 2
        isetsize = 4
        itlbnum = 2
        lddel = 1
        mac = 0
        memtech = 11
        mmuen = 0
        notag = 0
        nwindows = 8
        nwp = 2
        pclow = 2
        pwd = 0
        rstaddr = 0
        scantest = 0
        smp = 0
        svt = 1
        tbuf = 2
        tlb_rep = 1
        tlb_type = 1
        v8 = 50

Analyzing hierarchy for entity <odpad> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        oepol = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3

Analyzing hierarchy for entity <dsu3> in library <gaisler> (architecture <rtl>) with generics.
        haddr = 2304
        hindex = 2
        hmask = 3840
        irq = 0
        kbytes = 0
        ncpu = 1
        tbits = 30
        tech = 11

Analyzing hierarchy for entity <outpad> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3

Analyzing hierarchy for entity <ahbuart> in library <gaisler> (architecture <struct>) with generics.
        hindex = 1
        paddr = 7
        pindex = 7
        pmask = 4095

Analyzing hierarchy for entity <ahbjtag> in library <gaisler> (architecture <struct>) with generics.
        ainst = 2
        dinst = 3
        hindex = 2
        idcode = 9
        manf = 804
        nsync = 1
        part = 0
        scantest = 0
        tech = 11
        ver = 0

Analyzing hierarchy for entity <mctrl> in library <esa> (architecture <rtl>) with generics.
        fast = 0
        hindex = 0
        invclk = 0
        ioaddr = 512
        iomask = 3584
        mobile = 0
        oepol = 0
        paddr = 0
        pageburst = 1
        pindex = 0
        pmask = 4095
        ram16 = 0
        ram8 = 1
        ramaddr = 1024
        rammask = 3072
        romaddr = 0
        romasel = 28
        rommask = 3584
        scantest = 0
        sdbits = 32
        sden = 1
        sdlsb = 2
        sdrasel = 29
        sepbus = 0
        srbanks = 2
        syncrst = 0
        wprot = 0

Analyzing hierarchy for entity <outpadv> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3
        width = 4

Analyzing hierarchy for entity <outpadv> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3
        width = 2

Analyzing hierarchy for entity <outpadv> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3
        width = 28

Analyzing hierarchy for entity <outpadv> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3
        width = 5

Analyzing hierarchy for entity <iopadv> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        oepol = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3
        width = 8

Analyzing hierarchy for entity <apbctrl> in library <grlib> (architecture <rtl>) with generics.
        asserterr = 0
        assertwarn = 0
        debug = 2
        enbusmon = 0
        haddr = 2048
        hindex = 1
        hmask = 4095
        icheck = 1
        nslaves = 16
        pslvdisable = 0

Analyzing hierarchy for entity <apbuart> in library <gaisler> (architecture <rtl>) with generics.
        abits = 8
        console = 0
        fifosize = 4
        flow = 1
        paddr = 1
        parity = 1
        pindex = 1
        pirq = 2
        pmask = 4095

Analyzing hierarchy for entity <irqmp> in library <gaisler> (architecture <rtl>) with generics.
        eirq = 0
        ncpu = 1
        paddr = 2
        pindex = 2
        pmask = 4095

Analyzing hierarchy for entity <gptimer> in library <gaisler> (architecture <rtl>) with generics.
        nbits = 32
        ntimers = 2
        paddr = 3
        pindex = 3
        pirq = 8
        pmask = 4095
        sbits = 8
        sepirq = 1
        wdog = 0

Analyzing hierarchy for entity <iopad> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        oepol = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3

Analyzing hierarchy for entity <outpadv> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3
        width = 8

Analyzing hierarchy for entity <grgpio> in library <gaisler> (architecture <rtl>) with generics.
        bpdir = 0
        bypass = 0
        imask = 0
        nbits = 18
        oepol = 0
        paddr = 8
        pindex = 8
        pmask = 4095
        scantest = 0
        syncrst = 0

Analyzing hierarchy for entity <virtex_clkpad> in library <techmap> (architecture <rtl>) with generics.
        arch = 0
        hf = 0
        level = 0
        voltage = 3

Analyzing hierarchy for entity <virtex_inpad> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        voltage = 3

Analyzing hierarchy for entity <clkgen_spartan3> in library <techmap> (architecture <struct>) with generics.
        clk2xen = 0
        clk_div = 5
        clk_mul = 4
        clksel = 0
        freq = 50000
        noclkfb = 0
        pcidll = 0
        pcien = 0
        pcisysclk = 0
        sdramen = 1

Analyzing hierarchy for entity <virtex_outpad> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        slew = 1
        strength = 24
        voltage = 3

Analyzing hierarchy for entity <proc3> in library <gaisler> (architecture <rtl>) with generics.
        cached = 0
        clk2x = 0
        cp = 0
        dcen = 1
        disas = 0
        dlinesize = 4
        dlram = 0
        dlramsize = 1
        dlramstart = 143
        drepl = 0
        dsetlock = 0
        dsets = 1
        dsetsize = 4
        dsnoop = 1
        dsu = 1
        dtlbnum = 2
        fabtech = 11
        fpu = 0
        hindex = 0
        icen = 1
        ilinesize = 8
        ilram = 0
        ilramsize = 1
        ilramstart = 142
        irepl = 0
        isetlock = 0
        isets = 2
        isetsize = 4
        itlbnum = 2
        lddel = 1
        mac = 0
        memtech = 11
        mmuen = 0
        notag = 0
        nwindows = 8
        nwp = 2
        pclow = 2
        pwd = 0
        rstaddr = 0
        scantest = 0
        smp = 0
        svt = 1
        tbuf = 2
        tlb_rep = 1
        tlb_type = 1
        v8 = 50

Analyzing hierarchy for entity <regfile_3p> in library <techmap> (architecture <rtl>) with generics.
        abits = 5
        dbits = 32
        numregs = 32
        tech = 11
        wrfst = 1

Analyzing hierarchy for entity <cachemem> in library <gaisler> (architecture <rtl>) with generics.
        dcen = 1
        dlinesize = 4
        dlram = 0
        dlramsize = 1
        drepl = 0
        dsetlock = 0
        dsets = 1
        dsetsize = 4
        dsnoop = 1
        icen = 1
        ilinesize = 8
        ilram = 0
        ilramsize = 1
        irepl = 0
        isetlock = 0
        isets = 2
        isetsize = 4
        mmuen = 0
        tech = 11

Analyzing hierarchy for entity <tbufmem> in library <gaisler> (architecture <rtl>) with generics.
        tbuf = 2
        tech = 11

Analyzing hierarchy for entity <virtex_toutpad> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        slew = 0
        strength = 12
        voltage = 3

Analyzing hierarchy for entity <dsu3x> in library <gaisler> (architecture <rtl>) with generics.
        clk2x = 0
        haddr = 2304
        hindex = 2
        hmask = 3840
        irq = 0
        kbytes = 0
        ncpu = 1
        tbits = 30
        tech = 11

Analyzing hierarchy for entity <virtex_outpad> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        slew = 0
        strength = 12
        voltage = 3

Analyzing hierarchy for entity <ahbmst> in library <gaisler> (architecture <rtl>) with generics.
        chprot = 3
        devid = 7
        hindex = 1
        hirq = 0
        incaddr = 0
        venid = 1
        version = 0

Analyzing hierarchy for entity <dcom_uart> in library <gaisler> (architecture <rtl>) with generics.
        paddr = 7
        pindex = 7
        pmask = 4095

Analyzing hierarchy for entity <dcom> in library <gaisler> (architecture <struct>).

Analyzing hierarchy for entity <ahbmst> in library <gaisler> (architecture <rtl>) with generics.
        chprot = 3
        devid = 28
        hindex = 2
        hirq = 0
        incaddr = 0
        venid = 1
        version = 0

Analyzing hierarchy for entity <tap> in library <techmap> (architecture <rtl>) with generics.
        idcode = 9
        irlen = 6
        manf = 804
        part = 0
        scantest = 0
        tech = 11
        trsten = 1
        ver = 0

Analyzing hierarchy for entity <jtagcom> in library <gaisler> (architecture <rtl>) with generics.
        ainst = 2
        dinst = 3
        isel = 1
        nsync = 1

Analyzing hierarchy for entity <sdmctrl> in library <gaisler> (architecture <rtl>) with generics.
        fast = 0
        invclk = 0
        mobile = 0
        pageburst = 1
        pindex = 0
        sdbits = 32
        wprot = 0

Analyzing hierarchy for entity <outpad> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3

Analyzing hierarchy for entity <outpad> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3

Analyzing hierarchy for entity <outpad> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3

Analyzing hierarchy for entity <outpad> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3

Analyzing hierarchy for entity <outpad> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3

Analyzing hierarchy for entity <outpad> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3

Analyzing hierarchy for entity <outpad> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3

Analyzing hierarchy for entity <outpad> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3

Analyzing hierarchy for entity <outpad> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3

Analyzing hierarchy for entity <iopad> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        oepol = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3

Analyzing hierarchy for entity <virtex_iopad> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        slew = 0
        strength = 12
        voltage = 3

Analyzing hierarchy for entity <outpad> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3

Analyzing hierarchy for entity <outpad> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3

Analyzing hierarchy for entity <outpad> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3

Analyzing hierarchy for entity <outpad> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3

Analyzing hierarchy for entity <outpad> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3

Analyzing hierarchy for entity <outpad> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3

Analyzing hierarchy for entity <outpad> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3

Analyzing hierarchy for entity <outpad> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3

Analyzing hierarchy for entity <top> in library <gaisler> (architecture <behavioral>).

Analyzing hierarchy for entity <mul32> in library <gaisler> (architecture <rtl>) with generics.
        infer = 1
        mac = 0
        multype = 3
        pipe = 1

Analyzing hierarchy for entity <div32> in library <gaisler> (architecture <rtl>).

Analyzing hierarchy for entity <cache> in library <gaisler> (architecture <rtl>) with generics.
        cached = 0
        clk2x = 0
        dcen = 1
        dlinesize = 4
        dlram = 0
        dlramsize = 1
        dlramstart = 143
        drepl = 0
        dsetlock = 0
        dsets = 1
        dsetsize = 4
        dsnoop = 1
        dsu = 1
        hindex = 0
        icen = 1
        ilinesize = 8
        ilram = 0
        ilramsize = 1
        ilramstart = 142
        irepl = 0
        isetlock = 0
        isets = 2
        isetsize = 4
        memtech = 11
        scantest = 0

Analyzing hierarchy for entity <generic_regfile_3p> in library <techmap> (architecture <rtl>) with generics.
        abits = 5
        dbits = 32
        numregs = 32
        tech = 11
        wrfst = 1

Analyzing hierarchy for entity <syncram> in library <techmap> (architecture <rtl>) with generics.
        abits = 7
        dbits = 28
        tech = 11

Analyzing hierarchy for entity <syncram> in library <techmap> (architecture <rtl>) with generics.
        abits = 10
        dbits = 32
        tech = 11

Analyzing hierarchy for entity <syncram_dp> in library <techmap> (architecture <rtl>) with generics.
        abits = 8
        dbits = 24
        tech = 11

Analyzing hierarchy for entity <syncram64> in library <techmap> (architecture <rtl>) with generics.
        abits = 7
        tech = 11

Analyzing hierarchy for entity <spartan3_tap> in library <techmap> (architecture <rtl>).

Analyzing hierarchy for entity <virtex_outpad> in library <techmap> (architecture <rtl>) with generics.
        level = 0
        slew = 0
        strength = 12
        voltage = 3

Analyzing hierarchy for entity <my_mux> in library <gaisler> (architecture <rtl>).

Analyzing hierarchy for module <mips_core> in library <gaisler>.

Analyzing hierarchy for entity <icache> in library <gaisler> (architecture <rtl>) with generics.
        icen = 1
        ilinesize = 8
        irepl = 0
        isetlock = 0
        isets = 2
        isetsize = 4
        lram = 0
        lramsize = 1
        lramstart = 142

Analyzing hierarchy for entity <dcache> in library <gaisler> (architecture <rtl>) with generics.
        cached = 0
        dcen = 1
        dlinesize = 4
        dlram = 0
        dlramsize = 1
        dlramstart = 143
        drepl = 0
        dsetlock = 0
        dsets = 1
        dsetsize = 4
        dsnoop = 1
        dsu = 1
        ilram = 0
        ilramstart = 142
        memtech = 11

Analyzing hierarchy for entity <mmu_acache> in library <gaisler> (architecture <rtl>) with generics.
        cached = 0
        clk2x = 0
        hindex = 0
        ilinesize = 8
        scantest = 0

Analyzing hierarchy for entity <virtex2_syncram> in library <techmap> (architecture <behav>) with generics.
        abits = 7
        dbits = 28

Analyzing hierarchy for entity <virtex2_syncram> in library <techmap> (architecture <behav>) with generics.
        abits = 10
        dbits = 32

Analyzing hierarchy for entity <virtex2_syncram_dp> in library <techmap> (architecture <behav>) with generics.
        abits = 8
        dbits = 24

Analyzing hierarchy for entity <virtex2_syncram64> in library <techmap> (architecture <behav>) with generics.
        abits = 7

Analyzing hierarchy for module <rf_stage> in library <gaisler>.

Analyzing hierarchy for module <exec_stage> in library <gaisler>.

Analyzing hierarchy for module <r32_reg> in library <gaisler>.

Analyzing hierarchy for module <r32_inst_reg> in library <gaisler>.

Analyzing hierarchy for module <r32_data_reg> in library <gaisler>.

Analyzing hierarchy for module <decode_pipe> in library <gaisler>.

Analyzing hierarchy for module <forward> in library <gaisler>.

Analyzing hierarchy for module <r5_reg> in library <gaisler>.

Analyzing hierarchy for module <wb_mux> in library <gaisler>.

Analyzing hierarchy for module <hazard_unit> in library <gaisler>.

Analyzing hierarchy for module <cal_cpi> in library <gaisler>.

Analyzing hierarchy for module <ctl_FSM> in library <gaisler> with parameters.
        ID_CUR = "00000000000000000000000000000001"
        ID_LD = "00000000000000000000000000000101"
        ID_MUL = "00000000000000000000000000000010"
        ID_NOI = "00000000000000000000000000000110"
        ID_RET = "00000000000000000000000000000100"
        PC_IGN = "00000000000000000000000000000001"
        PC_IRQ = "00000000000000000000000000000100"
        PC_KEP = "00000000000000000000000000000010"
        PC_RST = "00000000000000000000000000001000"

Analyzing hierarchy for module <pc_gen> in library <gaisler>.

Analyzing hierarchy for module <compare> in library <gaisler>.

Analyzing hierarchy for module <ext> in library <gaisler>.

Analyzing hierarchy for module <r32_reg_clr_cls> in library <gaisler>.

Analyzing hierarchy for module <jack> in library <gaisler>.

Analyzing hierarchy for module <rd_sel> in library <gaisler>.

Analyzing hierarchy for module <fwd_mux> in library <gaisler>.

Analyzing hierarchy for module <mips_alu> in library <gaisler>.

Analyzing hierarchy for module <add32> in library <gaisler>.

Analyzing hierarchy for module <alu_muxa> in library <gaisler>.

Analyzing hierarchy for module <alu_muxb> in library <gaisler>.

Analyzing hierarchy for module <r32_reg_cls> in library <gaisler>.

Analyzing hierarchy for module <decoder> in library <gaisler>.

Analyzing hierarchy for module <pipelinedregs> in library <gaisler>.

Analyzing hierarchy for module <forward_node> in library <gaisler>.

Analyzing hierarchy for module <fw_latch5> in library <gaisler>.

Analyzing hierarchy for module <r1_reg> in library <gaisler>.

Analyzing hierarchy for module <r5_reg> in library <gaisler>.

Analyzing hierarchy for module <muldiv_ff> in library <gaisler> with parameters.
        OP_DIV = "00000000000000000000000000001011"
        OP_DIVU = "00000000000000000000000000001010"
        OP_MFHI = "00000000000000000000000000000110"
        OP_MFLO = "00000000000000000000000000000111"
        OP_MTHI = "00000000000000000000000000011111"
        OP_MTLO = "00000000000000000000000000011110"
        OP_MULT = "00000000000000000000000000001001"
        OP_MULTU = "00000000000000000000000000001000"
        OP_NONE = "00000000000000000000000000000000"

Analyzing hierarchy for module <shifter_tak> in library <gaisler>.

Analyzing hierarchy for module <alu> in library <gaisler>.

Analyzing hierarchy for module <muxb_ctl_reg_clr_cls> in library <gaisler>.

Analyzing hierarchy for module <wb_mux_ctl_reg_clr_cls> in library <gaisler>.

Analyzing hierarchy for module <wb_we_reg_clr_cls> in library <gaisler>.

Analyzing hierarchy for module <wb_we_reg> in library <gaisler>.

Analyzing hierarchy for module <wb_mux_ctl_reg_clr> in library <gaisler>.

Analyzing hierarchy for module <muxb_ctl_reg_clr> in library <gaisler>.

Analyzing hierarchy for module <dmem_ctl_reg_clr> in library <gaisler>.

Analyzing hierarchy for module <alu_func_reg_clr> in library <gaisler>.

Analyzing hierarchy for module <muxa_ctl_reg_clr> in library <gaisler>.

Analyzing hierarchy for module <wb_mux_ctl_reg> in library <gaisler>.

Analyzing hierarchy for module <wb_we_reg_clr> in library <gaisler>.

Analyzing hierarchy for module <cmp_ctl_reg_clr_cls> in library <gaisler>.

Analyzing hierarchy for module <alu_we_reg_clr> in library <gaisler>.

Analyzing hierarchy for module <alu_func_reg_clr_cls> in library <gaisler>.

Analyzing hierarchy for module <dmem_ctl_reg_clr_cls> in library <gaisler>.

Analyzing hierarchy for module <ext_ctl_reg_clr_cls> in library <gaisler>.

Analyzing hierarchy for module <rd_sel_reg_clr_cls> in library <gaisler>.

Analyzing hierarchy for module <alu_we_reg_clr_cls> in library <gaisler>.

Analyzing hierarchy for module <muxa_ctl_reg_clr_cls> in library <gaisler>.

Analyzing hierarchy for module <pc_gen_ctl_reg_clr_cls> in library <gaisler>.

Analyzing hierarchy for module <dmem_ctl_reg> in library <gaisler>.

WARNING:Xst:2591 - "../../lib/techmap/unisim/clkgen_unisim.vhd" line 586: attribute on instance <CLKIN_PERIOD> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing generic Entity <leon3mp> in library <work> (Architecture <rtl>).
        clktech = 11
        dbguart = 0
        disas = 0
        fabtech = 11
        memtech = 11
        padtech = 11
        pclow = 2
WARNING:Xst:37 - Detected unknown constraint/property "syn_netlist_hierarchy". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_keep = TRUE" for signal <clk50>.
    Set property "syn_preserve = TRUE" for signal <clk50>.
    Set user-defined property "KEEP =  TRUE" for signal <clk50> (previous value was "KEEP soft").
WARNING:Xst:752 - "leon3mp.vhd" line 263: Unconnected input port 'rstn' of component 'clkpad' is tied to default value.
WARNING:Xst:753 - "leon3mp.vhd" line 263: Unconnected output port 'lock' of component 'clkpad'.
WARNING:Xst:752 - "leon3mp.vhd" line 265: Unconnected input port 'rstn' of component 'clkpad' is tied to default value.
WARNING:Xst:753 - "leon3mp.vhd" line 265: Unconnected output port 'lock' of component 'clkpad'.
WARNING:Xst:753 - "leon3mp.vhd" line 266: Unconnected output port 'clkn' of component 'clkgen'.
WARNING:Xst:753 - "leon3mp.vhd" line 266: Unconnected output port 'clk2x' of component 'clkgen'.
WARNING:Xst:753 - "leon3mp.vhd" line 266: Unconnected output port 'pciclk' of component 'clkgen'.
WARNING:Xst:753 - "leon3mp.vhd" line 266: Unconnected output port 'clk4x' of component 'clkgen'.
WARNING:Xst:753 - "leon3mp.vhd" line 266: Unconnected output port 'clk2xu' of component 'clkgen'.
WARNING:Xst:752 - "leon3mp.vhd" line 275: Unconnected input port 'testrst' of component 'rstgen' is tied to default value.
WARNING:Xst:752 - "leon3mp.vhd" line 275: Unconnected input port 'testen' of component 'rstgen' is tied to default value.
WARNING:Xst:752 - "leon3mp.vhd" line 282: Unconnected input port 'testen' of component 'ahbctrl' is tied to default value.
WARNING:Xst:752 - "leon3mp.vhd" line 282: Unconnected input port 'testrst' of component 'ahbctrl' is tied to default value.
WARNING:Xst:752 - "leon3mp.vhd" line 282: Unconnected input port 'scanen' of component 'ahbctrl' is tied to default value.
WARNING:Xst:752 - "leon3mp.vhd" line 282: Unconnected input port 'testoen' of component 'ahbctrl' is tied to default value.
WARNING:Xst:753 - "leon3mp.vhd" line 331: Unconnected output port 'tapo_tck' of component 'ahbjtag'.
WARNING:Xst:753 - "leon3mp.vhd" line 331: Unconnected output port 'tapo_tdi' of component 'ahbjtag'.
WARNING:Xst:753 - "leon3mp.vhd" line 331: Unconnected output port 'tapo_inst' of component 'ahbjtag'.
WARNING:Xst:753 - "leon3mp.vhd" line 331: Unconnected output port 'tapo_rst' of component 'ahbjtag'.
WARNING:Xst:753 - "leon3mp.vhd" line 331: Unconnected output port 'tapo_capt' of component 'ahbjtag'.
WARNING:Xst:753 - "leon3mp.vhd" line 331: Unconnected output port 'tapo_shft' of component 'ahbjtag'.
WARNING:Xst:753 - "leon3mp.vhd" line 331: Unconnected output port 'tapo_upd' of component 'ahbjtag'.
WARNING:Xst:752 - "leon3mp.vhd" line 331: Unconnected input port 'trst' of component 'ahbjtag' is tied to default value.
WARNING:Xst:753 - "leon3mp.vhd" line 331: Unconnected output port 'tdoen' of component 'ahbjtag'.
Entity <leon3mp> analyzed. Unit <leon3mp> generated.

Analyzing generic Entity <clkpad> in library <techmap> (Architecture <rtl>).
        arch = 0
        hf = 0
        level = 0
        tech = 11
        voltage = 3
Entity <clkpad> analyzed. Unit <clkpad> generated.

Analyzing generic Entity <virtex_clkpad> in library <techmap> (Architecture <rtl>).
        arch = 0
        hf = 0
        level = 0
        voltage = 3
WARNING:Xst:2211 - "../../lib/techmap/unisim/pads_unisim.vhd" line 450: Instantiating black box module <IBUFG>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <g0.ttl0.ip> in unit <virtex_clkpad>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <g0.ttl0.ip> in unit <virtex_clkpad>.
Entity <virtex_clkpad> analyzed. Unit <virtex_clkpad> generated.

Analyzing generic Entity <inpad> in library <techmap> (Architecture <rtl>).
        filter = 0
        level = 0
        strength = 0
        tech = 11
        voltage = 3
Entity <inpad> analyzed. Unit <inpad> generated.

Analyzing generic Entity <virtex_inpad> in library <techmap> (Architecture <rtl>).
        level = 0
        voltage = 3
WARNING:Xst:2211 - "../../lib/techmap/unisim/pads_unisim.vhd" line 52: Instantiating black box module <IBUF>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <ttl0.ip> in unit <virtex_inpad>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <ttl0.ip> in unit <virtex_inpad>.
Entity <virtex_inpad> analyzed. Unit <virtex_inpad> generated.

Analyzing generic Entity <clkgen> in library <techmap> (Architecture <struct>).
        clk2xen = 0
        clk_div = 5
        clk_mul = 4
        clk_odiv = 0
        clksel = 0
        freq = 50000
        noclkfb = 0
        pcidll = 0
        pcien = 0
        pcisysclk = 0
        sdramen = 1
        tech = 11
Entity <clkgen> analyzed. Unit <clkgen> generated.

Analyzing generic Entity <clkgen_spartan3> in library <techmap> (Architecture <struct>).
        clk2xen = 0
        clk_div = 5
        clk_mul = 4
        clksel = 0
        freq = 50000
        noclkfb = 0
        pcidll = 0
        pcien = 0
        pcisysclk = 0
        sdramen = 1
WARNING:Xst:2211 - "../../lib/techmap/unisim/clkgen_unisim.vhd" line 574: Instantiating black box module <BUFG>.
WARNING:Xst:2211 - "../../lib/techmap/unisim/clkgen_unisim.vhd" line 575: Instantiating black box module <BUFG>.
WARNING:Xst:753 - "../../lib/techmap/unisim/clkgen_unisim.vhd" line 586: Unconnected output port 'CLK90' of component 'DCM'.
WARNING:Xst:753 - "../../lib/techmap/unisim/clkgen_unisim.vhd" line 586: Unconnected output port 'CLK180' of component 'DCM'.
WARNING:Xst:753 - "../../lib/techmap/unisim/clkgen_unisim.vhd" line 586: Unconnected output port 'CLK270' of component 'DCM'.
WARNING:Xst:753 - "../../lib/techmap/unisim/clkgen_unisim.vhd" line 586: Unconnected output port 'CLK2X180' of component 'DCM'.
WARNING:Xst:753 - "../../lib/techmap/unisim/clkgen_unisim.vhd" line 586: Unconnected output port 'CLKDV' of component 'DCM'.
WARNING:Xst:753 - "../../lib/techmap/unisim/clkgen_unisim.vhd" line 586: Unconnected output port 'PSDONE' of component 'DCM'.
WARNING:Xst:753 - "../../lib/techmap/unisim/clkgen_unisim.vhd" line 586: Unconnected output port 'STATUS' of component 'DCM'.
WARNING:Xst:2211 - "../../lib/techmap/unisim/clkgen_unisim.vhd" line 586: Instantiating black box module <DCM>.
    Set user-defined property "CLKDV_DIVIDE =  2.0000000000000000" for instance <dll0> in unit <clkgen_spartan3>.
    Set user-defined property "CLKFX_DIVIDE =  5" for instance <dll0> in unit <clkgen_spartan3>.
    Set user-defined property "CLKFX_MULTIPLY =  4" for instance <dll0> in unit <clkgen_spartan3>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <dll0> in unit <clkgen_spartan3>.
    Set user-defined property "CLKIN_PERIOD =  20.0000000000000000" for instance <dll0> in unit <clkgen_spartan3>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <dll0> in unit <clkgen_spartan3>.
    Set user-defined property "CLK_FEEDBACK =  2X" for instance <dll0> in unit <clkgen_spartan3>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <dll0> in unit <clkgen_spartan3>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <dll0> in unit <clkgen_spartan3>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <dll0> in unit <clkgen_spartan3>.
    Set user-defined property "DSS_MODE =  NONE" for instance <dll0> in unit <clkgen_spartan3>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <dll0> in unit <clkgen_spartan3>.
    Set user-defined property "FACTORY_JF =  C080" for instance <dll0> in unit <clkgen_spartan3>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <dll0> in unit <clkgen_spartan3>.
    Set user-defined property "STARTUP_WAIT =  FALSE" for instance <dll0> in unit <clkgen_spartan3>.
WARNING:Xst:753 - "../../lib/techmap/unisim/clkgen_unisim.vhd" line 620: Unconnected output port 'CLK90' of component 'DCM'.
WARNING:Xst:753 - "../../lib/techmap/unisim/clkgen_unisim.vhd" line 620: Unconnected output port 'CLK180' of component 'DCM'.
WARNING:Xst:753 - "../../lib/techmap/unisim/clkgen_unisim.vhd" line 620: Unconnected output port 'CLK270' of component 'DCM'.
WARNING:Xst:753 - "../../lib/techmap/unisim/clkgen_unisim.vhd" line 620: Unconnected output port 'CLK2X' of component 'DCM'.
WARNING:Xst:753 - "../../lib/techmap/unisim/clkgen_unisim.vhd" line 620: Unconnected output port 'CLK2X180' of component 'DCM'.
WARNING:Xst:753 - "../../lib/techmap/unisim/clkgen_unisim.vhd" line 620: Unconnected output port 'CLKDV' of component 'DCM'.
WARNING:Xst:753 - "../../lib/techmap/unisim/clkgen_unisim.vhd" line 620: Unconnected output port 'CLKFX' of component 'DCM'.
WARNING:Xst:753 - "../../lib/techmap/unisim/clkgen_unisim.vhd" line 620: Unconnected output port 'CLKFX180' of component 'DCM'.
WARNING:Xst:753 - "../../lib/techmap/unisim/clkgen_unisim.vhd" line 620: Unconnected output port 'PSDONE' of component 'DCM'.
WARNING:Xst:753 - "../../lib/techmap/unisim/clkgen_unisim.vhd" line 620: Unconnected output port 'STATUS' of component 'DCM'.
WARNING:Xst:2211 - "../../lib/techmap/unisim/clkgen_unisim.vhd" line 620: Instantiating black box module <DCM>.
    Set user-defined property "CLKDV_DIVIDE =  2.0000000000000000" for instance <sd0.dll1> in unit <clkgen_spartan3>.
    Set user-defined property "CLKFX_DIVIDE =  2" for instance <sd0.dll1> in unit <clkgen_spartan3>.
    Set user-defined property "CLKFX_MULTIPLY =  2" for instance <sd0.dll1> in unit <clkgen_spartan3>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <sd0.dll1> in unit <clkgen_spartan3>.
    Set user-defined property "CLKIN_PERIOD =  10.0000000000000000" for instance <sd0.dll1> in unit <clkgen_spartan3>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <sd0.dll1> in unit <clkgen_spartan3>.
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <sd0.dll1> in unit <clkgen_spartan3>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <sd0.dll1> in unit <clkgen_spartan3>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <sd0.dll1> in unit <clkgen_spartan3>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <sd0.dll1> in unit <clkgen_spartan3>.
    Set user-defined property "DSS_MODE =  NONE" for instance <sd0.dll1> in unit <clkgen_spartan3>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <sd0.dll1> in unit <clkgen_spartan3>.
    Set user-defined property "FACTORY_JF =  C080" for instance <sd0.dll1> in unit <clkgen_spartan3>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <sd0.dll1> in unit <clkgen_spartan3>.
    Set user-defined property "STARTUP_WAIT =  FALSE" for instance <sd0.dll1> in unit <clkgen_spartan3>.
Entity <clkgen_spartan3> analyzed. Unit <clkgen_spartan3> generated.

Analyzing generic Entity <outpad.1> in library <techmap> (Architecture <rtl>).
        level = 0
        slew = 1
        strength = 24
        tech = 11
        voltage = 3
Entity <outpad.1> analyzed. Unit <outpad.1> generated.

Analyzing generic Entity <virtex_outpad.1> in library <techmap> (Architecture <rtl>).
        level = 0
        slew = 1
        strength = 24
        voltage = 3
WARNING:Xst:2211 - "../../lib/techmap/unisim/pads_unisim.vhd" line 182: Instantiating black box module <OBUF>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <ttl0.fast0.op> in unit <virtex_outpad.1>.
    Set user-defined property "DRIVE =  24" for instance <ttl0.fast0.op> in unit <virtex_outpad.1>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <ttl0.fast0.op> in unit <virtex_outpad.1>.
    Set user-defined property "SLEW =  FAST" for instance <ttl0.fast0.op> in unit <virtex_outpad.1>.
Entity <virtex_outpad.1> analyzed. Unit <virtex_outpad.1> generated.

Analyzing generic Entity <rstgen> in library <gaisler> (Architecture <rtl>).
        acthigh = 0
        scanen = 0
        syncrst = 0
Entity <rstgen> analyzed. Unit <rstgen> generated.

Analyzing generic Entity <ahbctrl> in library <grlib> (Architecture <rtl>).
        arbdisable = 0
        asserterr = 0
        assertwarn = 0
        cfgaddr = 4080
        cfgmask = 4080
        debug = 2
        defmast = 0
        devid = 0
        disirq = 0
        enbusmon = 0
        enebterm = 0
        fixbrst = 0
        fpnpen = 0
        hmstdisable = 0
        hslvdisable = 0
        icheck = 1
        ioaddr = 4095
        ioen = 0
        iomask = 4095
        mprio = 0
        nahbm = 3
        nahbs = 8
        rrobin = 1
        split = 0
        timeout = 0
WARNING:Xst:790 - "../../lib/grlib/amba/ahbctrl.vhd" line 160: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "../../lib/grlib/amba/ahbctrl.vhd" line 486: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "../../lib/grlib/amba/ahbctrl.vhd" line 495: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "../../lib/grlib/amba/ahbctrl.vhd" line 534: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "../../lib/grlib/amba/ahbctrl.vhd" line 557: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "../../lib/grlib/amba/ahbctrl.vhd" line 571: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:819 - "../../lib/grlib/amba/ahbctrl.vhd" line 338: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
   <msto(15).hbusreq>, <msto(15).hlock>, <msto(15).htrans>, <msto(15).haddr>, <msto(15).hwrite>, <msto(15).hsize>, <msto(15).hburst>, <msto(15).hprot>, <msto(15).hwdata>, <msto(15).hirq>, <msto(15).hconfig>, <msto(15).hindex>, <msto(14).hbusreq>, <msto(14).hlock>, <msto(14).htrans>, <msto(14).haddr>, <msto(14).hwrite>, <msto(14).hsize>, <msto(14).hburst>, <msto(14).hprot>, <msto(14).hwdata>, <msto(14).hirq>, <msto(14).hconfig>, <msto(14).hindex>, <msto(13).hbusreq>, <msto(13).hlock>, <msto(13).htrans>, <msto(13).haddr>, <msto(13).hwrite>, <msto(13).hsize>, <msto(13).hburst>, <msto(13).hprot>, <msto(13).hwdata>, <msto(13).hirq>, <msto(13).hconfig>, <msto(13).hindex>, <msto(12).hbusreq>, <msto(12).hlock>, <msto(12).htrans>, <msto(12).haddr>, <msto(12).hwrite>, <msto(12).hsize>, <msto(12).hburst>, <msto(12).hprot>, <msto(12).hwdata>, <msto(12).hirq>, <msto(12).hconfig>, <msto(12).hindex>, <msto(11).hbusreq>, <msto(11).hlock>, <msto(11).htrans>, <msto(11).haddr>, <msto(11).hwrite>, <msto(11).hsize>,
   <msto(11).hburst>, <msto(11).hprot>, <msto(11).hwdata>, <msto(11).hirq>, <msto(11).hconfig>, <msto(11).hindex>, <msto(10).hbusreq>, <msto(10).hlock>, <msto(10).htrans>, <msto(10).haddr>, <msto(10).hwrite>, <msto(10).hsize>, <msto(10).hburst>, <msto(10).hprot>, <msto(10).hwdata>, <msto(10).hirq>, <msto(10).hconfig>, <msto(10).hindex>, <msto(9).hbusreq>, <msto(9).hlock>, <msto(9).htrans>, <msto(9).haddr>, <msto(9).hwrite>, <msto(9).hsize>, <msto(9).hburst>, <msto(9).hprot>, <msto(9).hwdata>, <msto(9).hirq>, <msto(9).hconfig>, <msto(9).hindex>, <msto(8).hbusreq>, <msto(8).hlock>, <msto(8).htrans>, <msto(8).haddr>, <msto(8).hwrite>, <msto(8).hsize>, <msto(8).hburst>, <msto(8).hprot>, <msto(8).hwdata>, <msto(8).hirq>, <msto(8).hconfig>, <msto(8).hindex>, <msto(7).hbusreq>, <msto(7).hlock>, <msto(7).htrans>, <msto(7).haddr>, <msto(7).hwrite>, <msto(7).hsize>, <msto(7).hburst>, <msto(7).hprot>, <msto(7).hwdata>, <msto(7).hirq>, <msto(7).hconfig>, <msto(7).hindex>, <msto(6).hbusreq>, <msto(6).hlock>,
   <msto(6).htrans>, <msto(6).haddr>, <msto(6).hwrite>, <msto(6).hsize>, <msto(6).hburst>, <msto(6).hprot>, <msto(6).hwdata>, <msto(6).hirq>, <msto(6).hconfig>, <msto(6).hindex>, <msto(5).hbusreq>, <msto(5).hlock>, <msto(5).htrans>, <msto(5).haddr>, <msto(5).hwrite>, <msto(5).hsize>, <msto(5).hburst>, <msto(5).hprot>, <msto(5).hwdata>, <msto(5).hirq>, <msto(5).hconfig>, <msto(5).hindex>, <msto(4).hbusreq>, <msto(4).hlock>, <msto(4).htrans>, <msto(4).haddr>, <msto(4).hwrite>, <msto(4).hsize>, <msto(4).hburst>, <msto(4).hprot>, <msto(4).hwdata>, <msto(4).hirq>, <msto(4).hconfig>, <msto(4).hindex>, <msto(3).hbusreq>, <msto(3).hlock>, <msto(3).htrans>, <msto(3).haddr>, <msto(3).hwrite>, <msto(3).hsize>, <msto(3).hburst>, <msto(3).hprot>, <msto(3).hwdata>, <msto(3).hirq>, <msto(3).hconfig>, <msto(3).hindex>, <msto(2).hbusreq>, <msto(2).hlock>, <msto(2).htrans>, <msto(2).haddr>, <msto(2).hwrite>, <msto(2).hsize>, <msto(2).hburst>, <msto(2).hprot>, <msto(2).hwdata>, <msto(2).hirq>, <msto(2).hconfig>,
   <msto(2).hindex>, <msto(1).hbusreq>, <msto(1).hlock>, <msto(1).htrans>, <msto(1).haddr>, <msto(1).hwrite>, <msto(1).hsize>, <msto(1).hburst>, <msto(1).hprot>, <msto(1).hwdata>, <msto(1).hirq>, <msto(1).hconfig>, <msto(1).hindex>, <msto(0).hbusreq>, <msto(0).hlock>, <msto(0).htrans>, <msto(0).haddr>, <msto(0).hwrite>, <msto(0).hsize>, <msto(0).hburst>, <msto(0).hprot>, <msto(0).hwdata>, <msto(0).hirq>, <msto(0).hconfig>, <msto(0).hindex>, <slvo(0).hconfig>, <slvo(1).hconfig>, <slvo(2).hconfig>, <slvo(3).hconfig>, <slvo(4).hconfig>, <slvo(5).hconfig>, <slvo(6).hconfig>, <slvo(7).hconfig>, <slvo(0).hirq>, <slvo(1).hirq>, <slvo(2).hirq>, <slvo(3).hirq>, <slvo(4).hirq>, <slvo(5).hirq>, <slvo(6).hirq>, <slvo(7).hirq>
INFO:Xst:2679 - Register <rin.ldefmst> in unit <ahbctrl> has a constant value of 0 during circuit operation. The register is replaced by logic.
Entity <ahbctrl> analyzed. Unit <ahbctrl> generated.

Analyzing generic Entity <leon3s> in library <gaisler> (Architecture <rtl>).
        cached = 0
        cp = 0
        dcen = 1
        disas = 0
        dlinesize = 4
        dlram = 0
        dlramsize = 1
        dlramstart = 143
        drepl = 0
        dsetlock = 0
        dsets = 1
        dsetsize = 4
        dsnoop = 1
        dsu = 1
        dtlbnum = 2
        fabtech = 11
        fpu = 0
        hindex = 0
        icen = 1
        ilinesize = 8
        ilram = 0
        ilramsize = 1
        ilramstart = 142
        irepl = 0
        isetlock = 0
        isets = 2
        isetsize = 4
        itlbnum = 2
        lddel = 1
        mac = 0
        memtech = 11
        mmuen = 0
        notag = 0
        nwindows = 8
        nwp = 2
        pclow = 2
        pwd = 0
        rstaddr = 0
        scantest = 0
        smp = 0
        svt = 1
        tbuf = 2
        tlb_rep = 1
        tlb_type = 1
        v8 = 50
WARNING:Xst:37 - Detected unknown constraint/property "sync_set_reset". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:753 - "../../lib/gaisler/leon3/leon3s.vhd" line 142: Unconnected output port 'iack_o' of component 'proc3'.
Entity <leon3s> analyzed. Unit <leon3s> generated.

Analyzing generic Entity <proc3> in library <gaisler> (Architecture <rtl>).
        cached = 0
        clk2x = 0
        cp = 0
        dcen = 1
        disas = 0
        dlinesize = 4
        dlram = 0
        dlramsize = 1
        dlramstart = 143
        drepl = 0
        dsetlock = 0
        dsets = 1
        dsetsize = 4
        dsnoop = 1
        dsu = 1
        dtlbnum = 2
        fabtech = 11
        fpu = 0
        hindex = 0
        icen = 1
        ilinesize = 8
        ilram = 0
        ilramsize = 1
        ilramstart = 142
        irepl = 0
        isetlock = 0
        isets = 2
        isetsize = 4
        itlbnum = 2
        lddel = 1
        mac = 0
        memtech = 11
        mmuen = 0
        notag = 0
        nwindows = 8
        nwp = 2
        pclow = 2
        pwd = 0
        rstaddr = 0
        scantest = 0
        smp = 0
        svt = 1
        tbuf = 2
        tlb_rep = 1
        tlb_type = 1
        v8 = 50
Entity <proc3> analyzed. Unit <proc3> generated.

Analyzing Entity <top> in library <gaisler> (Architecture <behavioral>).
Entity <top> analyzed. Unit <top> generated.

Analyzing Entity <my_mux> in library <gaisler> (Architecture <rtl>).
Entity <my_mux> analyzed. Unit <my_mux> generated.

Analyzing module <mips_core> in library <gaisler>.
Module <mips_core> is correct for synthesis.
 
Analyzing module <rf_stage> in library <gaisler>.
Module <rf_stage> is correct for synthesis.
 
Analyzing module <cal_cpi> in library <gaisler>.
Module <cal_cpi> is correct for synthesis.
 
Analyzing module <ctl_FSM> in library <gaisler>.
        ID_CUR = 32'sb00000000000000000000000000000001
        ID_LD = 32'sb00000000000000000000000000000101
        ID_MUL = 32'sb00000000000000000000000000000010
        ID_NOI = 32'sb00000000000000000000000000000110
        ID_RET = 32'sb00000000000000000000000000000100
        PC_IGN = 32'sb00000000000000000000000000000001
        PC_IRQ = 32'sb00000000000000000000000000000100
        PC_KEP = 32'sb00000000000000000000000000000010
        PC_RST = 32'sb00000000000000000000000000001000
WARNING:Xst:2725 - "../../lib/gaisler/vlog/ctl_fsm1.v" line 46: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../lib/gaisler/vlog/ctl_fsm1.v" line 47: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../lib/gaisler/vlog/ctl_fsm1.v" line 58: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../lib/gaisler/vlog/ctl_fsm1.v" line 71: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../lib/gaisler/vlog/ctl_fsm1.v" line 82: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../lib/gaisler/vlog/ctl_fsm1.v" line 91: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../lib/gaisler/vlog/ctl_fsm1.v" line 92: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../lib/gaisler/vlog/ctl_fsm1.v" line 93: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../lib/gaisler/vlog/ctl_fsm1.v" line 94: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../lib/gaisler/vlog/ctl_fsm1.v" line 95: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../lib/gaisler/vlog/ctl_fsm1.v" line 96: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../lib/gaisler/vlog/ctl_fsm1.v" line 104: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../lib/gaisler/vlog/ctl_fsm1.v" line 111: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../lib/gaisler/vlog/ctl_fsm1.v" line 119: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../lib/gaisler/vlog/ctl_fsm1.v" line 127: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../lib/gaisler/vlog/ctl_fsm1.v" line 134: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../lib/gaisler/vlog/ctl_fsm1.v" line 142: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../lib/gaisler/vlog/ctl_fsm1.v" line 150: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../../lib/gaisler/vlog/ctl_fsm1.v" line 158: Size mismatch between case item and case selector.
Module <ctl_FSM> is correct for synthesis.
 
Analyzing module <pc_gen> in library <gaisler>.
Module <pc_gen> is correct for synthesis.
 
Analyzing module <compare> in library <gaisler>.
Module <compare> is correct for synthesis.
 
Analyzing module <ext> in library <gaisler>.
Module <ext> is correct for synthesis.
 
Analyzing module <r32_reg_clr_cls> in library <gaisler>.
Module <r32_reg_clr_cls> is correct for synthesis.
 
Analyzing module <jack> in library <gaisler>.
Module <jack> is correct for synthesis.
 
Analyzing module <rd_sel> in library <gaisler>.
Module <rd_sel> is correct for synthesis.
 
Analyzing module <fwd_mux> in library <gaisler>.
Module <fwd_mux> is correct for synthesis.
 
Analyzing module <exec_stage> in library <gaisler>.
Module <exec_stage> is correct for synthesis.
 
Analyzing module <mips_alu> in library <gaisler>.
Module <mips_alu> is correct for synthesis.
 
Analyzing module <muldiv_ff> in library <gaisler>.
        OP_DIV = 32'sb00000000000000000000000000001011
        OP_DIVU = 32'sb00000000000000000000000000001010
        OP_MFHI = 32'sb00000000000000000000000000000110
        OP_MFLO = 32'sb00000000000000000000000000000111
        OP_MTHI = 32'sb00000000000000000000000000011111
        OP_MTLO = 32'sb00000000000000000000000000011110
        OP_MULT = 32'sb00000000000000000000000000001001
        OP_MULTU = 32'sb00000000000000000000000000001000
        OP_NONE = 32'sb00000000000000000000000000000000
"../../lib/gaisler/vlog/EXEC_stage.v" line 734: Found Parallel Case directive in module <muldiv_ff>.
Module <muldiv_ff> is correct for synthesis.
 
Analyzing module <shifter_tak> in library <gaisler>.
Module <shifter_tak> is correct for synthesis.
 
Analyzing module <alu> in library <gaisler>.
Module <alu> is correct for synthesis.
 
Analyzing module <add32> in library <gaisler>.
Module <add32> is correct for synthesis.
 
Analyzing module <alu_muxa> in library <gaisler>.
Module <alu_muxa> is correct for synthesis.
 
Analyzing module <alu_muxb> in library <gaisler>.
Module <alu_muxb> is correct for synthesis.
 
Analyzing module <r32_reg_cls> in library <gaisler>.
Module <r32_reg_cls> is correct for synthesis.
 
Analyzing module <r32_reg> in library <gaisler>.
Module <r32_reg> is correct for synthesis.
 
Analyzing module <r32_inst_reg> in library <gaisler>.
Module <r32_inst_reg> is correct for synthesis.
 
Analyzing module <r32_data_reg> in library <gaisler>.
Module <r32_data_reg> is correct for synthesis.
 
Analyzing module <decode_pipe> in library <gaisler>.
Module <decode_pipe> is correct for synthesis.
 
Analyzing module <decoder> in library <gaisler>.
"../../lib/gaisler/vlog/decode_pipe1.v" line 96: Found Parallel Case directive in module <decoder>.
"../../lib/gaisler/vlog/decode_pipe1.v" line 653: Found Parallel Case directive in module <decoder>.
"../../lib/gaisler/vlog/decode_pipe1.v" line 1044: $display : mtco
"../../lib/gaisler/vlog/decode_pipe1.v" line 1021: Found Parallel Case directive in module <decoder>.
"../../lib/gaisler/vlog/decode_pipe1.v" line 93: Found Parallel Case directive in module <decoder>.
Module <decoder> is correct for synthesis.
 
Analyzing module <pipelinedregs> in library <gaisler>.
Module <pipelinedregs> is correct for synthesis.
 
Analyzing module <muxb_ctl_reg_clr_cls> in library <gaisler>.
Module <muxb_ctl_reg_clr_cls> is correct for synthesis.
 
Analyzing module <wb_mux_ctl_reg_clr_cls> in library <gaisler>.
Module <wb_mux_ctl_reg_clr_cls> is correct for synthesis.
 
Analyzing module <wb_we_reg_clr_cls> in library <gaisler>.
Module <wb_we_reg_clr_cls> is correct for synthesis.
 
Analyzing module <wb_we_reg> in library <gaisler>.
Module <wb_we_reg> is correct for synthesis.
 
Analyzing module <wb_mux_ctl_reg_clr> in library <gaisler>.
Module <wb_mux_ctl_reg_clr> is correct for synthesis.
 
Analyzing module <muxb_ctl_reg_clr> in library <gaisler>.
Module <muxb_ctl_reg_clr> is correct for synthesis.
 
Analyzing module <dmem_ctl_reg_clr> in library <gaisler>.
Module <dmem_ctl_reg_clr> is correct for synthesis.
 
Analyzing module <alu_func_reg_clr> in library <gaisler>.
Module <alu_func_reg_clr> is correct for synthesis.
 
Analyzing module <muxa_ctl_reg_clr> in library <gaisler>.
Module <muxa_ctl_reg_clr> is correct for synthesis.
 
Analyzing module <wb_mux_ctl_reg> in library <gaisler>.
Module <wb_mux_ctl_reg> is correct for synthesis.
 
Analyzing module <wb_we_reg_clr> in library <gaisler>.
Module <wb_we_reg_clr> is correct for synthesis.
 
Analyzing module <cmp_ctl_reg_clr_cls> in library <gaisler>.
Module <cmp_ctl_reg_clr_cls> is correct for synthesis.
 
Analyzing module <alu_we_reg_clr> in library <gaisler>.
Module <alu_we_reg_clr> is correct for synthesis.
 
Analyzing module <alu_func_reg_clr_cls> in library <gaisler>.
Module <alu_func_reg_clr_cls> is correct for synthesis.
 
Analyzing module <dmem_ctl_reg_clr_cls> in library <gaisler>.
Module <dmem_ctl_reg_clr_cls> is correct for synthesis.
 
Analyzing module <ext_ctl_reg_clr_cls> in library <gaisler>.
Module <ext_ctl_reg_clr_cls> is correct for synthesis.
 
Analyzing module <rd_sel_reg_clr_cls> in library <gaisler>.
Module <rd_sel_reg_clr_cls> is correct for synthesis.
 
Analyzing module <alu_we_reg_clr_cls> in library <gaisler>.
Module <alu_we_reg_clr_cls> is correct for synthesis.
 
Analyzing module <muxa_ctl_reg_clr_cls> in library <gaisler>.
Module <muxa_ctl_reg_clr_cls> is correct for synthesis.
 
Analyzing module <pc_gen_ctl_reg_clr_cls> in library <gaisler>.
Module <pc_gen_ctl_reg_clr_cls> is correct for synthesis.
 
Analyzing module <dmem_ctl_reg> in library <gaisler>.
Module <dmem_ctl_reg> is correct for synthesis.
 
Analyzing module <forward> in library <gaisler>.
Module <forward> is correct for synthesis.
 
Analyzing module <forward_node> in library <gaisler>.
Module <forward_node> is correct for synthesis.
 
Analyzing module <fw_latch5> in library <gaisler>.
Module <fw_latch5> is correct for synthesis.
 
Analyzing module <r5_reg> in library <gaisler>.
Module <r5_reg> is correct for synthesis.
 
Analyzing module <wb_mux> in library <gaisler>.
Module <wb_mux> is correct for synthesis.
 
Analyzing module <hazard_unit> in library <gaisler>.
Module <hazard_unit> is correct for synthesis.
 
Analyzing module <r1_reg> in library <gaisler>.
Module <r1_reg> is correct for synthesis.
 
Analyzing generic Entity <mul32> in library <gaisler> (Architecture <rtl>).
        infer = 1
        mac = 0
        multype = 3
        pipe = 1
INFO:Xst:2679 - Register <rm.ready> in unit <mul32> has a constant value of 0 during circuit operation. The register is replaced by logic.
Entity <mul32> analyzed. Unit <mul32> generated.

Analyzing Entity <div32> in library <gaisler> (Architecture <rtl>).
Entity <div32> analyzed. Unit <div32> generated.

Analyzing generic Entity <cache> in library <gaisler> (Architecture <rtl>).
        cached = 0
        clk2x = 0
        dcen = 1
        dlinesize = 4
        dlram = 0
        dlramsize = 1
        dlramstart = 143
        drepl = 0
        dsetlock = 0
        dsets = 1
        dsetsize = 4
        dsnoop = 1
        dsu = 1
        hindex = 0
        icen = 1
        ilinesize = 8
        ilram = 0
        ilramsize = 1
        ilramstart = 142
        irepl = 0
        isetlock = 0
        isets = 2
        isetsize = 4
        memtech = 11
        scantest = 0
WARNING:Xst:753 - "../../lib/gaisler/leon3/cache.vhd" line 112: Unconnected output port 'mcmmo' of component 'mmu_acache'.
Entity <cache> analyzed. Unit <cache> generated.

Analyzing generic Entity <icache> in library <gaisler> (Architecture <rtl>).
        icen = 1
        ilinesize = 8
        irepl = 0
        isetlock = 0
        isets = 2
        isetsize = 4
        lram = 0
        lramsize = 1
        lramstart = 142
WARNING:Xst:790 - "../../lib/gaisler/leon3/icache.vhd" line 437: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "../../lib/gaisler/leon3/icache.vhd" line 438: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "../../lib/gaisler/leon3/icache.vhd" line 463: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "../../lib/gaisler/leon3/icache.vhd" line 474: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "../../lib/gaisler/leon3/icache.vhd" line 475: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "../../lib/gaisler/leon3/icache.vhd" line 478: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:819 - "../../lib/gaisler/leon3/icache.vhd" line 186: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
   <dco.icdiag.cctrl.ics>, <dco.icdiag.cctrl.burst>, <dco.icdiag.enable>, <dco.icdiag.addr>, <dco.icdiag.tag>, <dco.icdiag.read>, <dco.icdiag.flush>, <dco.icdiag.scanen>, <dco.icdiag.ilramen>
Entity <icache> analyzed. Unit <icache> generated.

Analyzing generic Entity <dcache> in library <gaisler> (Architecture <rtl>).
        cached = 0
        dcen = 1
        dlinesize = 4
        dlram = 0
        dlramsize = 1
        dlramstart = 143
        drepl = 0
        dsetlock = 0
        dsets = 1
        dsetsize = 4
        dsnoop = 1
        dsu = 1
        ilram = 0
        ilramstart = 142
        memtech = 11
WARNING:Xst:819 - "../../lib/gaisler/leon3/dcache.vhd" line 232: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
   <r.wb.addr>, <r.wb.data1>, <r.wb.data2>, <r.wb.size>, <r.wb.asi>, <r.wb.read>, <r.wb.lock>, <r.cctrl.burst>, <r.cctrl.dfrz>, <r.cctrl.ifrz>, <r.cctrl.dsnoop>, <r.cctrl.dcs>, <r.cctrl.ics>
Entity <dcache> analyzed. Unit <dcache> generated.

Analyzing generic Entity <mmu_acache> in library <gaisler> (Architecture <rtl>).
        cached = 0
        clk2x = 0
        hindex = 0
        ilinesize = 8
        scantest = 0
WARNING:Xst:819 - "../../lib/gaisler/leon3/mmu_acache.vhd" line 100: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
   <ahbso(15).hready>, <ahbso(15).hresp>, <ahbso(15).hrdata>, <ahbso(15).hsplit>, <ahbso(15).hcache>, <ahbso(15).hirq>, <ahbso(15).hconfig>, <ahbso(15).hindex>, <ahbso(14).hready>, <ahbso(14).hresp>, <ahbso(14).hrdata>, <ahbso(14).hsplit>, <ahbso(14).hcache>, <ahbso(14).hirq>, <ahbso(14).hconfig>, <ahbso(14).hindex>, <ahbso(13).hready>, <ahbso(13).hresp>, <ahbso(13).hrdata>, <ahbso(13).hsplit>, <ahbso(13).hcache>, <ahbso(13).hirq>, <ahbso(13).hconfig>, <ahbso(13).hindex>, <ahbso(12).hready>, <ahbso(12).hresp>, <ahbso(12).hrdata>, <ahbso(12).hsplit>, <ahbso(12).hcache>, <ahbso(12).hirq>, <ahbso(12).hconfig>, <ahbso(12).hindex>, <ahbso(11).hready>, <ahbso(11).hresp>, <ahbso(11).hrdata>, <ahbso(11).hsplit>, <ahbso(11).hcache>, <ahbso(11).hirq>, <ahbso(11).hconfig>, <ahbso(11).hindex>, <ahbso(10).hready>, <ahbso(10).hresp>, <ahbso(10).hrdata>, <ahbso(10).hsplit>, <ahbso(10).hcache>, <ahbso(10).hirq>, <ahbso(10).hconfig>, <ahbso(10).hindex>, <ahbso(9).hready>, <ahbso(9).hresp>, <ahbso(9).hrdata>,
   <ahbso(9).hsplit>, <ahbso(9).hcache>, <ahbso(9).hirq>, <ahbso(9).hconfig>, <ahbso(9).hindex>, <ahbso(8).hready>, <ahbso(8).hresp>, <ahbso(8).hrdata>, <ahbso(8).hsplit>, <ahbso(8).hcache>, <ahbso(8).hirq>, <ahbso(8).hconfig>, <ahbso(8).hindex>, <ahbso(7).hready>, <ahbso(7).hresp>, <ahbso(7).hrdata>, <ahbso(7).hsplit>, <ahbso(7).hcache>, <ahbso(7).hirq>, <ahbso(7).hconfig>, <ahbso(7).hindex>, <ahbso(6).hready>, <ahbso(6).hresp>, <ahbso(6).hrdata>, <ahbso(6).hsplit>, <ahbso(6).hcache>, <ahbso(6).hirq>, <ahbso(6).hconfig>, <ahbso(6).hindex>, <ahbso(5).hready>, <ahbso(5).hresp>, <ahbso(5).hrdata>, <ahbso(5).hsplit>, <ahbso(5).hcache>, <ahbso(5).hirq>, <ahbso(5).hconfig>, <ahbso(5).hindex>, <ahbso(4).hready>, <ahbso(4).hresp>, <ahbso(4).hrdata>, <ahbso(4).hsplit>, <ahbso(4).hcache>, <ahbso(4).hirq>, <ahbso(4).hconfig>, <ahbso(4).hindex>, <ahbso(3).hready>, <ahbso(3).hresp>, <ahbso(3).hrdata>, <ahbso(3).hsplit>, <ahbso(3).hcache>, <ahbso(3).hirq>, <ahbso(3).hconfig>, <ahbso(3).hindex>, <ahbso(2).hready>,
   <ahbso(2).hresp>, <ahbso(2).hrdata>, <ahbso(2).hsplit>, <ahbso(2).hcache>, <ahbso(2).hirq>, <ahbso(2).hconfig>, <ahbso(2).hindex>, <ahbso(1).hready>, <ahbso(1).hresp>, <ahbso(1).hrdata>, <ahbso(1).hsplit>, <ahbso(1).hcache>, <ahbso(1).hirq>, <ahbso(1).hconfig>, <ahbso(1).hindex>, <ahbso(0).hready>, <ahbso(0).hresp>, <ahbso(0).hrdata>, <ahbso(0).hsplit>, <ahbso(0).hcache>, <ahbso(0).hirq>, <ahbso(0).hconfig>, <ahbso(0).hindex>
Entity <mmu_acache> analyzed. Unit <mmu_acache> generated.

Analyzing generic Entity <regfile_3p> in library <techmap> (Architecture <rtl>).
        abits = 5
        dbits = 32
        numregs = 32
        tech = 11
        wrfst = 1
Entity <regfile_3p> analyzed. Unit <regfile_3p> generated.

Analyzing generic Entity <generic_regfile_3p> in library <techmap> (Architecture <rtl>).
        abits = 5
        dbits = 32
        numregs = 32
        tech = 11
        wrfst = 1
Entity <generic_regfile_3p> analyzed. Unit <generic_regfile_3p> generated.

Analyzing generic Entity <cachemem> in library <gaisler> (Architecture <rtl>).
        dcen = 1
        dlinesize = 4
        dlram = 0
        dlramsize = 1
        drepl = 0
        dsetlock = 0
        dsets = 1
        dsetsize = 4
        dsnoop = 1
        icen = 1
        ilinesize = 8
        ilram = 0
        ilramsize = 1
        irepl = 0
        isetlock = 0
        isets = 2
        isetsize = 4
        mmuen = 0
        tech = 11
WARNING:Xst:819 - "../../lib/gaisler/leon3/cachemem.vhd" line 163: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
   <crami.icramin.data>, <crami.dcramin.tag>, <crami.dcramin.data>, <crami.dcramin.ptag>, <crami.icramin.tag>, <crami.icramin.flush>
WARNING:Xst:752 - "../../lib/gaisler/leon3/cachemem.vhd" line 245: Unconnected input port 'testin' of component 'syncram' is tied to default value.
WARNING:Xst:752 - "../../lib/gaisler/leon3/cachemem.vhd" line 247: Unconnected input port 'testin' of component 'syncram' is tied to default value.
WARNING:Xst:752 - "../../lib/gaisler/leon3/cachemem.vhd" line 245: Unconnected input port 'testin' of component 'syncram' is tied to default value.
WARNING:Xst:752 - "../../lib/gaisler/leon3/cachemem.vhd" line 247: Unconnected input port 'testin' of component 'syncram' is tied to default value.
WARNING:Xst:752 - "../../lib/gaisler/leon3/cachemem.vhd" line 283: Unconnected input port 'testin' of component 'syncram_dp' is tied to default value.
WARNING:Xst:752 - "../../lib/gaisler/leon3/cachemem.vhd" line 316: Unconnected input port 'testin' of component 'syncram' is tied to default value.
Entity <cachemem> analyzed. Unit <cachemem> generated.

Analyzing generic Entity <syncram.1> in library <techmap> (Architecture <rtl>).
        abits = 7
        dbits = 28
        tech = 11
Entity <syncram.1> analyzed. Unit <syncram.1> generated.

Analyzing generic Entity <virtex2_syncram.1> in library <techmap> (Architecture <behav>).
        abits = 7
        dbits = 28
WARNING:Xst:2211 - "../../lib/techmap/unisim/memory_unisim.vhd" line 544: Instantiating black box module <RAMB16_S36_S36>.
Entity <virtex2_syncram.1> analyzed. Unit <virtex2_syncram.1> generated.

Analyzing generic Entity <syncram.2> in library <techmap> (Architecture <rtl>).
        abits = 10
        dbits = 32
        tech = 11
Entity <syncram.2> analyzed. Unit <syncram.2> generated.

Analyzing generic Entity <virtex2_syncram.2> in library <techmap> (Architecture <behav>).
        abits = 10
        dbits = 32
WARNING:Xst:2211 - "../../lib/techmap/unisim/memory_unisim.vhd" line 565: Instantiating black box module <RAMB16_S18>.
WARNING:Xst:2211 - "../../lib/techmap/unisim/memory_unisim.vhd" line 565: Instantiating black box module <RAMB16_S18>.
Entity <virtex2_syncram.2> analyzed. Unit <virtex2_syncram.2> generated.

Analyzing generic Entity <syncram_dp> in library <techmap> (Architecture <rtl>).
        abits = 8
        dbits = 24
        tech = 11
Entity <syncram_dp> analyzed. Unit <syncram_dp> generated.

Analyzing generic Entity <virtex2_syncram_dp> in library <techmap> (Architecture <behav>).
        abits = 8
        dbits = 24
WARNING:Xst:2211 - "../../lib/techmap/unisim/memory_unisim.vhd" line 793: Instantiating black box module <RAMB16_S36_S36>.
Entity <virtex2_syncram_dp> analyzed. Unit <virtex2_syncram_dp> generated.

Analyzing generic Entity <tbufmem> in library <gaisler> (Architecture <rtl>).
        tbuf = 2
        tech = 11
Entity <tbufmem> analyzed. Unit <tbufmem> generated.

Analyzing generic Entity <syncram64> in library <techmap> (Architecture <rtl>).
        abits = 7
        tech = 11
Entity <syncram64> analyzed. Unit <syncram64> generated.

Analyzing generic Entity <virtex2_syncram64> in library <techmap> (Architecture <behav>).
        abits = 7
WARNING:Xst:753 - "../../lib/techmap/unisim/memory_unisim.vhd" line 1028: Unconnected output port 'DOPA' of component 'RAMB16_S36_S36'.
WARNING:Xst:753 - "../../lib/techmap/unisim/memory_unisim.vhd" line 1028: Unconnected output port 'DOPB' of component 'RAMB16_S36_S36'.
WARNING:Xst:2211 - "../../lib/techmap/unisim/memory_unisim.vhd" line 1028: Instantiating black box module <RAMB16_S36_S36>.
Entity <virtex2_syncram64> analyzed. Unit <virtex2_syncram64> generated.

Analyzing generic Entity <odpad> in library <techmap> (Architecture <rtl>).
        level = 0
        oepol = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3
Entity <odpad> analyzed. Unit <odpad> generated.

Analyzing generic Entity <virtex_toutpad> in library <techmap> (Architecture <rtl>).
        level = 0
        slew = 0
        strength = 12
        voltage = 3
WARNING:Xst:2211 - "../../lib/techmap/unisim/pads_unisim.vhd" line 251: Instantiating black box module <OBUFT>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <ttl0.slow0.op> in unit <virtex_toutpad>.
    Set user-defined property "DRIVE =  12" for instance <ttl0.slow0.op> in unit <virtex_toutpad>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <ttl0.slow0.op> in unit <virtex_toutpad>.
    Set user-defined property "SLEW =  SLOW" for instance <ttl0.slow0.op> in unit <virtex_toutpad>.
Entity <virtex_toutpad> analyzed. Unit <virtex_toutpad> generated.

Analyzing generic Entity <dsu3> in library <gaisler> (Architecture <rtl>).
        haddr = 2304
        hindex = 2
        hmask = 3840
        irq = 0
        kbytes = 0
        ncpu = 1
        tbits = 30
        tech = 11
Entity <dsu3> analyzed. Unit <dsu3> generated.

Analyzing generic Entity <dsu3x> in library <gaisler> (Architecture <rtl>).
        clk2x = 0
        haddr = 2304
        hindex = 2
        hmask = 3840
        irq = 0
        kbytes = 0
        ncpu = 1
        tbits = 30
        tech = 11
WARNING:Xst:819 - "../../lib/gaisler/leon3/dsu3x.vhd" line 164: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
   <r.slv.hsel>, <r.slv.haddr>, <r.slv.hwrite>, <r.slv.hwdata>, <r.slv.hrdata>, <r.slv.hready>, <r.slv.hready2>, <tr.tbreg1.addr>, <tr.tbreg1.mask>, <tr.tbreg1.read>, <tr.tbreg1.write>, <tr.tbreg2.addr>, <tr.tbreg2.mask>, <tr.tbreg2.read>, <tr.tbreg2.write>, <dbgi(0).dsumode>, <dbgi(0).idle>, <dbgi(0).ipend>, <dbgi(0).dsu>, <dbgi(0).error>, <dbgi(0).halt>, <dbgi(0).pwd>, <dbgi(0).data>, <dbgi(0).crdy>
Entity <dsu3x> analyzed. Unit <dsu3x> generated.

Analyzing generic Entity <outpad.2> in library <techmap> (Architecture <rtl>).
        level = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3
Entity <outpad.2> analyzed. Unit <outpad.2> generated.

Analyzing generic Entity <virtex_outpad.2> in library <techmap> (Architecture <rtl>).
        level = 0
        slew = 0
        strength = 12
        voltage = 3
WARNING:Xst:2211 - "../../lib/techmap/unisim/pads_unisim.vhd" line 178: Instantiating black box module <OBUF>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <ttl0.slow0.op> in unit <virtex_outpad.2>.
    Set user-defined property "DRIVE =  12" for instance <ttl0.slow0.op> in unit <virtex_outpad.2>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <ttl0.slow0.op> in unit <virtex_outpad.2>.
    Set user-defined property "SLEW =  SLOW" for instance <ttl0.slow0.op> in unit <virtex_outpad.2>.
Entity <virtex_outpad.2> analyzed. Unit <virtex_outpad.2> generated.

Analyzing generic Entity <ahbuart> in library <gaisler> (Architecture <struct>).
        hindex = 1
        paddr = 7
        pindex = 7
        pmask = 4095
Entity <ahbuart> analyzed. Unit <ahbuart> generated.

Analyzing generic Entity <ahbmst.1> in library <gaisler> (Architecture <rtl>).
        chprot = 3
        devid = 7
        hindex = 1
        hirq = 0
        incaddr = 0
        venid = 1
        version = 0
Entity <ahbmst.1> analyzed. Unit <ahbmst.1> generated.

Analyzing generic Entity <dcom_uart> in library <gaisler> (Architecture <rtl>).
        paddr = 7
        pindex = 7
        pmask = 4095
Entity <dcom_uart> analyzed. Unit <dcom_uart> generated.

Analyzing Entity <dcom> in library <gaisler> (Architecture <struct>).
Entity <dcom> analyzed. Unit <dcom> generated.

Analyzing generic Entity <ahbjtag> in library <gaisler> (Architecture <struct>).
        ainst = 2
        dinst = 3
        hindex = 2
        idcode = 9
        manf = 804
        nsync = 1
        part = 0
        scantest = 0
        tech = 11
        ver = 0
Entity <ahbjtag> analyzed. Unit <ahbjtag> generated.

Analyzing generic Entity <ahbmst.2> in library <gaisler> (Architecture <rtl>).
        chprot = 3
        devid = 28
        hindex = 2
        hirq = 0
        incaddr = 0
        venid = 1
        version = 0
Entity <ahbmst.2> analyzed. Unit <ahbmst.2> generated.

Analyzing generic Entity <tap> in library <techmap> (Architecture <rtl>).
        idcode = 9
        irlen = 6
        manf = 804
        part = 0
        scantest = 0
        tech = 11
        trsten = 1
        ver = 0
Entity <tap> analyzed. Unit <tap> generated.

Analyzing Entity <spartan3_tap> in library <techmap> (Architecture <rtl>).
WARNING:Xst:2211 - "../../lib/techmap/unisim/tap_unisim.vhd" line 186: Instantiating black box module <BSCAN_SPARTAN3>.
    Set user-defined property "dont_touch =  TRUE" for instance <u0> in unit <spartan3_tap>.
Entity <spartan3_tap> analyzed. Unit <spartan3_tap> generated.

Analyzing generic Entity <jtagcom> in library <gaisler> (Architecture <rtl>).
        ainst = 2
        dinst = 3
        isel = 1
        nsync = 1
Entity <jtagcom> analyzed. Unit <jtagcom> generated.

Analyzing generic Entity <mctrl> in library <esa> (Architecture <rtl>).
        fast = 0
        hindex = 0
        invclk = 0
        ioaddr = 512
        iomask = 3584
        mobile = 0
        oepol = 0
        paddr = 0
        pageburst = 1
        pindex = 0
        pmask = 4095
        ram16 = 0
        ram8 = 1
        ramaddr = 1024
        rammask = 3072
        romaddr = 0
        romasel = 28
        rommask = 3584
        scantest = 0
        sdbits = 32
        sden = 1
        sdlsb = 2
        sdrasel = 29
        sepbus = 0
        srbanks = 2
        syncrst = 0
        wprot = 0
    Set property "syn_preserve = TRUE" for signal <rbdrive>.
    Set property "syn_preserve = TRUE" for signal <rrsbdrive>.
    Set property "syn_preserve = TRUE" for signal <rsbdrive>.
INFO:Xst:1561 - "../../lib/esa/memoryctrl/mctrl.vhd" line 724: Mux is complete : default of case is discarded
WARNING:Xst:819 - "../../lib/esa/memoryctrl/mctrl.vhd" line 207: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
   <r.mcfg1.romrws>, <r.mcfg1.romwws>, <r.mcfg1.romwidth>, <r.mcfg1.romwrite>, <r.mcfg1.ioen>, <r.mcfg1.iows>, <r.mcfg1.bexcen>, <r.mcfg1.brdyen>, <r.mcfg1.iowidth>, <r.mcfg2.ramrws>, <r.mcfg2.ramwws>, <r.mcfg2.ramwidth>, <r.mcfg2.rambanksz>, <r.mcfg2.rmw>, <r.mcfg2.brdyen>, <r.mcfg2.srdis>, <r.mcfg2.sdren>
Entity <mctrl> analyzed. Unit <mctrl> generated.

Analyzing generic Entity <sdmctrl> in library <gaisler> (Architecture <rtl>).
        fast = 0
        invclk = 0
        mobile = 0
        pageburst = 1
        pindex = 0
        sdbits = 32
        wprot = 0
WARNING:Xst:819 - "../../lib/gaisler/memctrl/sdmctrl.vhd" line 131: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
   <r.cfg.command>, <r.cfg.csize>, <r.cfg.bsize>, <r.cfg.casdel>, <r.cfg.trfc>, <r.cfg.trp>, <r.cfg.refresh>, <r.cfg.renable>, <r.cfg.pageburst>, <r.cfg.mobileen>, <r.cfg.ds>, <r.cfg.tcsr>, <r.cfg.pasr>, <r.cfg.pmode>, <r.cfg.txsr>, <r.cfg.cke>
INFO:Xst:2679 - Register <r.bsel> in unit <sdmctrl> has a constant value of 0 during circuit operation. The register is replaced by logic.
Entity <sdmctrl> analyzed. Unit <sdmctrl> generated.

Analyzing generic Entity <outpadv.1> in library <techmap> (Architecture <rtl>).
        level = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3
        width = 4
Entity <outpadv.1> analyzed. Unit <outpadv.1> generated.

Analyzing generic Entity <outpad.3> in library <techmap> (Architecture <rtl>).
        level = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3
Entity <outpad.3> analyzed. Unit <outpad.3> generated.

Analyzing generic Entity <outpadv.2> in library <techmap> (Architecture <rtl>).
        level = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3
        width = 2
Entity <outpadv.2> analyzed. Unit <outpadv.2> generated.

Analyzing generic Entity <outpadv.3> in library <techmap> (Architecture <rtl>).
        level = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3
        width = 28
Entity <outpadv.3> analyzed. Unit <outpadv.3> generated.

Analyzing generic Entity <outpadv.4> in library <techmap> (Architecture <rtl>).
        level = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3
        width = 5
Entity <outpadv.4> analyzed. Unit <outpadv.4> generated.

Analyzing generic Entity <iopadv> in library <techmap> (Architecture <rtl>).
        level = 0
        oepol = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3
        width = 8
Entity <iopadv> analyzed. Unit <iopadv> generated.

Analyzing generic Entity <iopad.2> in library <techmap> (Architecture <rtl>).
        level = 0
        oepol = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3
Entity <iopad.2> analyzed. Unit <iopad.2> generated.

Analyzing generic Entity <virtex_iopad> in library <techmap> (Architecture <rtl>).
        level = 0
        slew = 0
        strength = 12
        voltage = 3
WARNING:Xst:2211 - "../../lib/techmap/unisim/pads_unisim.vhd" line 106: Instantiating black box module <IOBUF>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <ttl0.slow0.op> in unit <virtex_iopad>.
    Set user-defined property "DRIVE =  12" for instance <ttl0.slow0.op> in unit <virtex_iopad>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <ttl0.slow0.op> in unit <virtex_iopad>.
    Set user-defined property "SLEW =  SLOW" for instance <ttl0.slow0.op> in unit <virtex_iopad>.
Entity <virtex_iopad> analyzed. Unit <virtex_iopad> generated.

Analyzing generic Entity <apbctrl> in library <grlib> (Architecture <rtl>).
        asserterr = 0
        assertwarn = 0
        debug = 2
        enbusmon = 0
        haddr = 2048
        hindex = 1
        hmask = 4095
        icheck = 1
        nslaves = 16
        pslvdisable = 0
WARNING:Xst:819 - "../../lib/grlib/amba/apbctrl.vhd" line 91: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
   <apbo(0).pconfig>, <apbo(1).pconfig>, <apbo(2).pconfig>, <apbo(3).pconfig>, <apbo(4).pconfig>, <apbo(5).pconfig>, <apbo(6).pconfig>, <apbo(7).pconfig>, <apbo(8).pconfig>, <apbo(9).pconfig>, <apbo(10).pconfig>, <apbo(11).pconfig>, <apbo(12).pconfig>, <apbo(13).pconfig>, <apbo(14).pconfig>, <apbo(15).pconfig>, <apbo(0).pirq>, <apbo(1).pirq>, <apbo(2).pirq>, <apbo(3).pirq>, <apbo(4).pirq>, <apbo(5).pirq>, <apbo(6).pirq>, <apbo(7).pirq>, <apbo(8).pirq>, <apbo(9).pirq>, <apbo(10).pirq>, <apbo(11).pirq>, <apbo(12).pirq>, <apbo(13).pirq>, <apbo(14).pirq>, <apbo(15).pirq>
Entity <apbctrl> analyzed. Unit <apbctrl> generated.

Analyzing generic Entity <apbuart> in library <gaisler> (Architecture <rtl>).
        abits = 8
        console = 0
        fifosize = 4
        flow = 1
        paddr = 1
        parity = 1
        pindex = 1
        pirq = 2
        pmask = 4095
Entity <apbuart> analyzed. Unit <apbuart> generated.

Analyzing generic Entity <irqmp> in library <gaisler> (Architecture <rtl>).
        eirq = 0
        ncpu = 1
        paddr = 2
        pindex = 2
        pmask = 4095
WARNING:Xst:819 - "../../lib/gaisler/leon3/irqmp.vhd" line 101: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
   <irqi(0).pwd>, <irqi(0).intack>, <irqi(0).irl>
Entity <irqmp> analyzed. Unit <irqmp> generated.

Analyzing generic Entity <gptimer> in library <gaisler> (Architecture <rtl>).
        nbits = 32
        ntimers = 2
        paddr = 3
        pindex = 3
        pirq = 8
        pmask = 4095
        sbits = 8
        sepirq = 1
        wdog = 0
WARNING:Xst:819 - "../../lib/gaisler/misc/gptimer.vhd" line 100: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
   <r.timers(1).enable>, <r.timers(1).load>, <r.timers(1).restart>, <r.timers(1).irqpen>, <r.timers(1).irqen>, <r.timers(1).irq>, <r.timers(1).chain>, <r.timers(1).value>, <r.timers(1).reload>, <r.timers(2).enable>, <r.timers(2).load>, <r.timers(2).restart>, <r.timers(2).irqpen>, <r.timers(2).irqen>, <r.timers(2).irq>, <r.timers(2).chain>, <r.timers(2).value>, <r.timers(2).reload>
Entity <gptimer> analyzed. Unit <gptimer> generated.

Analyzing generic Entity <iopad.1> in library <techmap> (Architecture <rtl>).
        level = 0
        oepol = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3
Entity <iopad.1> analyzed. Unit <iopad.1> generated.

Analyzing generic Entity <outpadv.5> in library <techmap> (Architecture <rtl>).
        level = 0
        slew = 0
        strength = 12
        tech = 11
        voltage = 3
        width = 8
Entity <outpadv.5> analyzed. Unit <outpadv.5> generated.

Analyzing generic Entity <grgpio> in library <gaisler> (Architecture <rtl>).
        bpdir = 0
        bypass = 0
        imask = 0
        nbits = 18
        oepol = 0
        paddr = 8
        pindex = 8
        pmask = 4095
        scantest = 0
        syncrst = 0
Entity <grgpio> analyzed. Unit <grgpio> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...
INFO:Xst:2679 - Register <r.ldefmst> in unit <ahbctrl> has a constant value of 0 during circuit operation. The register is replaced by logic.

Synthesizing Unit <rstgen>.
    Related source file is "../../lib/gaisler/misc/rstgen.vhd".
WARNING:Xst:647 - Input <testrst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <testen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 5-bit register for signal <r>.
    Found 1-bit register for signal <rstoutl>.
    Summary:
        inferred   6 D-type flip-flop(s).
Unit <rstgen> synthesized.


Synthesizing Unit <ahbctrl>.
    Related source file is "../../lib/grlib/amba/ahbctrl.vhd".
WARNING:Xst:647 - Input <slvo(9).hsplit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(12).hwdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(15).haddr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(9).hready> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(10).hprot> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(3).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(8).hsplit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(11).hwdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(13).hsize> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(10).haddr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(8).hready> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(2).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(14).hconfig> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(14).hbusreq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(9).hconfig> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(9).hbusreq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(7).hsplit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(9).hwrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(8).hlock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(10).hwdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(1).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(6).hsplit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(8).hwrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(0).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(13).hconfig> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(5).hprot> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(8).hresp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(5).hsplit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(7).hwrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(15).hlock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(8).hsize> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(5).haddr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(15).hburst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(15).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(4).hsplit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(6).hwrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(13).hresp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(10).hlock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(14).hburst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(12).hprot> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(15).hrdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(3).hsplit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(14).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(5).hwrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(13).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(15).hsize> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(13).hconfig> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(13).hburst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(12).haddr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(13).hbusreq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(14).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(9).hcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(14).hrdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(8).hconfig> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(2).hsplit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(13).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(8).hbusreq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(4).hwrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(9).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(10).hsize> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(10).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(9).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(12).hburst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(8).hcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(13).hrdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(15).hsplit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(1).hsplit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(11).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(12).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(5).hlock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(15).hready> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(6).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(8).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(11).hburst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(12).hconfig> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(12).hrdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(14).hsplit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(0).hsplit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(11).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(7).hprot> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(14).hready> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(7).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(3).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(10).hburst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(11).hrdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(13).hsplit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(7).haddr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(10).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(9).htrans> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(15).hresp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(13).hready> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(12).hlock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(6).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(5).hsize> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(10).hrdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(12).hsplit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(8).htrans> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(14).hprot> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(8).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(10).hresp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(12).hready> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(5).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(12).hconfig> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(12).hbusreq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(7).hconfig> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(11).hsplit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(14).haddr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(7).hbusreq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(7).htrans> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(11).hready> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(9).hconfig> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(15).hwrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(4).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(12).hsize> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(10).hsplit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(6).htrans> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(10).hready> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(14).hwrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(3).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(7).hlock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(11).hconfig> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(5).htrans> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(9).hprot> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(13).hwrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(2).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(15).hcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(4).htrans> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(9).hwdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(9).haddr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(14).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(4).hprot> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(12).hwrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(15).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(1).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(14).hlock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(14).hcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(15).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(7).hsize> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(8).hwdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(4).haddr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(11).hwrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(14).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(11).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(0).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(11).hconfig> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(12).hresp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(11).hbusreq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(13).hcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(6).hconfig> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(6).hbusreq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(12).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(7).hwdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(11).hprot> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(7).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(8).hconfig> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(10).hwrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(13).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(12).hcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(6).hwdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(14).hsize> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(11).haddr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(12).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(10).hconfig> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(4).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(11).hcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(9).hlock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(5).hwdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(11).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(10).hcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(4).hlock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(4).hwdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(9).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(15).htrans> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(10).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(6).hprot> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(9).hresp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(9).hsize> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(14).htrans> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(6).haddr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(10).hconfig> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(10).hbusreq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(5).hconfig> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(14).hresp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(11).hlock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(5).hbusreq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(15).hconfig> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(4).hsize> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(13).htrans> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(13).hprot> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(9).hburst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(9).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(12).htrans> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(13).haddr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(8).hburst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(8).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(11).hsize> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(15).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(11).htrans> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(7).hburst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(7).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(15).hconfig> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(15).hbusreq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(6).hlock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(10).htrans> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(15).hwdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(12).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(6).hburst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(8).hprot> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(6).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(13).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(9).hrdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(8).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(14).hwdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(5).hburst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(8).haddr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(4).hconfig> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(5).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(4).hbusreq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(14).hconfig> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(13).hlock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(8).hrdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(10).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(13).hwdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(6).hsize> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(4).hburst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(5).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(15).hprot> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <msto(4).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slvo(11).hresp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <rsplitin> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <rsplit> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <rin.defmst> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <r.haddr<15:11>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <r.beat> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 16x3-bit ROM for signal <bco_lsb$rom0000> created at line 160.
    Found 16x3-bit ROM for signal <bco_msb$rom0000> created at line 161.
    Found 3-bit 4-to-1 multiplexer for signal <slvi.hsize>.
    Found 1-bit 4-to-1 multiplexer for signal <slvi.hwrite>.
    Found 4-bit 4-to-1 multiplexer for signal <slvi.hprot>.
    Found 32-bit 4-to-1 multiplexer for signal <slvi.hwdata>.
    Found 32-bit 4-to-1 multiplexer for signal <msti.hrdata>.
    Found 2-bit 4-to-1 multiplexer for signal <$mux0000> created at line 374.
    Found 3-bit 4-to-1 multiplexer for signal <$mux0001> created at line 377.
    Found 32-bit 8-to-1 multiplexer for signal <$varindex0000> created at line 495.
    Found 1-bit 4-to-1 multiplexer for signal <arb$mux0000> created at line 379.
    Found 32-bit 4-to-1 multiplexer for signal <haddr$mux0000> created at line 365.
    Found 12-bit comparator equal for signal <hmbsel$cmp_eq0000> created at line 421.
    Found 12-bit comparator equal for signal <hmbsel_0$cmp_eq0000> created at line 421.
    Found 12-bit comparator equal for signal <hmbsel_0$cmp_eq0004> created at line 421.
    Found 12-bit comparator equal for signal <hmbsel_0$cmp_eq0005> created at line 421.
    Found 12-bit comparator equal for signal <hmbsel_1$cmp_eq0000> created at line 421.
    Found 12-bit comparator equal for signal <hmbsel_1$cmp_eq0002> created at line 421.
    Found 12-bit comparator equal for signal <hmbsel_1$cmp_eq0005> created at line 421.
    Found 12-bit comparator equal for signal <hmbsel_2$cmp_eq0000> created at line 421.
    Found 12-bit comparator equal for signal <hmbsel_2$cmp_eq0002> created at line 421.
    Found 12-bit comparator equal for signal <hmbsel_3$cmp_eq0000> created at line 421.
    Found 12-bit comparator equal for signal <hsel_1$cmp_eq0000> created at line 421.
    Found 12-bit comparator equal for signal <hsel_1$cmp_eq0001> created at line 421.
    Found 12-bit comparator equal for signal <hsel_1$cmp_eq0003> created at line 421.
    Found 12-bit comparator equal for signal <hsel_1$cmp_eq0007> created at line 421.
    Found 12-bit comparator equal for signal <hsel_2$cmp_eq0000> created at line 421.
    Found 12-bit comparator equal for signal <hsel_2$cmp_eq0001> created at line 421.
    Found 12-bit comparator equal for signal <hsel_2$cmp_eq0003> created at line 421.
    Found 12-bit comparator equal for signal <hsel_2$cmp_eq0007> created at line 421.
    Found 12-bit comparator equal for signal <hsel_3$cmp_eq0000> created at line 421.
    Found 12-bit comparator equal for signal <hsel_3$cmp_eq0001> created at line 421.
    Found 12-bit comparator equal for signal <hsel_3$cmp_eq0005> created at line 421.
    Found 12-bit comparator equal for signal <hsel_4$cmp_eq0000> created at line 421.
    Found 12-bit comparator equal for signal <hsel_4$cmp_eq0003> created at line 421.
    Found 12-bit comparator equal for signal <hsel_5$cmp_eq0001> created at line 421.
    Found 12-bit comparator equal for signal <hsel_6$cmp_eq0000> created at line 421.
    Found 12-bit comparator equal for signal <hsel_6$cmp_eq0002> created at line 421.
    Found 12-bit comparator equal for signal <hsel_6$cmp_eq0006> created at line 421.
    Found 12-bit comparator equal for signal <hsel_6$cmp_eq0010> created at line 421.
    Found 12-bit comparator equal for signal <hsel_7$cmp_eq0000> created at line 421.
    Found 12-bit comparator equal for signal <hsel_7$cmp_eq0001> created at line 421.
    Found 12-bit comparator equal for signal <hsel_7$cmp_eq0003> created at line 421.
    Found 12-bit comparator equal for signal <hsel_7$cmp_eq0007> created at line 421.
    Found 32-bit 8-to-1 multiplexer for signal <msti.hrdata$mux0000>.
    Found 1-bit register for signal <r.cfga11>.
    Found 1-bit register for signal <r.cfgsel>.
    Found 1-bit register for signal <r.defslv>.
    Found 14-bit register for signal <r.haddr>.
    Found 2-bit register for signal <r.hmaster>.
    Found 2-bit register for signal <r.hmasterd>.
    Found 1-bit register for signal <r.hmasterlock>.
    Found 1-bit register for signal <r.hmasterlockd>.
    Found 32-bit register for signal <r.hrdatam>.
    Found 32-bit register for signal <r.hrdatas>.
    Found 1-bit register for signal <r.hready>.
    Found 3-bit register for signal <r.hslave>.
    Found 2-bit register for signal <r.htrans>.
    Found 2-bit comparator greatequal for signal <rrvec_1$cmp_le0000> created at line 274.
    Found 2-bit comparator greatequal for signal <rrvec_2$cmp_le0000> created at line 274.
    Found 2-bit comparator greatequal for signal <rrvec_3$cmp_le0000> created at line 274.
    Found 1-bit 4-to-1 multiplexer for signal <v.hmasterlock$mux0000> created at line 557.
    Found 32-bit 4-to-1 multiplexer for signal <v.hrdatam$mux0000<255>> created at line 486.
    Found 256-bit 8-to-1 multiplexer for signal <v.hrdatas$mux0000<255:248>> created at line 495.
    Summary:
        inferred   2 ROM(s).
        inferred  93 D-type flip-flop(s).
        inferred  35 Comparator(s).
        inferred 463 Multiplexer(s).
Unit <ahbctrl> synthesized.


Synthesizing Unit <apbctrl>.
    Related source file is "../../lib/grlib/amba/apbctrl.vhd".
WARNING:Xst:647 - Input <apbo(9).pindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbo(8).pindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbo(7).pindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbo(6).pindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.hmastlock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbo(5).pindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbo(4).pindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.hcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.hburst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbo(3).pindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.hmbsel> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbo(2).pindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbo(1).pindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbo(15).pindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbo(0).pindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbo(14).pindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.hsel<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.hsel<2:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbo(13).pindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbo(12).pindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbo(11).pindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbo(10).pindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.hsize> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.hprot> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.haddr<31:20>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.hmaster> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Using one-hot encoding for signal <r.state>.
    Found 12-bit comparator equal for signal <psel_0$cmp_eq0001> created at line 130.
    Found 12-bit comparator equal for signal <psel_1$cmp_eq0001> created at line 130.
    Found 12-bit comparator equal for signal <psel_10$cmp_eq0001> created at line 130.
    Found 12-bit comparator equal for signal <psel_11$cmp_eq0001> created at line 130.
    Found 12-bit comparator equal for signal <psel_12$cmp_eq0001> created at line 130.
    Found 12-bit comparator equal for signal <psel_13$cmp_eq0001> created at line 130.
    Found 12-bit comparator equal for signal <psel_14$cmp_eq0001> created at line 130.
    Found 12-bit comparator equal for signal <psel_15$cmp_eq0001> created at line 130.
    Found 12-bit comparator equal for signal <psel_2$cmp_eq0001> created at line 130.
    Found 12-bit comparator equal for signal <psel_3$cmp_eq0001> created at line 130.
    Found 12-bit comparator equal for signal <psel_7$cmp_eq0001> created at line 130.
    Found 12-bit comparator equal for signal <psel_8$cmp_eq0001> created at line 130.
    Found 1-bit register for signal <r.cfgsel>.
    Found 20-bit register for signal <r.haddr>.
    Found 1-bit register for signal <r.hready>.
    Found 1-bit register for signal <r.hwrite>.
    Found 1-bit register for signal <r.penable>.
    Found 32-bit register for signal <r.prdata>.
    Found 1-bit register for signal <r.psel>.
    Found 32-bit register for signal <r.pwdata>.
    Found 3-bit register for signal <r.state>.
    Found 64-bit 16-to-1 multiplexer for signal <v.prdata$mux0001<63:62>> created at line 153.
    Summary:
        inferred  92 D-type flip-flop(s).
        inferred  12 Comparator(s).
        inferred  64 Multiplexer(s).
Unit <apbctrl> synthesized.


Synthesizing Unit <apbuart>.
    Related source file is "../../lib/gaisler/uart/apbuart.vhd".
WARNING:Xst:647 - Input <apbi.psel<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.psel<2:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.pirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.pwdata<31:13>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.scanen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.testen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <uarto.flow> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <apbi.paddr<31:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.paddr<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.testrst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.testoen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <r.txstate> of Case statement line 321 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
        - add an 'INIT' attribute on signal <r.txstate> (optimization is then done without any risk)
        - use the attribute 'signal_encoding user' to avoid onehot optimization
        - use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
    Using one-hot encoding for signal <r.txstate>.
    Using one-hot encoding for signal <r.rxstate>.
    Found 12-bit register for signal <r.brate>.
    Found 1-bit register for signal <r.break>.
    Found 2-bit register for signal <r.ctsn>.
    Found 1-bit register for signal <r.debug>.
    Found 1-bit register for signal <r.dpar>.
    Found 1-bit xor2 for signal <r.dpar$xor0000> created at line 420.
    Found 1-bit register for signal <r.extclk>.
    Found 1-bit register for signal <r.extclken>.
    Found 1-bit register for signal <r.flow>.
    Found 1-bit register for signal <r.frame>.
    Found 1-bit register for signal <r.irq>.
    Found 1-bit register for signal <r.loopb>.
    Found 1-bit register for signal <r.oen>.
    Found 1-bit register for signal <r.ovf>.
    Found 1-bit register for signal <r.paren>.
    Found 1-bit register for signal <r.parerr>.
    Found 1-bit register for signal <r.parsel>.
    Found 3-bit register for signal <r.rcnt>.
    Found 1-bit register for signal <r.rfifoirqen>.
    Found 32-bit register for signal <r.rhold>.
    Found 1-bit register for signal <r.rirqen>.
    Found 2-bit up counter for signal <r.rraddr>.
    Found 1-bit register for signal <r.rsempty>.
    Found 8-bit register for signal <r.rshift>.
    Found 1-bit register for signal <r.rtsn>.
    Found 2-bit register for signal <r.rwaddr>.
    Found 3-bit register for signal <r.rxclk>.
    Found 2-bit register for signal <r.rxdb>.
    Found 1-bit register for signal <r.rxen>.
    Found 5-bit register for signal <r.rxf>.
    Found 5-bit register for signal <r.rxstate>.
    Found 1-bit register for signal <r.rxtick>.
    Found 12-bit register for signal <r.scaler>.
    Found 3-bit register for signal <r.tcnt>.
    Found 1-bit register for signal <r.tfifoirqen>.
    Found 32-bit register for signal <r.thold>.
    Found 1-bit register for signal <r.tick>.
    Found 1-bit register for signal <r.tirqen>.
    Found 1-bit register for signal <r.tpar>.
    Found 1-bit xor2 for signal <r.tpar$xor0000> created at line 341.
    Found 2-bit register for signal <r.traddr>.
    Found 1-bit register for signal <r.tsempty>.
    Found 11-bit register for signal <r.tshift>.
    Found 2-bit up counter for signal <r.twaddr>.
    Found 3-bit register for signal <r.txclk>.
    Found 1-bit register for signal <r.txd>.
    Found 1-bit register for signal <r.txen>.
    Found 4-bit register for signal <r.txstate>.
    Found 1-bit register for signal <r.txtick>.
    Found 8-bit 4-to-1 multiplexer for signal <rdata_7_0$varindex0000> created at line 190.
    Found 8-bit 4-to-1 multiplexer for signal <rdata_7_0$varindex0001> created at line 226.
    Found 3-bit adder for signal <rxclk$add0001> created at line 233.
    Found 12-bit subtractor for signal <scaler$sub0000> created at line 273.
    Found 3-bit adder for signal <txclk$add0001> created at line 233.
    Found 3-bit adder for signal <v.rcnt$add0001> created at line 233.
    Found 3-bit subtractor for signal <v.rcnt$addsub0000> created at line 273.
    Found 3-bit adder for signal <v.rcnt$addsub0001> created at line 233.
    Found 2-bit adder for signal <v.rwaddr$add0001> created at line 233.
    Found 3-bit adder for signal <v.tcnt$addsub0000> created at line 233.
    Found 3-bit subtractor for signal <v.tcnt$sub0000> created at line 273.
    Found 2-bit adder for signal <v.traddr$add0001> created at line 233.
    Summary:
        inferred   2 Counter(s).
        inferred 169 D-type flip-flop(s).
        inferred  10 Adder/Subtractor(s).
        inferred  16 Multiplexer(s).
Unit <apbuart> synthesized.


Synthesizing Unit <irqmp>.
    Related source file is "../../lib/gaisler/leon3/irqmp.vhd".
WARNING:Xst:647 - Input <apbi.psel<0:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.psel<3:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.pirq<31:16>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.pirq<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.pwdata<16>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.scanen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.testen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.paddr<31:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.paddr<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.testrst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.testoen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <r2in.irl<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <r2in.ipend> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <r2in.imask<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <r.ibroadcast> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 1-bit 4-to-1 multiplexer for signal <prdata_0$mux0001> created at line 143.
    Found 1-bit 4-to-1 multiplexer for signal <prdata_1$mux0001> created at line 143.
    Found 1-bit 4-to-1 multiplexer for signal <prdata_1$mux0002> created at line 145.
    Found 1-bit 4-to-1 multiplexer for signal <prdata_10$mux0001> created at line 143.
    Found 1-bit 4-to-1 multiplexer for signal <prdata_10$mux0002> created at line 145.
    Found 1-bit 4-to-1 multiplexer for signal <prdata_11$mux0001> created at line 143.
    Found 1-bit 4-to-1 multiplexer for signal <prdata_11$mux0002> created at line 145.
    Found 1-bit 4-to-1 multiplexer for signal <prdata_12$mux0001> created at line 143.
    Found 1-bit 4-to-1 multiplexer for signal <prdata_12$mux0002> created at line 145.
    Found 1-bit 4-to-1 multiplexer for signal <prdata_13$mux0001> created at line 143.
    Found 1-bit 4-to-1 multiplexer for signal <prdata_13$mux0002> created at line 145.
    Found 1-bit 4-to-1 multiplexer for signal <prdata_14$mux0001> created at line 143.
    Found 1-bit 4-to-1 multiplexer for signal <prdata_14$mux0002> created at line 145.
    Found 1-bit 4-to-1 multiplexer for signal <prdata_15$mux0001> created at line 143.
    Found 1-bit 4-to-1 multiplexer for signal <prdata_15$mux0002> created at line 145.
    Found 1-bit 4-to-1 multiplexer for signal <prdata_2$mux0001> created at line 143.
    Found 1-bit 4-to-1 multiplexer for signal <prdata_2$mux0002> created at line 145.
    Found 1-bit 4-to-1 multiplexer for signal <prdata_3$mux0001> created at line 143.
    Found 1-bit 4-to-1 multiplexer for signal <prdata_3$mux0002> created at line 145.
    Found 1-bit 4-to-1 multiplexer for signal <prdata_4$mux0001> created at line 143.
    Found 1-bit 4-to-1 multiplexer for signal <prdata_4$mux0002> created at line 145.
    Found 1-bit 4-to-1 multiplexer for signal <prdata_5$mux0001> created at line 143.
    Found 1-bit 4-to-1 multiplexer for signal <prdata_5$mux0002> created at line 145.
    Found 1-bit 4-to-1 multiplexer for signal <prdata_6$mux0001> created at line 143.
    Found 1-bit 4-to-1 multiplexer for signal <prdata_6$mux0002> created at line 145.
    Found 1-bit 4-to-1 multiplexer for signal <prdata_7$mux0001> created at line 143.
    Found 1-bit 4-to-1 multiplexer for signal <prdata_7$mux0002> created at line 145.
    Found 1-bit 4-to-1 multiplexer for signal <prdata_8$mux0001> created at line 143.
    Found 1-bit 4-to-1 multiplexer for signal <prdata_8$mux0002> created at line 145.
    Found 1-bit 4-to-1 multiplexer for signal <prdata_9$mux0001> created at line 143.
    Found 1-bit 4-to-1 multiplexer for signal <prdata_9$mux0002> created at line 145.
    Found 1-bit register for signal <r.cpurst<0>>.
    Found 15-bit register for signal <r.iforce<0>>.
    Found 15-bit register for signal <r.ilevel>.
    Found 15-bit register for signal <r.imask<0>>.
    Found 15-bit register for signal <r.ipend>.
    Found 4-bit register for signal <r.irl<0>>.
    Summary:
        inferred  65 D-type flip-flop(s).
        inferred  31 Multiplexer(s).
Unit <irqmp> synthesized.


Synthesizing Unit <gptimer>.
    Related source file is "../../lib/gaisler/misc/gptimer.vhd".
WARNING:Xst:647 - Input <apbi.psel<0:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.psel<4:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.pirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.scanen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.testen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.paddr<31:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.paddr<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <gpti.extclk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.testrst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.testoen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 32-bit 1-of-6 priority encoder for internal node.
    Found 32-bit 1-of-6 priority encoder for internal node.
    Found 1-bit register for signal <r.dishlt>.
    Found 8-bit register for signal <r.reload>.
    Found 8-bit register for signal <r.scaler>.
    Found 1-bit register for signal <r.tick>.
    Found 1-bit register for signal <r.timers(1).chain>.
    Found 1-bit register for signal <r.timers(1).enable>.
    Found 1-bit 4-to-1 multiplexer for signal <r.timers(1).enable$mux0002>.
    Found 1-bit 4-to-1 multiplexer for signal <r.timers(1).enable$mux0003>.
    Found 1-bit 4-to-1 multiplexer for signal <r.timers(1).enable$mux0004> created at line 220.
    Found 1-bit register for signal <r.timers(1).irq>.
    Found 1-bit register for signal <r.timers(1).irqen>.
    Found 1-bit register for signal <r.timers(1).irqpen>.
    Found 1-bit 4-to-1 multiplexer for signal <r.timers(1).irqpen$mux0002>.
    Found 1-bit 4-to-1 multiplexer for signal <r.timers(1).irqpen$mux0003>.
    Found 1-bit 4-to-1 multiplexer for signal <r.timers(1).irqpen$mux0004> created at line 220.
    Found 1-bit register for signal <r.timers(1).load>.
    Found 32-bit register for signal <r.timers(1).reload>.
    Found 1-bit register for signal <r.timers(1).restart>.
    Found 32-bit register for signal <r.timers(1).value>.
    Found 32-bit 4-to-1 multiplexer for signal <r.timers(1).value$mux0003>.
    Found 1-bit register for signal <r.timers(2).chain>.
    Found 1-bit register for signal <r.timers(2).enable>.
    Found 1-bit 4-to-1 multiplexer for signal <r.timers(2).enable$mux0002>.
    Found 1-bit 4-to-1 multiplexer for signal <r.timers(2).enable$mux0003>.
    Found 1-bit 4-to-1 multiplexer for signal <r.timers(2).enable$mux0004> created at line 220.
    Found 1-bit register for signal <r.timers(2).irq>.
    Found 1-bit register for signal <r.timers(2).irqen>.
    Found 1-bit register for signal <r.timers(2).irqpen>.
    Found 1-bit 4-to-1 multiplexer for signal <r.timers(2).irqpen$mux0002>.
    Found 1-bit 4-to-1 multiplexer for signal <r.timers(2).irqpen$mux0003>.
    Found 1-bit 4-to-1 multiplexer for signal <r.timers(2).irqpen$mux0004> created at line 220.
    Found 1-bit register for signal <r.timers(2).load>.
    Found 32-bit register for signal <r.timers(2).reload>.
    Found 1-bit register for signal <r.timers(2).restart>.
    Found 32-bit register for signal <r.timers(2).value>.
    Found 32-bit 4-to-1 multiplexer for signal <r.timers(2).value$mux0003>.
    Found 2-bit up counter for signal <r.tsel>.
    Found 1-bit register for signal <r.wdog>.
    Found 1-bit register for signal <r.wdogn>.
    Found 1-bit 4-to-1 multiplexer for signal <readdata_0$mux0000> created at line 196.
    Found 1-bit 4-to-1 multiplexer for signal <readdata_1$mux0000> created at line 196.
    Found 1-bit 4-to-1 multiplexer for signal <readdata_2$mux0000> created at line 196.
    Found 1-bit 4-to-1 multiplexer for signal <readdata_3$mux0000> created at line 196.
    Found 1-bit 4-to-1 multiplexer for signal <readdata_4$mux0000> created at line 196.
    Found 1-bit 4-to-1 multiplexer for signal <readdata_5$mux0000> created at line 196.
    Found 1-bit 4-to-1 multiplexer for signal <readdata_6$mux0000> created at line 196.
    Found 32-bit 3-to-1 multiplexer for signal <res$mux0000> created at line 139.
    Found 32-bit subtractor for signal <res$sub0000> created at line 273.
    Found 1-bit 4-to-1 multiplexer for signal <rin.timers(1).load$mux0000>.
    Found 1-bit 4-to-1 multiplexer for signal <rin.timers(2).load$mux0000>.
    Found 9-bit subtractor for signal <scaler$sub0000> created at line 273.
    Summary:
        inferred   1 Counter(s).
        inferred 162 D-type flip-flop(s).
        inferred   2 Adder/Subtractor(s).
        inferred 117 Multiplexer(s).
        inferred  64 Priority encoder(s).
Unit <gptimer> synthesized.


Synthesizing Unit <grgpio>.
    Related source file is "../../lib/gaisler/misc/grgpio.vhd".
WARNING:Xst:647 - Input <apbi.psel<0:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.psel<9:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.pirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.pwdata<31:18>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <gpioi.din<31:18>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.scanen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.testen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.paddr<31:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.paddr<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <gpioi.sig_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.testrst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <gpioi.sig_in> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.testoen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <r.level> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <r.imask> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <r.ilat> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <r.edge> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <r.bypass> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 18-bit register for signal <r.din1>.
    Found 18-bit register for signal <r.din2>.
    Found 18-bit register for signal <r.dir>.
    Found 18-bit register for signal <r.dout>.
    Summary:
        inferred  72 D-type flip-flop(s).
Unit <grgpio> synthesized.


Synthesizing Unit <mul32>.
    Related source file is "../../lib/gaisler/arith/mul32.vhd".
WARNING:Xst:647 - Input <muli.acc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <rm.acc<31:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <prod<65:64>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <mreg> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <mmin.xsigned> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <mmin.xmac> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <mmin.msigned> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <mmin.mmac> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <mm.xsigned> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <mm.xmac> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <mm.msigned> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <mm.mmac> is used but never assigned. This sourceless signal will be automatically connected to value 0.
    Using one-hot encoding for signal <rm.state>.
    Found 66-bit register for signal <prod>.
    Found 33x33-bit multiplier for signal <prod$mult0001> created at line 111.
    Found 64-bit register for signal <rm.acc>.
    Found 1-bit register for signal <rm.nready>.
    Found 1-bit register for signal <rm.start>.
    Found 2-bit register for signal <rm.state>.
    Summary:
        inferred 134 D-type flip-flop(s).
        inferred   1 Multiplier(s).
Unit <mul32> synthesized.


Synthesizing Unit <div32>.
    Related source file is "../../lib/gaisler/arith/div32.vhd".
    Using one-hot encoding for signal <r.state>.
    Found 33-bit adder for signal <addout>.
    Found 33-bit adder for signal <addout$add0000> created at line 209.
    Found 5-bit register for signal <r.cnt>.
    Found 1-bit register for signal <r.neg>.
    Found 1-bit xor2 for signal <r.neg$xor0000> created at line 94.
    Found 1-bit register for signal <r.ovf>.
    Found 1-bit register for signal <r.qcorr>.
    Found 1-bit xor2 for signal <r.qcorr$xor0000> created at line 117.
    Found 1-bit register for signal <r.qmsb>.
    Found 1-bit register for signal <r.qzero>.
    Found 1-bit xor2 for signal <r.qzero$xor0000> created at line 111.
    Found 6-bit register for signal <r.state>.
    Found 65-bit register for signal <r.x>.
    Found 1-bit register for signal <r.zcorr>.
    Found 1-bit register for signal <r.zero>.
    Found 1-bit register for signal <r.zero2>.
    Found 5-bit adder for signal <v.cnt$add0000> created at line 233.
    Found 1-bit xor2 for signal <v.x_31_0$xor0000> created at line 83.
    Summary:
        inferred  84 D-type flip-flop(s).
        inferred   3 Adder/Subtractor(s).
Unit <div32> synthesized.


Synthesizing Unit <my_mux>.
    Related source file is "../../lib/gaisler/leon3/my_mux.vhd".
    Found 32-bit 4-to-1 multiplexer for signal <res>.
    Summary:
        inferred  32 Multiplexer(s).
Unit <my_mux> synthesized.


Synthesizing Unit <r32_reg>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
    Found 32-bit register for signal <r32_o>.
    Summary:
        inferred  32 D-type flip-flop(s).
Unit <r32_reg> synthesized.


Synthesizing Unit <r32_inst_reg>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
    Found 32-bit register for signal <r32_o>.
    Summary:
        inferred  32 D-type flip-flop(s).
Unit <r32_inst_reg> synthesized.


Synthesizing Unit <r32_data_reg>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
    Found 32-bit register for signal <r32_o>.
    Summary:
        inferred  32 D-type flip-flop(s).
Unit <r32_data_reg> synthesized.


Synthesizing Unit <r5_reg>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
    Found 5-bit register for signal <r5_o>.
    Summary:
        inferred   5 D-type flip-flop(s).
Unit <r5_reg> synthesized.


Synthesizing Unit <wb_mux>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
Unit <wb_mux> synthesized.


Synthesizing Unit <cal_cpi>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
    Found 101-bit up counter for signal <ins_no>.
    Found 101-bit up counter for signal <clk_no>.
    Summary:
        inferred   2 Counter(s).
Unit <cal_cpi> synthesized.


Synthesizing Unit <ctl_FSM>.
    Related source file is "../../lib/gaisler/vlog/ctl_fsm1.v".
    Using one-hot encoding for signal <CurrState>.
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <CurrState> of Case statement line 70 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
        - add an 'INIT' attribute on signal <CurrState> (optimization is then done without any risk)
        - use the attribute 'signal_encoding user' to avoid onehot optimization
        - use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <CurrState> of Case statement line 103 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
        - add an 'INIT' attribute on signal <CurrState> (optimization is then done without any risk)
        - use the attribute 'signal_encoding user' to avoid onehot optimization
        - use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <CurrState> of Case statement line 103 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
        - add an 'INIT' attribute on signal <CurrState> (optimization is then done without any risk)
        - use the attribute 'signal_encoding user' to avoid onehot optimization
        - use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <CurrState> of Case statement line 103 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
        - add an 'INIT' attribute on signal <CurrState> (optimization is then done without any risk)
        - use the attribute 'signal_encoding user' to avoid onehot optimization
        - use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <CurrState> of Case statement line 103 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
        - add an 'INIT' attribute on signal <CurrState> (optimization is then done without any risk)
        - use the attribute 'signal_encoding user' to avoid onehot optimization
        - use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <CurrState> of Case statement line 103 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
        - add an 'INIT' attribute on signal <CurrState> (optimization is then done without any risk)
        - use the attribute 'signal_encoding user' to avoid onehot optimization
        - use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <CurrState> of Case statement line 103 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
        - add an 'INIT' attribute on signal <CurrState> (optimization is then done without any risk)
        - use the attribute 'signal_encoding user' to avoid onehot optimization
        - use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <CurrState> of Case statement line 103 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
        - add an 'INIT' attribute on signal <CurrState> (optimization is then done without any risk)
        - use the attribute 'signal_encoding user' to avoid onehot optimization
        - use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
    Found 8-bit register for signal <CurrState>.
    Found 6-bit up counter for signal <delay_counter>.
    Found 1-bit register for signal <riack>.
    Summary:
        inferred   1 Counter(s).
        inferred   9 D-type flip-flop(s).
Unit <ctl_FSM> synthesized.


Synthesizing Unit <pc_gen>.
    Related source file is "../../lib/gaisler/vlog/RF_components1.v".
WARNING:Xst:646 - Signal <br_addr<32>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:737 - Found 1-bit latch for signal <branch>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
    Found 32-bit adder carry out for signal <br_addr$addsub0000>.
    Found 32-bit adder for signal <pc_next$share0000> created at line 74.
    Summary:
        inferred   2 Adder/Subtractor(s).
Unit <pc_gen> synthesized.


Synthesizing Unit <compare>.
    Related source file is "../../lib/gaisler/vlog/RF_components1.v".
    Found 32-bit comparator equal for signal <res$cmp_eq0001> created at line 47.
    Found 32-bit comparator not equal for signal <res$cmp_ne0000> created at line 48.
    Summary:
        inferred   2 Comparator(s).
Unit <compare> synthesized.


Synthesizing Unit <ext>.
    Related source file is "../../lib/gaisler/vlog/RF_components1.v".
WARNING:Xst:647 - Input <ins_i<31:26>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <ext> synthesized.


Synthesizing Unit <r32_reg_clr_cls>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
    Found 32-bit register for signal <r32_o>.
    Summary:
        inferred  32 D-type flip-flop(s).
Unit <r32_reg_clr_cls> synthesized.


Synthesizing Unit <jack>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
WARNING:Xst:647 - Input <ins_i<31:26>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ins_i<10:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <jack> synthesized.


Synthesizing Unit <rd_sel>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
    Found 10-bit 4-to-1 multiplexer for signal <rd_o>.
    Summary:
        inferred  10 Multiplexer(s).
Unit <rd_sel> synthesized.


Synthesizing Unit <fwd_mux>.
    Related source file is "../../lib/gaisler/vlog/forward.v".
Unit <fwd_mux> synthesized.


Synthesizing Unit <add32>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
    Found 32-bit adder for signal <d_o>.
    Summary:
        inferred   1 Adder/Subtractor(s).
Unit <add32> synthesized.


Synthesizing Unit <alu_muxa>.
    Related source file is "../../lib/gaisler/vlog/EXEC_stage.v".
    Found 32-bit 4-to-1 multiplexer for signal <a_o>.
    Found 32-bit 4-to-1 multiplexer for signal <a_o$mux0000> created at line 212.
    Summary:
        inferred  64 Multiplexer(s).
Unit <alu_muxa> synthesized.


Synthesizing Unit <alu_muxb>.
    Related source file is "../../lib/gaisler/vlog/EXEC_stage.v".
    Found 32-bit 4-to-1 multiplexer for signal <b_o>.
    Found 32-bit 4-to-1 multiplexer for signal <b_o$mux0000> created at line 232.
    Summary:
        inferred  64 Multiplexer(s).
Unit <alu_muxb> synthesized.


Synthesizing Unit <r32_reg_cls>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
    Found 32-bit register for signal <r32_o>.
    Summary:
        inferred  32 D-type flip-flop(s).
Unit <r32_reg_cls> synthesized.


Synthesizing Unit <muldiv_ff>.
    Related source file is "../../lib/gaisler/vlog/EXEC_stage.v".
WARNING:Xst:646 - Signal <START_SECTION/over> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <LAST_CYCLE_DEAL_SECTION/eqz> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <LAST_CYCLE_DEAL_SECTION/eqop2> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <LAST_CYCLE_DEAL_SECTION/eqnop2> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <LAST_CYCLE_DEAL_SECTION/LAST_CYCLE_DEAL_SECTION_DEFAULT/op1s_eq_op2s> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <LAST_CYCLE_DEAL_SECTION/LAST_CYCLE_DEAL_SECTION_DEFAULT/op1s_eq_h64> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 32-bit 4-to-1 multiplexer for signal <res>.
    Found 1-bit register for signal <rdy>.
    Found 33-bit adder for signal <$add0000> created at line 678.
    Found 33-bit adder for signal <$add0001> created at line 679.
    Found 33-bit adder for signal <$add0002> created at line 693.
    Found 33-bit adder for signal <$add0003> created at line 693.
    Found 32-bit adder for signal <$add0004> created at line 703.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0000> created at line 677.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0001> created at line 677.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0002> created at line 677.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0003> created at line 677.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0004> created at line 677.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0005> created at line 677.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0006> created at line 677.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0007> created at line 677.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0008> created at line 677.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0009> created at line 677.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0010> created at line 677.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0011> created at line 677.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0012> created at line 677.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0013> created at line 677.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0014> created at line 677.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0015> created at line 677.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0016> created at line 677.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0017> created at line 677.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0018> created at line 677.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0019> created at line 677.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0020> created at line 677.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0021> created at line 677.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0022> created at line 677.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0023> created at line 677.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0024> created at line 677.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0025> created at line 677.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0026> created at line 677.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0027> created at line 677.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0028> created at line 677.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0029> created at line 677.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0030> created at line 677.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0031> created at line 677.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0032> created at line 677.
    Found 1-bit register for signal <add1>.
    Found 1-bit register for signal <addnop2>.
    Found 1-bit register for signal <addop2>.
    Found 6-bit up counter for signal <count>.
    Found 1-bit register for signal <finish>.
    Found 65-bit register for signal <hilo>.
    Found 1-bit xor2 for signal <hilo_0$xor0000> created at line 695.
    Found 1-bit register for signal <mul>.
    Found 33-bit adder for signal <nop2_reged>.
    Found 1-bit xor2 for signal <old_sub_or_yn_67$xor0000> created at line 690.
    Found 1-bit register for signal <op1_sign_reged>.
    Found 1-bit xor2 for signal <op1s_eq_h64_74$xor0000> created at line 731.
    Found 1-bit xor2 for signal <op1s_eq_op2s_73$xor0000> created at line 730.
    Found 33-bit register for signal <op2_reged>.
    Found 1-bit register for signal <op2_sign_reged>.
    Found 1-bit register for signal <overflow>.
    Found 1-bit register for signal <sign>.
    Found 1-bit register for signal <start>.
    Found 1-bit register for signal <sub_or_yn>.
    Summary:
        inferred   1 Counter(s).
        inferred 110 D-type flip-flop(s).
        inferred   7 Adder/Subtractor(s).
        inferred   2 Comparator(s).
        inferred  65 Multiplexer(s).
Unit <muldiv_ff> synthesized.


Synthesizing Unit <shifter_tak>.
    Related source file is "../../lib/gaisler/vlog/EXEC_stage.v".
WARNING:Xst:647 - Input <shift_amount<31:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <shifter_tak> synthesized.


Synthesizing Unit <alu>.
    Related source file is "../../lib/gaisler/vlog/EXEC_stage.v".
WARNING:Xst:646 - Signal <sum> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 32-bit adder for signal <alu_out$addsub0000>.
    Found 32-bit adder for signal <alu_out$addsub0001> created at line 259.
    Found 32-bit comparator less for signal <alu_out$cmp_lt0000> created at line 264.
    Found 32-bit xor2 for signal <alu_out$xor0000> created at line 262.
    Found 33-bit adder for signal <old_sum_77$addsub0000> created at line 267.
    Summary:
        inferred   4 Adder/Subtractor(s).
        inferred   1 Comparator(s).
Unit <alu> synthesized.


Synthesizing Unit <decoder>.
    Related source file is "../../lib/gaisler/vlog/decode_pipe1.v".
WARNING:Xst:646 - Signal <inst_cop0_code> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 5-bit comparator equal for signal <load_o$cmp_eq0000> created at line 58.
    Found 5-bit comparator equal for signal <load_o$cmp_eq0001> created at line 58.
    Summary:
        inferred   2 Comparator(s).
Unit <decoder> synthesized.


Synthesizing Unit <muxb_ctl_reg_clr_cls>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
    Found 2-bit register for signal <muxb_ctl_o>.
    Summary:
        inferred   2 D-type flip-flop(s).
Unit <muxb_ctl_reg_clr_cls> synthesized.


Synthesizing Unit <wb_mux_ctl_reg_clr_cls>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
    Found 1-bit register for signal <wb_mux_ctl_o<0>>.
    Summary:
        inferred   1 D-type flip-flop(s).
Unit <wb_mux_ctl_reg_clr_cls> synthesized.


Synthesizing Unit <wb_we_reg_clr_cls>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
    Found 1-bit register for signal <wb_we_o<0>>.
    Summary:
        inferred   1 D-type flip-flop(s).
Unit <wb_we_reg_clr_cls> synthesized.


Synthesizing Unit <wb_we_reg>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
    Found 1-bit register for signal <wb_we_o<0>>.
    Summary:
        inferred   1 D-type flip-flop(s).
Unit <wb_we_reg> synthesized.


Synthesizing Unit <wb_mux_ctl_reg_clr>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
    Found 1-bit register for signal <wb_mux_ctl_o<0>>.
    Summary:
        inferred   1 D-type flip-flop(s).
Unit <wb_mux_ctl_reg_clr> synthesized.


Synthesizing Unit <muxb_ctl_reg_clr>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
    Found 2-bit register for signal <muxb_ctl_o>.
    Summary:
        inferred   2 D-type flip-flop(s).
Unit <muxb_ctl_reg_clr> synthesized.


Synthesizing Unit <dmem_ctl_reg_clr>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
    Found 5-bit register for signal <dmem_ctl_o>.
    Summary:
        inferred   5 D-type flip-flop(s).
Unit <dmem_ctl_reg_clr> synthesized.


Synthesizing Unit <alu_func_reg_clr>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
    Found 5-bit register for signal <alu_func_o>.
    Summary:
        inferred   5 D-type flip-flop(s).
Unit <alu_func_reg_clr> synthesized.


Synthesizing Unit <muxa_ctl_reg_clr>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
    Found 2-bit register for signal <muxa_ctl_o>.
    Summary:
        inferred   2 D-type flip-flop(s).
Unit <muxa_ctl_reg_clr> synthesized.


Synthesizing Unit <wb_mux_ctl_reg>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
    Found 1-bit register for signal <wb_mux_ctl_o<0>>.
    Summary:
        inferred   1 D-type flip-flop(s).
Unit <wb_mux_ctl_reg> synthesized.


Synthesizing Unit <wb_we_reg_clr>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
    Found 1-bit register for signal <wb_we_o<0>>.
    Summary:
        inferred   1 D-type flip-flop(s).
Unit <wb_we_reg_clr> synthesized.


Synthesizing Unit <cmp_ctl_reg_clr_cls>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
    Found 3-bit register for signal <cmp_ctl_o>.
    Summary:
        inferred   3 D-type flip-flop(s).
Unit <cmp_ctl_reg_clr_cls> synthesized.


Synthesizing Unit <alu_we_reg_clr>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
    Found 1-bit register for signal <alu_we_o<0>>.
    Summary:
        inferred   1 D-type flip-flop(s).
Unit <alu_we_reg_clr> synthesized.


Synthesizing Unit <alu_func_reg_clr_cls>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
    Found 5-bit register for signal <alu_func_o>.
    Summary:
        inferred   5 D-type flip-flop(s).
Unit <alu_func_reg_clr_cls> synthesized.


Synthesizing Unit <dmem_ctl_reg_clr_cls>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
    Found 5-bit register for signal <dmem_ctl_o>.
    Summary:
        inferred   5 D-type flip-flop(s).
Unit <dmem_ctl_reg_clr_cls> synthesized.


Synthesizing Unit <ext_ctl_reg_clr_cls>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
    Found 3-bit register for signal <ext_ctl_o>.
    Summary:
        inferred   3 D-type flip-flop(s).
Unit <ext_ctl_reg_clr_cls> synthesized.


Synthesizing Unit <rd_sel_reg_clr_cls>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
    Found 2-bit register for signal <rd_sel_o>.
    Summary:
        inferred   2 D-type flip-flop(s).
Unit <rd_sel_reg_clr_cls> synthesized.


Synthesizing Unit <alu_we_reg_clr_cls>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
    Found 1-bit register for signal <alu_we_o<0>>.
    Summary:
        inferred   1 D-type flip-flop(s).
Unit <alu_we_reg_clr_cls> synthesized.


Synthesizing Unit <muxa_ctl_reg_clr_cls>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
    Found 2-bit register for signal <muxa_ctl_o>.
    Summary:
        inferred   2 D-type flip-flop(s).
Unit <muxa_ctl_reg_clr_cls> synthesized.


Synthesizing Unit <pc_gen_ctl_reg_clr_cls>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
    Found 3-bit register for signal <pc_gen_ctl_o>.
    Summary:
        inferred   3 D-type flip-flop(s).
Unit <pc_gen_ctl_reg_clr_cls> synthesized.


Synthesizing Unit <dmem_ctl_reg>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
    Found 5-bit register for signal <dmem_ctl_o>.
    Summary:
        inferred   5 D-type flip-flop(s).
Unit <dmem_ctl_reg> synthesized.


Synthesizing Unit <forward_node>.
    Related source file is "../../lib/gaisler/vlog/forward.v".
    Found 5-bit comparator equal for signal <mux_fw$cmp_eq0000> created at line 33.
    Found 5-bit comparator equal for signal <mux_fw$cmp_eq0001> created at line 33.
    Summary:
        inferred   2 Comparator(s).
Unit <forward_node> synthesized.


Synthesizing Unit <fw_latch5>.
    Related source file is "../../lib/gaisler/vlog/forward.v".
    Found 5-bit register for signal <q>.
    Summary:
        inferred   5 D-type flip-flop(s).
Unit <fw_latch5> synthesized.


Synthesizing Unit <r1_reg>.
    Related source file is "../../lib/gaisler/vlog/ulit.v".
    Found 1-bit register for signal <r1_o<0>>.
    Summary:
        inferred   1 D-type flip-flop(s).
Unit <r1_reg> synthesized.


Synthesizing Unit <icache>.
    Related source file is "../../lib/gaisler/leon3/icache.vhd".
WARNING:Xst:647 - Input <ici.fline> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <icramo.tpar> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dco.icdiag.ilock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dco.icdiag.cctrl.ifrz> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ici.rpc<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dci.eenaddr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dco.werr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dci.enaddr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dci.nullify> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dco.cache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dci.asi> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dci.read> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dco.icdiag.cctrl.dsnoop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dco.data> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ici.pnull> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dco.scanen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ici.dpc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dci.write> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dco.testen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <icramo.ctx> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dco.icdiag.addr<31:22>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dco.icdiag.addr<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <mcio.par> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dco.icdiag.ctx> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <mcio.scanen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ici.fpc<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dci.dsuen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dco.set> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <icramo.dpar> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dco.idle> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dci.lock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dco.mexc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dci.intack> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dci.esu> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dci.msu> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dci.flushl> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dco.icdiag.cctrl.dfrz> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dco.icdiag.pflushaddr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dco.mds> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dco.icdiag.pflushtyp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dci.edata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dci.flush> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ici.flushl> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dco.icdiag.cctrl.dcs> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dci.eaddress> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dco.icdiag.pflush> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dci.size> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1780 - Signal <validv<0:1>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <validv<2:3>> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:1780 - Signal <tag<0:1>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1781 - Signal <tag<2:3>> is used but never assigned. Tied to default value.
    Using one-hot encoding for signal <r.istate>.
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <r.istate> of Case statement line 291 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
        - add an 'INIT' attribute on signal <r.istate> (optimization is then done without any risk)
        - use the attribute 'signal_encoding user' to avoid onehot optimization
        - use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
    Using one-hot encoding for signal <rdatasel$mux0000>.
    Found 20-bit comparator equal for signal <hit$cmp_eq0000> created at line 261.
    Found 20-bit comparator equal for signal <hit$cmp_eq0001> created at line 261.
    Found 32-bit 4-to-1 multiplexer for signal <icramo.tag$mux0000> created at line 293.
    Found 1-bit register for signal <r.burst>.
    Found 1-bit register for signal <r.diagrdy>.
    Found 1-bit register for signal <r.diagset<0>>.
    Found 7-bit up counter for signal <r.faddr>.
    Found 1-bit register for signal <r.flush>.
    Found 1-bit register for signal <r.flush2>.
    Found 1-bit register for signal <r.flush3>.
    Found 1-bit register for signal <r.hit>.
    Found 1-bit register for signal <r.holdn>.
    Found 3-bit register for signal <r.istate>.
    Found 1-bit register for signal <r.lock>.
    Found 1-bit register for signal <r.lrr>.
    Found 1-bit register for signal <r.overrun>.
    Found 1-bit register for signal <r.req>.
    Found 1-bit register for signal <r.rndcnt<0>>.
    Found 1-bit register for signal <r.setrepl<0>>.
    Found 1-bit register for signal <r.su>.
    Found 1-bit register for signal <r.underrun>.
    Found 8-bit register for signal <r.valid>.
    Found 30-bit register for signal <r.waddress>.
    Found 128-bit register for signal <rl.lru>.
    Found 1-bit register for signal <rl.set<0>>.
    Found 7-bit register for signal <rl.waddr>.
    Found 1-bit register for signal <rl.write>.
    Found 7-bit adder for signal <v.faddr$add0000> created at line 233.
    Found 1-bit 4-to-1 multiplexer for signal <validv$mux0000> created at line 280.
    Found 1-bit 8-to-1 multiplexer for signal <validv$mux0001> created at line 140.
    Found 1-bit 8-to-1 multiplexer for signal <validv$mux0002> created at line 140.
    Found 3-bit adder for signal <xaddr_inc$add0000> created at line 233.
    Summary:
        inferred   1 Counter(s).
        inferred 194 D-type flip-flop(s).
        inferred   2 Adder/Subtractor(s).
        inferred   2 Comparator(s).
        inferred  36 Multiplexer(s).
Unit <icache> synthesized.


Synthesizing Unit <dcache>.
    Related source file is "../../lib/gaisler/leon3/dcache.vhd".
WARNING:Xst:647 - Input <ahbsi.hsel> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbsi.hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbsi.hmastlock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <dco.cache> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <dci.asi<7:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbsi.testoen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ico.data> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dcramo.dpar> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dcramo.ctx> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbsi.hsize> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbsi.hprot> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbsi.scanen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dcramo.stag<0><11:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dcramo.stag<1:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbsi.testen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <mcdo.par> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ico.set> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbsi.haddr<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbsi.hwdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dcramo.tpar> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ico.mds> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ico.idle> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ico.mexc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <dcrami.spar> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <dci.esu> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dci.msu> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbsi.hcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dci.flushl> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbsi.hburst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbsi.hmbsel> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <dco.icdiag.pflushtyp> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <dcramo.spar> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dci.eaddress<31:12>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dci.eaddress<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbsi.hmaster> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbsi.testrst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <rl.write> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <rl.waddr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <r.setrepl<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <r.rndcnt<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <r.lramrd> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <r.forcemiss> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.write> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.waddr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.set<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<0><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<1><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<2><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<3><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<4><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<5><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<6><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<7><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<8><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<9><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<10><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<11><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<12><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<13><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<14><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<15><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<16><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<17><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<18><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<19><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<20><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<21><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<22><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<23><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<24><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<25><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<26><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<27><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<28><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<29><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<30><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<31><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<32><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<33><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<34><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<35><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<36><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<37><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<38><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<39><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<40><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<41><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<42><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<43><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<44><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<45><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<46><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<47><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<48><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<49><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<50><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<51><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<52><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<53><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<54><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<55><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<56><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<57><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<58><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<59><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<60><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<61><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<62><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<63><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<64><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<65><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<66><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<67><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<68><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<69><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<70><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<71><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<72><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<73><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<74><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<75><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<76><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<77><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<78><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<79><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<80><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<81><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<82><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<83><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<84><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<85><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<86><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<87><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<88><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<89><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<90><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<91><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<92><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<93><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<94><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<95><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<96><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<97><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<98><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<99><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<100><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<101><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<102><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<103><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<104><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<105><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<106><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<107><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<108><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<109><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<110><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<111><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<112><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<113><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<114><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<115><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<116><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<117><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<118><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<119><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<120><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<121><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<122><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<123><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<124><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<125><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<126><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<127><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<128><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<129><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<130><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<131><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<132><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<133><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<134><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<135><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<136><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<137><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<138><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<139><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<140><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<141><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<142><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<143><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<144><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<145><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<146><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<147><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<148><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<149><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<150><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<151><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<152><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<153><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<154><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<155><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<156><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<157><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<158><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<159><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<160><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<161><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<162><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<163><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<164><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<165><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<166><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<167><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<168><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<169><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<170><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<171><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<172><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<173><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<174><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<175><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<176><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<177><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<178><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<179><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<180><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<181><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<182><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<183><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<184><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<185><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<186><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<187><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<188><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<189><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<190><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<191><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<192><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<193><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<194><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<195><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<196><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<197><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<198><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<199><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<200><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<201><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<202><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<203><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<204><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<205><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<206><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<207><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<208><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<209><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<210><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<211><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<212><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<213><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<214><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<215><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<216><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<217><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<218><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<219><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<220><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<221><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<222><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<223><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<224><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<225><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<226><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<227><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<228><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<229><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<230><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<231><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<232><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<233><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<234><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<235><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<236><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<237><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<238><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<239><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<240><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<241><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<242><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<243><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<244><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<245><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<246><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<247><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<248><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<249><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<250><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<251><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<252><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<253><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<254><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cl.lru<255><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.taddr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.set<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<0><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<1><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<2><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<3><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<4><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<5><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<6><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<7><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<8><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<9><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<10><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<11><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<12><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<13><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<14><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<15><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<16><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<17><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<18><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<19><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<20><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<21><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<22><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<23><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<24><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<25><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<26><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<27><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<28><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<29><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<30><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<31><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<32><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<33><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<34><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<35><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<36><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<37><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<38><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<39><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<40><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<41><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<42><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<43><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<44><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<45><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<46><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<47><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<48><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<49><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<50><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<51><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<52><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<53><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<54><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<55><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<56><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<57><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<58><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<59><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<60><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<61><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<62><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<63><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<64><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<65><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<66><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<67><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<68><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<69><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<70><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<71><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<72><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<73><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<74><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<75><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<76><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<77><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<78><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<79><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<80><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<81><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<82><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<83><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<84><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<85><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<86><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<87><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<88><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<89><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<90><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<91><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<92><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<93><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<94><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<95><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<96><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<97><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<98><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<99><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<100><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<101><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<102><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<103><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<104><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<105><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<106><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<107><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<108><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<109><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<110><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<111><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<112><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<113><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<114><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<115><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<116><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<117><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<118><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<119><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<120><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<121><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<122><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<123><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<124><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<125><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<126><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<127><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<128><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<129><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<130><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<131><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<132><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<133><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<134><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<135><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<136><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<137><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<138><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<139><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<140><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<141><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<142><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<143><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<144><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<145><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<146><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<147><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<148><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<149><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<150><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<151><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<152><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<153><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<154><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<155><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<156><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<157><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<158><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<159><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<160><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<161><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<162><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<163><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<164><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<165><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<166><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<167><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<168><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<169><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<170><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<171><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<172><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<173><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<174><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<175><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<176><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<177><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<178><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<179><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<180><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<181><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<182><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<183><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<184><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<185><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<186><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<187><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<188><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<189><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<190><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<191><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<192><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<193><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<194><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<195><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<196><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<197><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<198><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<199><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<200><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<201><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<202><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<203><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<204><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<205><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<206><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<207><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<208><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<209><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<210><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<211><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<212><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<213><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<214><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<215><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<216><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<217><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<218><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<219><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<220><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<221><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<222><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<223><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<224><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<225><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<226><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<227><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<228><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<229><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<230><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<231><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<232><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<233><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<234><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<235><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<236><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<237><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<238><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<239><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<240><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<241><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<242><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<243><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<244><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<245><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<246><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<247><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<248><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<249><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<250><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<251><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<252><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<253><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<254><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ch.hit<255><0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Using one-hot encoding for signal <r.dstate>.
    Using one-hot encoding for signal <rdatasel$mux0004>.
    Found 8-bit comparator equal for signal <cs.writebp_0$cmp_eq0000> created at line 934.
    Found 1-bit 4-to-1 multiplexer for signal <dwrite$mux0008>.
    Found 20-bit comparator equal for signal <hitv$cmp_eq0000> created at line 417.
    Found 4-bit register for signal <r.asi>.
    Found 1-bit register for signal <r.burst>.
    Found 1-bit register for signal <r.cctrl.burst>.
    Found 2-bit register for signal <r.cctrl.dcs>.
    Found 1-bit register for signal <r.cctrl.dfrz>.
    Found 1-bit register for signal <r.cctrl.dsnoop>.
    Found 2-bit register for signal <r.cctrl.ics>.
    Found 1-bit register for signal <r.cctrl.ifrz>.
    Found 1-bit register for signal <r.cctrlwr>.
    Found 6-bit register for signal <r.dstate>.
    Found 1-bit register for signal <r.dsuset<0>>.
    Found 8-bit up counter for signal <r.faddr>.
    Found 1-bit register for signal <r.flush>.
    Found 1-bit register for signal <r.flush2>.
    Found 1-bit register for signal <r.hit>.
    Found 1-bit register for signal <r.holdn>.
    Found 1-bit register for signal <r.icenable>.
    Found 1-bit register for signal <r.ilramen>.
    Found 1-bit register for signal <r.lock>.
    Found 1-bit register for signal <r.lrr>.
    Found 1-bit register for signal <r.mexc>.
    Found 1-bit register for signal <r.nomds>.
    Found 1-bit register for signal <r.read>.
    Found 1-bit register for signal <r.req>.
    Found 2-bit register for signal <r.size>.
    Found 1-bit register for signal <r.stpend>.
    Found 4-bit register for signal <r.valid<0>>.
    Found 32-bit register for signal <r.wb.addr>.
    Found 4-bit register for signal <r.wb.asi>.
    Found 32-bit register for signal <r.wb.data1>.
    Found 32-bit register for signal <r.wb.data2>.
    Found 1-bit register for signal <r.wb.lock>.
    Found 1-bit register for signal <r.wb.read>.
    Found 2-bit register for signal <r.wb.size>.
    Found 32-bit register for signal <r.xaddress>.
    Found 28-bit comparator equal for signal <rbphit$cmp_eq0000> created at line 358.
    Found 1-bit 4-to-1 multiplexer for signal <res$mux0000> created at line 141.
    Found 28-bit register for signal <rs.addr>.
    Found 1-bit register for signal <rs.readbpx<0>>.
    Found 1-bit register for signal <rs.snoop>.
    Found 1-bit register for signal <rs.writebp<0>>.
    Found 20-bit comparator equal for signal <snoopwe$cmp_eq0000> created at line 365.
    Found 1-bit 4-to-1 multiplexer for signal <twrite$mux0012>.
    Found 8-bit adder for signal <v.faddr$add0000> created at line 233.
    Summary:
        inferred   1 Counter(s).
        inferred 207 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   4 Comparator(s).
        inferred   3 Multiplexer(s).
Unit <dcache> synthesized.


Synthesizing Unit <mmu_acache>.
    Related source file is "../../lib/gaisler/leon3/mmu_acache.vhd".
WARNING:Xst:647 - Input <ahbso(12).hsplit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(4).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(9).hsplit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(10).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(13).hcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(5).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(3).hconfig<0:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(3).hconfig<4><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(3).hconfig<4><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(3).hconfig<5><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(3).hconfig<5><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(3).hconfig<6><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(3).hconfig<6><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(3).hconfig<7><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(3).hconfig<7><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(12).hresp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(3).hready> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(4).hrdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(14).hconfig<0:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(14).hconfig<4><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(14).hconfig<4><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(14).hconfig<5><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(14).hconfig<5><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(14).hconfig<6><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(14).hconfig<6><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(14).hconfig<7><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(14).hconfig<7><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(14).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(13).hrdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(5).hresp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(12).hready> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(9).hready> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(4).hsplit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(5).hcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(0).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(2).hconfig<0:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(2).hconfig<4><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(2).hconfig<4><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(2).hconfig<5><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(2).hconfig<5><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(2).hconfig<6><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(2).hconfig<6><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(2).hconfig<7><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(2).hconfig<7><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(5).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(13).hsplit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(11).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(13).hconfig<0:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(13).hconfig<4><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(13).hconfig<4><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(13).hconfig<5><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(13).hconfig<5><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(13).hconfig<6><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(13).hconfig<6><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(13).hconfig<7><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(13).hconfig<7><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(14).hcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(11).hresp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(6).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(4).hready> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(5).hrdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.testoen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(0).hcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(4).hresp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(15).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(1).hconfig<0:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(1).hconfig<4><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(1).hconfig<4><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(1).hconfig<5><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(1).hconfig<5><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(1).hconfig<6><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(1).hconfig<6><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(1).hconfig<7><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(1).hconfig<7><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(14).hrdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(13).hready> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(12).hconfig<0:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(12).hconfig<4><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(12).hconfig<4><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(12).hconfig<5><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(12).hconfig<5><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(12).hconfig<6><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(12).hconfig<6><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(12).hconfig<7><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(12).hconfig<7><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(5).hsplit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(6).hcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(1).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(0).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(6).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(0).hrdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(12).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(14).hsplit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(9).hconfig<0:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(9).hconfig<4><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(9).hconfig<4><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(9).hconfig<5><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(9).hconfig<5><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(9).hconfig<6><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(9).hconfig<6><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(9).hconfig<7><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(9).hconfig<7><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <hclken> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(10).hresp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(15).hcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(10).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(0).hconfig<0:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(0).hconfig<4><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(0).hconfig<4><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(0).hconfig<5><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(0).hconfig<5><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(0).hconfig<6><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(0).hconfig<6><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(0).hconfig<7><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(0).hconfig<7><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(7).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(5).hready> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(6).hrdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(11).hconfig<0:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(11).hconfig<4><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(11).hconfig<4><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(11).hconfig<5><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(11).hconfig<5><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(11).hconfig<6><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(11).hconfig<6><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(11).hconfig<7><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(11).hconfig<7><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(0).hsplit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(3).hresp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(1).hcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(9).hresp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(15).hrdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(14).hready> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(8).hconfig<0:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(8).hconfig<4><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(8).hconfig<4><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(8).hconfig<5><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(8).hconfig<5><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(8).hconfig<6><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(8).hconfig<6><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(8).hconfig<7><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(8).hconfig<7><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(6).hsplit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(10).hcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <mcii.flush> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <mcmmi.burst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(7).hcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(1).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(7).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(2).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(1).hrdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(0).hready> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(13).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(10).hconfig<0:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(10).hconfig<4><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(10).hconfig<4><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(10).hconfig<5><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(10).hconfig<5><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(10).hconfig<6><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(10).hconfig<6><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(10).hconfig<7><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(10).hconfig<7><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(15).hsplit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(15).hresp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(11).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(10).hrdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(8).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(6).hready> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(7).hrdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(7).hconfig<0:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(7).hconfig<4><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(7).hconfig<4><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(7).hconfig<5><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(7).hconfig<5><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(7).hconfig<6><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(7).hconfig<6><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(7).hconfig<7><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(7).hconfig<7><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(2).hresp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(1).hsplit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(8).hresp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(2).hcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.testrst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(15).hready> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(10).hsplit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(7).hsplit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(11).hcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(2).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(8).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(8).hcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <mcdo.par> is never assigned. Tied to value 0000.
WARNING:Xst:647 - Input <ahbso(3).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(14).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.hgrant<1:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(2).hrdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(1).hready> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(6).hconfig<0:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(6).hconfig<4><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(6).hconfig<4><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(6).hconfig<5><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(6).hconfig<5><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(6).hconfig<6><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(6).hconfig<6><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(6).hconfig<7><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(6).hconfig<7><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(14).hresp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(12).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(11).hrdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(10).hready> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(9).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(7).hready> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(1).hresp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(8).hrdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(7).hresp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(2).hsplit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(3).hcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(5).hconfig<0:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(5).hconfig<4><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(5).hconfig<4><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(5).hconfig<5><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(5).hconfig<5><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(5).hconfig<6><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(5).hconfig<6><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(5).hconfig<7><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(5).hconfig<7><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(11).hsplit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(8).hsplit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(3).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(9).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(12).hcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <mcio.par> is never assigned. Tied to value 0000.
WARNING:Xst:647 - Input <ahbso(9).hcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(15).hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(4).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(3).hrdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(2).hready> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.scanen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(13).hresp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(13).hindex> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(12).hrdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(0).hresp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(11).hready> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(4).hconfig<0:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(4).hconfig<4><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(4).hconfig<4><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(4).hconfig<5><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(4).hconfig<5><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(4).hconfig<6><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(4).hconfig<6><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(4).hconfig<7><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(4).hconfig<7><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(8).hready> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(9).hrdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(6).hresp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(3).hsplit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(15).hconfig<0:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(15).hconfig<4><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(15).hconfig<4><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(15).hconfig<5><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(15).hconfig<5><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(15).hconfig<6><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(15).hconfig<6><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(15).hconfig<7><19:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(15).hconfig<7><3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbso(4).hcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <r2in.reqmsk> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <r2in.hclken2> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <r2.hclken2> is used but never assigned. This sourceless signal will be automatically connected to value 0.
    Found 1-bit 4-to-1 multiplexer for signal <mcdo.mexc>.
    Found 1-bit 4-to-1 multiplexer for signal <mcdo.retry>.
    Found 1-bit 4-to-1 multiplexer for signal <mcdo.grant>.
    Found 1-bit 4-to-1 multiplexer for signal <mcdo.cache>.
    Found 1-bit 4-to-1 multiplexer for signal <mcdo.ready>.
    Found 1-bit 4-to-1 multiplexer for signal <ahbo.hwrite>.
    Found 1-bit xor2 for signal <ahbo.hprot$xor0000> created at line 312.
    Found 1-bit 4-to-1 multiplexer for signal <haddr_10$mux0002> created at line 184.
    Found 1-bit 4-to-1 multiplexer for signal <haddr_11$mux0002> created at line 184.
    Found 1-bit 4-to-1 multiplexer for signal <haddr_12$mux0002> created at line 184.
    Found 1-bit 4-to-1 multiplexer for signal <haddr_13$mux0002> created at line 184.
    Found 1-bit 4-to-1 multiplexer for signal <haddr_14$mux0002> created at line 184.
    Found 1-bit 4-to-1 multiplexer for signal <haddr_15$mux0002> created at line 184.
    Found 1-bit 4-to-1 multiplexer for signal <haddr_16$mux0002> created at line 184.
    Found 1-bit 4-to-1 multiplexer for signal <haddr_17$mux0002> created at line 184.
    Found 1-bit 4-to-1 multiplexer for signal <haddr_18$mux0002> created at line 184.
    Found 1-bit 4-to-1 multiplexer for signal <haddr_19$mux0002> created at line 184.
    Found 1-bit 4-to-1 multiplexer for signal <haddr_2$mux0004> created at line 184.
    Found 1-bit 4-to-1 multiplexer for signal <haddr_20$mux0002> created at line 184.
    Found 1-bit 4-to-1 multiplexer for signal <haddr_21$mux0002> created at line 184.
    Found 1-bit 4-to-1 multiplexer for signal <haddr_22$mux0002> created at line 184.
    Found 1-bit 4-to-1 multiplexer for signal <haddr_23$mux0002> created at line 184.
    Found 1-bit 4-to-1 multiplexer for signal <haddr_24$mux0002> created at line 184.
    Found 1-bit 4-to-1 multiplexer for signal <haddr_25$mux0002> created at line 184.
    Found 1-bit 4-to-1 multiplexer for signal <haddr_26$mux0002> created at line 184.
    Found 1-bit 4-to-1 multiplexer for signal <haddr_27$mux0002> created at line 184.
    Found 1-bit 4-to-1 multiplexer for signal <haddr_28$mux0002> created at line 184.
    Found 1-bit 4-to-1 multiplexer for signal <haddr_29$mux0002> created at line 184.
    Found 1-bit 4-to-1 multiplexer for signal <haddr_3$mux0004> created at line 184.
    Found 1-bit 4-to-1 multiplexer for signal <haddr_30$mux0002> created at line 184.
    Found 1-bit 4-to-1 multiplexer for signal <haddr_31$mux0002> created at line 184.
    Found 1-bit 4-to-1 multiplexer for signal <haddr_4$mux0004> created at line 184.
    Found 3-bit adder for signal <haddr_4_2$add0000> created at line 233.
    Found 3-bit adder for signal <haddr_4_2$add0001> created at line 233.
    Found 1-bit 4-to-1 multiplexer for signal <haddr_5$mux0002> created at line 184.
    Found 1-bit 4-to-1 multiplexer for signal <haddr_6$mux0002> created at line 184.
    Found 1-bit 4-to-1 multiplexer for signal <haddr_7$mux0002> created at line 184.
    Found 1-bit 4-to-1 multiplexer for signal <haddr_8$mux0002> created at line 184.
    Found 1-bit 4-to-1 multiplexer for signal <haddr_9$mux0002> created at line 184.
    Found 3-bit 4-to-1 multiplexer for signal <hburst$mux0005> created at line 184.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0000> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0001> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0002> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0003> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0004> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0005> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0006> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0007> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0008> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0009> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0010> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0011> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0012> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0013> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0014> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0015> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0016> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0017> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0018> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0019> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0020> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0021> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0022> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0023> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0024> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0025> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0026> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0027> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0028> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0029> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0030> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0031> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0032> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0033> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0034> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0035> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0036> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0037> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0038> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0039> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0040> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0041> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0042> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0043> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0044> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0045> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0046> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0047> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0048> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0049> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0050> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0051> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0052> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0053> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0054> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0055> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0056> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0057> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0058> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0059> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0060> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0061> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0062> created at line 500.
    Found 12-bit comparator equal for signal <hcache$cmp_eq0063> created at line 500.
    Found 1-bit 4-to-1 multiplexer for signal <hlock$mux0002> created at line 184.
    Found 3-bit 4-to-1 multiplexer for signal <hsize$mux0002> created at line 184.
    Found 1-bit register for signal <r.ba>.
    Found 1-bit register for signal <r.bg>.
    Found 2-bit register for signal <r.bo>.
    Found 1-bit register for signal <r.hcache>.
    Found 1-bit 4-to-1 multiplexer for signal <r.hcache$mux0000>.
    Found 1-bit register for signal <r.hlocken>.
    Found 1-bit register for signal <r.lb>.
    Found 1-bit register for signal <r.lock>.
    Found 1-bit register for signal <r.nba>.
    Found 2-bit register for signal <r.nbo>.
    Found 1-bit register for signal <r.retry>.
    Found 1-bit register for signal <r.retry2>.
    Found 1-bit register for signal <r.werr>.
    Found 1-bit 4-to-1 multiplexer for signal <su$mux0003> created at line 184.
    Summary:
        inferred  14 D-type flip-flop(s).
        inferred   2 Adder/Subtractor(s).
        inferred  64 Comparator(s).
        inferred  45 Multiplexer(s).
Unit <mmu_acache> synthesized.


Synthesizing Unit <generic_regfile_3p>.
    Related source file is "../../lib/techmap/inferred/memory_inferred.vhd".
WARNING:Xst:647 - Input <rclk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 32x32-bit dual-port RAM <Mram_memarr> for signal <memarr>.
    Found 32x32-bit dual-port RAM <Mram_memarr_ren> for signal <memarr>.
    Found 32-bit register for signal <din>.
    Found 5-bit register for signal <ra1>.
    Found 5-bit register for signal <ra2>.
    Found 5-bit comparator equal for signal <rdata1$cmp_eq0000> created at line 177.
    Found 5-bit comparator equal for signal <rdata2$cmp_eq0000> created at line 179.
    Found 5-bit register for signal <wa>.
    Found 1-bit register for signal <wr>.
    Summary:
        inferred   2 RAM(s).
        inferred  48 D-type flip-flop(s).
        inferred   2 Comparator(s).
Unit <generic_regfile_3p> synthesized.


Synthesizing Unit <dsu3x>.
    Related source file is "../../lib/gaisler/leon3/dsu3x.vhd".
WARNING:Xst:647 - Input <ahbmi.hcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbmi.testrst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbmi.hresp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbmi.testoen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dbgi(0).icnt> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbmi.hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbmi.scanen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbmi.hrdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbmi.testen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <hclk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbmi.hready> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbmi.hgrant> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <vh.irq> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:646 - Signal <trin.tbwr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <trin.tbreg2.write> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <trin.tbreg2.read> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <trin.tbreg2.mask> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <trin.tbreg2.addr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <trin.tbreg1.write> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <trin.tbreg1.read> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <trin.tbreg1.mask> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <trin.tbreg1.addr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <trin.hwrite> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <trin.hwdata> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <trin.htrans> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <trin.hsize> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <trin.hsel> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <trin.hmastlock> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <trin.hmaster> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <trin.hburst> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <trin.haddr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <trin.enable> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <trin.delaycnt> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <trin.dcnten> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <trin.break> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <trin.bphit2> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <trin.bphit> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <trin.aindex> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <trin.ahbactive> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <tr.tbwr> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <tr.tbreg2.write> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <tr.tbreg2.read> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <tr.tbreg2.mask> is used but never assigned. This sourceless signal will be automatically connected to value 000000000000000000000000000000.
WARNING:Xst:653 - Signal <tr.tbreg2.addr> is used but never assigned. This sourceless signal will be automatically connected to value 000000000000000000000000000000.
WARNING:Xst:653 - Signal <tr.tbreg1.write> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <tr.tbreg1.read> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <tr.tbreg1.mask> is used but never assigned. This sourceless signal will be automatically connected to value 000000000000000000000000000000.
WARNING:Xst:653 - Signal <tr.tbreg1.addr> is used but never assigned. This sourceless signal will be automatically connected to value 000000000000000000000000000000.
WARNING:Xst:653 - Signal <tr.hwrite> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <tr.hwdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <tr.htrans> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:653 - Signal <tr.hsize> is used but never assigned. This sourceless signal will be automatically connected to value 000.
WARNING:Xst:653 - Signal <tr.hsel> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <tr.hmastlock> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <tr.hmaster> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:653 - Signal <tr.hburst> is used but never assigned. This sourceless signal will be automatically connected to value 000.
WARNING:Xst:653 - Signal <tr.haddr> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <tr.enable> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <tr.delaycnt> is used but never assigned. This sourceless signal will be automatically connected to value 000000.
WARNING:Xst:653 - Signal <tr.dcnten> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <tr.break> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:1780 - Signal <tr.bphit2> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <tr.bphit> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <tr.aindex> is used but never assigned. This sourceless signal will be automatically connected to value 000000.
WARNING:Xst:653 - Signal <tr.ahbactive> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:1780 - Signal <tbo.data> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <tbi.write> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <tbi.enable> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <tbi.diag> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <tbi.data> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <tbi.addr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <rhin.oen> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <rhin.irq> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <rh.oen> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <rh.irq> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <r.tstop> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <r.slv.hready2> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <r.slv.haddr<1:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <hrdata2x> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ahbsi2.testrst> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ahbsi2.testoen> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ahbsi2.testen> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ahbsi2.scanen> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ahbsi2.htrans<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ahbsi2.hsize> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ahbsi2.hsel<0:1>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ahbsi2.hsel<3:15>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ahbsi2.hprot> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ahbsi2.hmbsel> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ahbsi2.hmastlock> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ahbsi2.hmaster> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ahbsi2.hirq> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ahbsi2.hcache> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ahbsi2.hburst> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ahbsi2.haddr<31:25>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 1-bit register for signal <r.act>.
    Found 1-bit register for signal <r.be<0>>.
    Found 1-bit register for signal <r.bmsk<0>>.
    Found 1-bit register for signal <r.bn<0>>.
    Found 1-bit register for signal <r.bs<0>>.
    Found 1-bit register for signal <r.bw<0>>.
    Found 1-bit register for signal <r.bx<0>>.
    Found 1-bit register for signal <r.bz<0>>.
    Found 3-bit register for signal <r.cnt>.
    Found 1-bit register for signal <r.dmsk<0>>.
    Found 3-bit register for signal <r.dsubre>.
    Found 3-bit register for signal <r.dsuen>.
    Found 1-bit register for signal <r.en<0>>.
    Found 1-bit register for signal <r.halt<0>>.
    Found 1-bit register for signal <r.pwd<0>>.
    Found 1-bit register for signal <r.reset<0>>.
    Found 25-bit register for signal <r.slv.haddr>.
    Found 32-bit register for signal <r.slv.hrdata>.
    Found 1-bit register for signal <r.slv.hready>.
    Found 1-bit register for signal <r.slv.hsel>.
    Found 32-bit register for signal <r.slv.hwdata>.
    Found 1-bit register for signal <r.slv.hwrite>.
    Found 1-bit register for signal <r.ss<0>>.
    Found 1-bit register for signal <r.te<0>>.
    Found 30-bit register for signal <r.timer>.
    Found 3-bit subtractor for signal <v.cnt$addsub0000> created at line 273.
    Found 30-bit adder for signal <v.timer$add0001> created at line 233.
    Summary:
        inferred 146 D-type flip-flop(s).
        inferred   2 Adder/Subtractor(s).
Unit <dsu3x> synthesized.


Synthesizing Unit <ahbmst_1>.
    Related source file is "../../lib/gaisler/misc/ahbmst.vhd".
WARNING:Xst:647 - Input <ahbi.testrst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.testoen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.hgrant<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.hgrant<2:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.hcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.scanen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.testen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <r.active>.
    Found 1-bit register for signal <r.grant>.
    Found 1-bit register for signal <r.retry>.
    Found 1-bit register for signal <r.start>.
    Summary:
        inferred   4 D-type flip-flop(s).
Unit <ahbmst_1> synthesized.


Synthesizing Unit <dcom_uart>.
    Related source file is "../../lib/gaisler/uart/dcom_uart.vhd".
WARNING:Xst:647 - Input <apbi.psel<0:6>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.psel<8:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.pirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.pwdata<31:18>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ui.ctsn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <uo.flow> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <uo.rxen> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <apbi.scanen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.testen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ui.extclk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <uo.txen> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <apbi.paddr<31:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.paddr<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.testrst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.testoen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <r.rxstate> of Case statement line 240 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
        - add an 'INIT' attribute on signal <r.rxstate> (optimization is then done without any risk)
        - use the attribute 'signal_encoding user' to avoid onehot optimization
        - use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
    Using one-hot encoding for signal <r.rxstate>.
    Using one-hot encoding for signal <r.txstate>.
    Found 18-bit register for signal <r.brate>.
    Found 14-bit comparator lessequal for signal <r.brate$cmp_le0000> created at line 128.
    Found 14-bit comparator not equal for signal <r.brate$cmp_ne0001> created at line 132.
    Found 1-bit register for signal <r.break>.
    Found 1-bit register for signal <r.dready>.
    Found 1-bit register for signal <r.fedge>.
    Found 1-bit register for signal <r.frame>.
    Found 1-bit register for signal <r.ovf>.
    Found 8-bit register for signal <r.rhold>.
    Found 1-bit register for signal <r.rsempty>.
    Found 8-bit register for signal <r.rshift>.
    Found 3-bit register for signal <r.rxclk>.
    Found 1-bit register for signal <r.rxdb>.
    Found 7-bit comparator equal for signal <r.rxdb$cmp_eq0000> created at line 201.
    Found 1-bit register for signal <r.rxdb2>.
    Found 1-bit register for signal <r.rxen>.
    Found 8-bit register for signal <r.rxf>.
    Found 4-bit register for signal <r.rxstate>.
    Found 1-bit register for signal <r.rxtick>.
    Found 18-bit register for signal <r.scaler>.
    Found 2-bit register for signal <r.tcnt>.
    Found 1-bit register for signal <r.thempty>.
    Found 8-bit register for signal <r.thold>.
    Found 1-bit register for signal <r.tick>.
    Found 1-bit register for signal <r.tsempty>.
    Found 11-bit register for signal <r.tshift>.
    Found 3-bit register for signal <r.txclk>.
    Found 3-bit register for signal <r.txstate>.
    Found 1-bit register for signal <r.txtick>.
    Found 1-bit 4-to-1 multiplexer for signal <rdata_0$mux0000> created at line 158.
    Found 1-bit 4-to-1 multiplexer for signal <rdata_1$mux0000> created at line 158.
    Found 1-bit 4-to-1 multiplexer for signal <rdata_10$mux0000> created at line 158.
    Found 1-bit 4-to-1 multiplexer for signal <rdata_11$mux0000> created at line 158.
    Found 1-bit 4-to-1 multiplexer for signal <rdata_12$mux0000> created at line 158.
    Found 1-bit 4-to-1 multiplexer for signal <rdata_13$mux0000> created at line 158.
    Found 1-bit 4-to-1 multiplexer for signal <rdata_14$mux0000> created at line 158.
    Found 1-bit 4-to-1 multiplexer for signal <rdata_15$mux0000> created at line 158.
    Found 1-bit 4-to-1 multiplexer for signal <rdata_16$mux0000> created at line 158.
    Found 1-bit 4-to-1 multiplexer for signal <rdata_17$mux0000> created at line 158.
    Found 1-bit 4-to-1 multiplexer for signal <rdata_2$mux0000> created at line 158.
    Found 1-bit 4-to-1 multiplexer for signal <rdata_3$mux0000> created at line 158.
    Found 1-bit 4-to-1 multiplexer for signal <rdata_4$mux0000> created at line 158.
    Found 1-bit 4-to-1 multiplexer for signal <rdata_5$mux0000> created at line 158.
    Found 1-bit 4-to-1 multiplexer for signal <rdata_6$mux0000> created at line 158.
    Found 1-bit 4-to-1 multiplexer for signal <rdata_7$mux0000> created at line 158.
    Found 1-bit 4-to-1 multiplexer for signal <rdata_8$mux0000> created at line 158.
    Found 1-bit 4-to-1 multiplexer for signal <rdata_9$mux0000> created at line 158.
    Found 3-bit adder for signal <rxclk$add0001> created at line 233.
    Found 18-bit addsub for signal <scaler$mux0000> created at line 114.
    Found 3-bit adder for signal <txclk$add0001> created at line 233.
    Found 14-bit comparator equal for signal <v.scaler$cmp_eq0000> created at line 132.
    Found 2-bit adder for signal <v.tcnt$addsub0000> created at line 233.
    Found 14-bit comparator greater for signal <v.tcnt$cmp_gt0000> created at line 128.
    Summary:
        inferred 108 D-type flip-flop(s).
        inferred   4 Adder/Subtractor(s).
        inferred   5 Comparator(s).
        inferred  18 Multiplexer(s).
Unit <dcom_uart> synthesized.


Synthesizing Unit <dcom>.
    Related source file is "../../lib/gaisler/uart/dcom.vhd".
WARNING:Xst:647 - Input <ahbi.testrst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dmao.start> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dmao.haddr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.testoen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.hready> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.hgrant> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.hcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dmao.mexc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <uarto.tsempty> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dmao.retry> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <uarto.enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.scanen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.hrdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.testen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <r.hresp> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Using one-hot encoding for signal <r.state>.
    Found 30-bit adder for signal <newaddr$add0000> created at line 233.
    Found 6-bit subtractor for signal <newlen$sub0001> created at line 273.
    Found 32-bit register for signal <r.addr>.
    Found 2-bit register for signal <r.clen>.
    Found 32-bit register for signal <r.data>.
    Found 6-bit register for signal <r.len>.
    Found 6-bit register for signal <r.state>.
    Found 1-bit register for signal <r.write>.
    Found 2-bit adder for signal <v.clen$add0001> created at line 233.
    Summary:
        inferred  79 D-type flip-flop(s).
        inferred   3 Adder/Subtractor(s).
Unit <dcom> synthesized.


Synthesizing Unit <ahbmst_2>.
    Related source file is "../../lib/gaisler/misc/ahbmst.vhd".
WARNING:Xst:647 - Input <ahbi.testrst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.testoen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.hgrant<0:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.hgrant<3:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.hcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.scanen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbi.testen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <r.active>.
    Found 1-bit register for signal <r.grant>.
    Found 1-bit register for signal <r.retry>.
    Found 1-bit register for signal <r.start>.
    Summary:
        inferred   4 D-type flip-flop(s).
Unit <ahbmst_2> synthesized.


Synthesizing Unit <jtagcom>.
    Related source file is "../../lib/gaisler/jtag/jtagcom.vhd".
WARNING:Xst:647 - Input <dmao.start> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dmao.haddr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <tapo.inst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <tapo.upd> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dmao.mexc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <tapo.capt> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dmao.retry> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 35-bit register for signal <r.addr>.
    Found 1-bit register for signal <r.asel<0>>.
    Found 33-bit register for signal <r.data>.
    Found 1-bit register for signal <r.dsel<0>>.
    Found 1-bit register for signal <r.shift<0>>.
    Found 1-bit register for signal <r.shift2>.
    Found 1-bit register for signal <r.shift3>.
    Found 1-bit register for signal <r.state<0>>.
    Found 1-bit register for signal <r.tck<0>>.
    Found 1-bit register for signal <r.tck2>.
    Found 1-bit register for signal <r.tdi<0>>.
    Found 1-bit register for signal <r.tdi2>.
    Found 1-bit register for signal <r.trst<0>>.
    Found 8-bit adder for signal <v.addr_9_2$add0000> created at line 233.
    Summary:
        inferred  79 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
Unit <jtagcom> synthesized.


Synthesizing Unit <sdmctrl>.
    Related source file is "../../lib/gaisler/memctrl/sdmctrl.vhd".
WARNING:Xst:647 - Input <apbi.psel<1:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.pirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.pwdata<11:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <sdmo.vhready> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <sdi.error> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.scanen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sdi.edac> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.testen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.paddr<31:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.paddr<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <wpo.wprothit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sdi.brmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.testrst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sdi.nhtrans<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sdi.merror> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sdi.haddr<31:30>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sdi.haddr<9:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <apbi.testoen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <r.wprothit> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <r.cfg.pageburst> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <r.aload> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Using one-hot encoding for signal <r.istate>.
    Using one-hot encoding for signal <r.sdstate>.
    Using one-hot encoding for signal <r.cmstate>.
    Using one-hot encoding for signal <r.mstate>.
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <r.sdstate> of Case statement line 246 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
        - add an 'INIT' attribute on signal <r.sdstate> (optimization is then done without any risk)
        - use the attribute 'signal_encoding user' to avoid onehot optimization
        - use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <r.mstate> of Case statement line 0 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
        - add an 'INIT' attribute on signal <r.mstate> (optimization is then done without any risk)
        - use the attribute 'signal_encoding user' to avoid onehot optimization
        - use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
    Found 15-bit register for signal <r.address>.
    Found 1-bit register for signal <r.bdelay>.
    Found 1-bit register for signal <r.bdrive>.
    Found 1-bit register for signal <r.burst>.
    Found 1-bit register for signal <r.busy>.
    Found 1-bit register for signal <r.casn>.
    Found 3-bit register for signal <r.cfg.bsize>.
    Found 1-bit register for signal <r.cfg.casdel>.
    Found 1-bit register for signal <r.cfg.cke>.
    Found 3-bit register for signal <r.cfg.command>.
    Found 2-bit register for signal <r.cfg.csize>.
    Found 4-bit register for signal <r.cfg.ds>.
    Found 2-bit register for signal <r.cfg.mobileen>.
    Found 6-bit register for signal <r.cfg.pasr>.
    Found 3-bit register for signal <r.cfg.pmode>.
    Found 15-bit register for signal <r.cfg.refresh>.
    Found 1-bit register for signal <r.cfg.renable>.
    Found 4-bit register for signal <r.cfg.tcsr>.
    Found 3-bit register for signal <r.cfg.trfc>.
    Found 1-bit register for signal <r.cfg.trp>.
    Found 4-bit register for signal <r.cfg.txsr>.
    Found 3-bit register for signal <r.cmstate>.
    Found 8-bit register for signal <r.dqm>.
    Found 22-bit register for signal <r.haddr>.
    Found 1-bit register for signal <r.hready>.
    Found 1-bit register for signal <r.hsel>.
    Found 3-bit register for signal <r.icnt>.
    Found 3-bit subtractor for signal <r.icnt$addsub0000> created at line 273.
    Found 4-bit register for signal <r.idlecnt>.
    Found 6-bit register for signal <r.istate>.
    Found 2-bit register for signal <r.mstate>.
    Found 1-bit register for signal <r.rasn>.
    Found 15-bit register for signal <r.refresh>.
    Found 2-bit register for signal <r.sdcsn>.
    Found 19-bit register for signal <r.sdstate>.
    Found 1-bit register for signal <r.sdwen>.
    Found 3-bit register for signal <r.sref_tmpcom>.
    Found 1-bit register for signal <r.startsd>.
    Found 4-bit register for signal <r.trfc>.
    Found 13-bit 4-to-1 multiplexer for signal <raddr$mux0000> created at line 215.
    Found 1-bit 8-to-1 multiplexer for signal <res$mux0000> created at line 141.
    Found 1-bit 8-to-1 multiplexer for signal <res1$mux0000> created at line 141.
    Found 1-bit 8-to-1 multiplexer for signal <res3$mux0000> created at line 141.
    Found 3-bit comparator not equal for signal <v.cfg.command_1$cmp_ne0000> created at line 609.
    Found 2-bit comparator not equal for signal <v.cfg.command_1$cmp_ne0001> created at line 606.
    Found 2-bit comparator not equal for signal <v.cfg.command_1$cmp_ne0002> created at line 603.
    Found 4-bit subtractor for signal <v.idlecnt$sub0000> created at line 273.
    Found 22-bit comparator equal for signal <v.rasn$cmp_eq0005> created at line 311.
    Found 15-bit subtractor for signal <v.refresh$sub0000> created at line 273.
    Found 4-bit subtractor for signal <v.trfc$sub0000> created at line 273.
    Summary:
        inferred 169 D-type flip-flop(s).
        inferred   4 Adder/Subtractor(s).
        inferred   4 Comparator(s).
        inferred  16 Multiplexer(s).
Unit <sdmctrl> synthesized.


Synthesizing Unit <dsu3>.
    Related source file is "../../lib/gaisler/leon3/dsu3.vhd".
Unit <dsu3> synthesized.


Synthesizing Unit <ahbuart>.
    Related source file is "../../lib/gaisler/uart/ahbuart.vhd".
Unit <ahbuart> synthesized.


Synthesizing Unit <mctrl>.
    Related source file is "../../lib/esa/memoryctrl/mctrl.vhd".
WARNING:Xst:647 - Input <ahbsi.hsel<1:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbsi.hmastlock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbsi.hirq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbsi.testoen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <memi.edac> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbsi.hsize<2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbsi.hprot> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbsi.scanen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbsi.testen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <memi.writen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <memo.ce> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <memi.cb> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbsi.hcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbsi.hmbsel<3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <memi.wrn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbsi.hmaster> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ahbsi.testrst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <memi.scb> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <sdmo.vhready> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <sdmo.bsel> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <sdi.merror> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:646 - Signal <r.sd> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <r.readdata<31:24>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <r.nbdrive> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <r.mcfg2.brdyen> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <r.bstate> of Case statement line 474 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
        - add an 'INIT' attribute on signal <r.bstate> (optimization is then done without any risk)
        - use the attribute 'signal_encoding user' to avoid onehot optimization
        - use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
    Using one-hot encoding for signal <r.bstate>.
    Found 32-bit 4-to-1 multiplexer for signal <ahbso.hrdata>.
    Found 32-bit register for signal <r.address>.
    Found 3-bit register for signal <r.area>.
    Found 4-bit register for signal <r.bdrive>.
    Found 1-bit register for signal <r.bexcn>.
    Found 1-bit register for signal <r.brdyn>.
    Found 1-bit register for signal <r.brmw>.
    Found 8-bit register for signal <r.bstate>.
    Found 2-bit register for signal <r.busw>.
    Found 32-bit register for signal <r.data>.
    Found 1-bit register for signal <r.echeck>.
    Found 32-bit register for signal <r.haddr>.
    Found 3-bit register for signal <r.hburst>.
    Found 2-bit register for signal <r.hresp>.
    Found 1-bit register for signal <r.hsel>.
    Found 2-bit register for signal <r.htrans>.
    Found 1-bit register for signal <r.hwrite>.
    Found 2-bit register for signal <r.iosn>.
    Found 4-bit register for signal <r.mben>.
    Found 1-bit register for signal <r.mcfg1.bexcen>.
    Found 1-bit register for signal <r.mcfg1.brdyen>.
    Found 1-bit register for signal <r.mcfg1.ioen>.
    Found 2-bit register for signal <r.mcfg1.iowidth>.
    Found 4-bit register for signal <r.mcfg1.iows>.
    Found 4-bit register for signal <r.mcfg1.romrws>.
    Found 2-bit register for signal <r.mcfg1.romwidth>.
    Found 1-bit register for signal <r.mcfg1.romwrite>.
    Found 4-bit register for signal <r.mcfg1.romwws>.
    Found 4-bit register for signal <r.mcfg2.rambanksz>.
    Found 2-bit register for signal <r.mcfg2.ramrws>.
    Found 2-bit register for signal <r.mcfg2.ramwidth>.
    Found 2-bit register for signal <r.mcfg2.ramwws>.
    Found 1-bit register for signal <r.mcfg2.rmw>.
    Found 1-bit register for signal <r.mcfg2.sdren>.
    Found 1-bit register for signal <r.mcfg2.srdis>.
    Found 1-bit register for signal <r.oen>.
    Found 5-bit register for signal <r.ramoen>.
    Found 5-bit register for signal <r.ramsn>.
    Found 1-bit register for signal <r.read>.
    Found 32-bit register for signal <r.readdata>.
    Found 1-bit register for signal <r.ready>.
    Found 1-bit register for signal <r.ready8>.
    Found 2-bit register for signal <r.romsn>.
    Found 15-bit register for signal <r.sa>.
    Found 1-bit register for signal <r.sdhsel>.
    Found 64-bit register for signal <r.sdwritedata>.
    Found 2-bit register for signal <r.size>.
    Found 1-bit register for signal <r.srhsel>.
    Found 32-bit register for signal <r.writedata>.
    Found 16-bit register for signal <r.writedata8>.
    Found 1-bit register for signal <r.writen>.
    Found 4-bit register for signal <r.wrn>.
    Found 4-bit register for signal <r.ws>.
    Found 32-bit register for signal <rbdrive>.
    Found 1-bit 4-to-1 multiplexer for signal <regsd_0$mux0000> created at line 697.
    Found 1-bit 4-to-1 multiplexer for signal <regsd_1$mux0000> created at line 697.
    Found 1-bit 4-to-1 multiplexer for signal <regsd_10$mux0000> created at line 697.
    Found 1-bit 4-to-1 multiplexer for signal <regsd_11$mux0000> created at line 697.
    Found 1-bit 4-to-1 multiplexer for signal <regsd_12$mux0000> created at line 697.
    Found 1-bit 4-to-1 multiplexer for signal <regsd_13$mux0000> created at line 697.
    Found 1-bit 4-to-1 multiplexer for signal <regsd_14$mux0000> created at line 697.
    Found 1-bit 4-to-1 multiplexer for signal <regsd_15$mux0000> created at line 697.
    Found 1-bit 4-to-1 multiplexer for signal <regsd_16$mux0000> created at line 697.
    Found 1-bit 4-to-1 multiplexer for signal <regsd_17$mux0000> created at line 697.
    Found 1-bit 4-to-1 multiplexer for signal <regsd_18$mux0000> created at line 697.
    Found 1-bit 4-to-1 multiplexer for signal <regsd_19$mux0000> created at line 697.
    Found 1-bit 4-to-1 multiplexer for signal <regsd_2$mux0000> created at line 697.
    Found 1-bit 4-to-1 multiplexer for signal <regsd_20$mux0000> created at line 697.
    Found 1-bit 4-to-1 multiplexer for signal <regsd_21$mux0000> created at line 697.
    Found 1-bit 4-to-1 multiplexer for signal <regsd_22$mux0000> created at line 697.
    Found 1-bit 4-to-1 multiplexer for signal <regsd_23$mux0000> created at line 697.
    Found 1-bit 4-to-1 multiplexer for signal <regsd_24$mux0000> created at line 697.
    Found 1-bit 4-to-1 multiplexer for signal <regsd_25$mux0000> created at line 697.
    Found 1-bit 4-to-1 multiplexer for signal <regsd_26$mux0000> created at line 697.
    Found 1-bit 4-to-1 multiplexer for signal <regsd_27$mux0000> created at line 697.
    Found 1-bit 4-to-1 multiplexer for signal <regsd_28$mux0000> created at line 697.
    Found 1-bit 4-to-1 multiplexer for signal <regsd_29$mux0000> created at line 697.
    Found 1-bit 4-to-1 multiplexer for signal <regsd_3$mux0000> created at line 697.
    Found 1-bit 4-to-1 multiplexer for signal <regsd_30$mux0000> created at line 697.
    Found 1-bit 4-to-1 multiplexer for signal <regsd_31$mux0000> created at line 697.
    Found 1-bit 4-to-1 multiplexer for signal <regsd_4$mux0000> created at line 697.
    Found 1-bit 4-to-1 multiplexer for signal <regsd_5$mux0000> created at line 697.
    Found 1-bit 4-to-1 multiplexer for signal <regsd_6$mux0000> created at line 697.
    Found 1-bit 4-to-1 multiplexer for signal <regsd_7$mux0000> created at line 697.
    Found 1-bit 4-to-1 multiplexer for signal <regsd_8$mux0000> created at line 697.
    Found 1-bit 4-to-1 multiplexer for signal <regsd_9$mux0000> created at line 697.
    Found 1-bit 16-to-1 multiplexer for signal <res$mux0000> created at line 141.
    Found 1-bit 16-to-1 multiplexer for signal <res1$mux0000> created at line 141.
    Found 64-bit register for signal <rsbdrive>.
    Found 2-bit adder for signal <v.address_1_0$add0000> created at line 233.
    Found 4-bit subtractor for signal <v.ws$sub0000> created at line 273.
    Found 1-bit 4-to-1 multiplexer for signal <writedata_0$mux0000> created at line 432.
    Found 1-bit 4-to-1 multiplexer for signal <writedata_1$mux0000> created at line 432.
    Found 1-bit 4-to-1 multiplexer for signal <writedata_2$mux0000> created at line 432.
    Found 1-bit 4-to-1 multiplexer for signal <writedata_3$mux0000> created at line 432.
    Found 1-bit 4-to-1 multiplexer for signal <writedata_4$mux0000> created at line 432.
    Found 1-bit 4-to-1 multiplexer for signal <writedata_5$mux0000> created at line 432.
    Found 1-bit 4-to-1 multiplexer for signal <writedata_6$mux0000> created at line 432.
    Found 1-bit 4-to-1 multiplexer for signal <writedata_7$mux0000> created at line 432.
    Summary:
        inferred 449 D-type flip-flop(s).
        inferred   2 Adder/Subtractor(s).
        inferred  74 Multiplexer(s).
Unit <mctrl> synthesized.


Synthesizing Unit <virtex_clkpad>.
    Related source file is "../../lib/techmap/unisim/pads_unisim.vhd".
WARNING:Xst:646 - Signal <rst> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ol3> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ol2> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ol> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <gnd> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <virtex_clkpad> synthesized.


Synthesizing Unit <virtex_inpad>.
    Related source file is "../../lib/techmap/unisim/pads_unisim.vhd".
Unit <virtex_inpad> synthesized.


Synthesizing Unit <clkgen_spartan3>.
    Related source file is "../../lib/techmap/unisim/clkgen_unisim.vhd".
WARNING:Xst:647 - Input <cgi.pllctrl> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cgi.clksel> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pciclkin> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1780 - Signal <pciclkint> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <dll2xrst> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <clk_r> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <clk_p> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <clk_o> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <clk_n> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <clk_m> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <clk_l> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 4-bit register for signal <dll1rst>.
    Summary:
        inferred   4 D-type flip-flop(s).
Unit <clkgen_spartan3> synthesized.


Synthesizing Unit <virtex_outpad_1>.
    Related source file is "../../lib/techmap/unisim/pads_unisim.vhd".
Unit <virtex_outpad_1> synthesized.


Synthesizing Unit <regfile_3p>.
    Related source file is "../../lib/techmap/maps/regfile_3p.vhd".
WARNING:Xst:647 - Input <testin> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <regfile_3p> synthesized.


Synthesizing Unit <cache>.
    Related source file is "../../lib/gaisler/leon3/cache.vhd".
WARNING:Xst:647 - Input <hclk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1780 - Signal <gnd> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Unit <cache> synthesized.


Synthesizing Unit <rf_stage>.
    Related source file is "../../lib/gaisler/vlog/RF_stage1.v".
WARNING:Xst:647 - Input <wb_din_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <INS_NO> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <CLK_NO> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <BUS6095> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <BUS6061> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <BUS3237> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <BUS3236> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Unit <rf_stage> synthesized.


Synthesizing Unit <forward>.
    Related source file is "../../lib/gaisler/vlog/forward.v".
Unit <forward> synthesized.


Synthesizing Unit <hazard_unit>.
    Related source file is "../../lib/gaisler/vlog/hazard_unit.v".
Unit <hazard_unit> synthesized.


Synthesizing Unit <mips_alu>.
    Related source file is "../../lib/gaisler/vlog/EXEC_stage.v".
Unit <mips_alu> synthesized.


Synthesizing Unit <pipelinedregs>.
    Related source file is "../../lib/gaisler/vlog/decode_pipe1.v".
WARNING:Xst:646 - Signal <dmem_ctl_o> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <pipelinedregs> synthesized.


Synthesizing Unit <virtex2_syncram_1>.
    Related source file is "../../lib/techmap/unisim/memory_unisim.vhd".
WARNING:Xst:646 - Signal <ya<19:9>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <xa<19:9>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <do<100:28>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <di<100:72>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <virtex2_syncram_1> synthesized.


Synthesizing Unit <virtex2_syncram_2>.
    Related source file is "../../lib/techmap/unisim/memory_unisim.vhd".
WARNING:Xst:646 - Signal <ya> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <xa<19:10>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <do<104:32>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <di<104:36>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <virtex2_syncram_2> synthesized.


Synthesizing Unit <virtex2_syncram_dp>.
    Related source file is "../../lib/techmap/unisim/memory_unisim.vhd".
WARNING:Xst:647 - Input <enable1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <enable2> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <do2<60:24>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <do1<60:24>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <di2<60:36>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <di1<60:36>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <addr2<19:9>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <addr1<19:9>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <virtex2_syncram_dp> synthesized.


Synthesizing Unit <virtex2_syncram64>.
    Related source file is "../../lib/techmap/unisim/memory_unisim.vhd".
WARNING:Xst:646 - Signal <ya<19:9>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <xa<19:9>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <virtex2_syncram64> synthesized.


Synthesizing Unit <virtex_toutpad>.
    Related source file is "../../lib/techmap/unisim/pads_unisim.vhd".
Unit <virtex_toutpad> synthesized.


Synthesizing Unit <virtex_outpad_2>.
    Related source file is "../../lib/techmap/unisim/pads_unisim.vhd".
Unit <virtex_outpad_2> synthesized.


Synthesizing Unit <spartan3_tap>.
    Related source file is "../../lib/techmap/unisim/tap_unisim.vhd".
Unit <spartan3_tap> synthesized.


Synthesizing Unit <virtex_iopad>.
    Related source file is "../../lib/techmap/unisim/pads_unisim.vhd".
Unit <virtex_iopad> synthesized.


Synthesizing Unit <clkpad>.
    Related source file is "../../lib/techmap/maps/clkpad.vhd".
Unit <clkpad> synthesized.


Synthesizing Unit <inpad>.
    Related source file is "../../lib/techmap/maps/inpad.vhd".
Unit <inpad> synthesized.


Synthesizing Unit <clkgen>.
    Related source file is "../../lib/techmap/maps/clkgen.vhd".
WARNING:Xst:1305 - Output <clk4x> is never assigned. Tied to value 0.
WARNING:Xst:1780 - Signal <sdintclk> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <intclk> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Unit <clkgen> synthesized.


Synthesizing Unit <outpad_1>.
    Related source file is "../../lib/techmap/maps/outpad.vhd".
WARNING:Xst:646 - Signal <vcc> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <padx> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <gnd> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <outpad_1> synthesized.


Synthesizing Unit <odpad>.
    Related source file is "../../lib/techmap/maps/odpad.vhd".
WARNING:Xst:1780 - Signal <padx> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Unit <odpad> synthesized.


Synthesizing Unit <outpad_2>.
    Related source file is "../../lib/techmap/maps/outpad.vhd".
WARNING:Xst:646 - Signal <vcc> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <padx> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <gnd> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <outpad_2> synthesized.


Synthesizing Unit <iopad_1>.
    Related source file is "../../lib/techmap/maps/iopad.vhd".
Unit <iopad_1> synthesized.


Synthesizing Unit <exec_stage>.
    Related source file is "../../lib/gaisler/vlog/EXEC_stage.v".
Unit <exec_stage> synthesized.


Synthesizing Unit <decode_pipe>.
    Related source file is "../../lib/gaisler/vlog/decode_pipe1.v".
WARNING:Xst:1780 - Signal <dmem_ctl_o> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Unit <decode_pipe> synthesized.


Synthesizing Unit <syncram_1>.
    Related source file is "../../lib/techmap/maps/syncram.vhd".
WARNING:Xst:647 - Input <testin> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1780 - Signal <wena> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <rena> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <gnd4> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <syncram_1> synthesized.


Synthesizing Unit <syncram_2>.
    Related source file is "../../lib/techmap/maps/syncram.vhd".
WARNING:Xst:647 - Input <testin> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1780 - Signal <wena> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <rena> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <gnd4> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <syncram_2> synthesized.


Synthesizing Unit <syncram_dp>.
    Related source file is "../../lib/techmap/maps/syncram_dp.vhd".
WARNING:Xst:647 - Input <testin> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <syncram_dp> synthesized.


Synthesizing Unit <syncram64>.
    Related source file is "../../lib/techmap/maps/syncram64.vhd".
WARNING:Xst:647 - Input <testin> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <syncram64> synthesized.


Synthesizing Unit <tap>.
    Related source file is "../../lib/techmap/maps/tap.vhd".
WARNING:Xst:647 - Input <tck> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <tdi> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <tdo> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <testrst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <tms> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <tapi_tdo2> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <tapi_en1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <testen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <tdoen> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <trst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <tapo_inst> is never assigned. Tied to value 00000000.
WARNING:Xst:1780 - Signal <tckn> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ltckn> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ltck> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Unit <tap> synthesized.


Synthesizing Unit <outpad_3>.
    Related source file is "../../lib/techmap/maps/outpad.vhd".
WARNING:Xst:646 - Signal <vcc> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <padx> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <gnd> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <outpad_3> synthesized.


Synthesizing Unit <iopad_2>.
    Related source file is "../../lib/techmap/maps/iopad.vhd".
Unit <iopad_2> synthesized.


Synthesizing Unit <ahbjtag>.
    Related source file is "../../lib/gaisler/jtag/ahbjtag.vhd".
Unit <ahbjtag> synthesized.


Synthesizing Unit <outpadv_1>.
    Related source file is "../../lib/techmap/maps/outpad.vhd".
Unit <outpadv_1> synthesized.


Synthesizing Unit <outpadv_2>.
    Related source file is "../../lib/techmap/maps/outpad.vhd".
Unit <outpadv_2> synthesized.


Synthesizing Unit <outpadv_3>.
    Related source file is "../../lib/techmap/maps/outpad.vhd".
Unit <outpadv_3> synthesized.


Synthesizing Unit <outpadv_4>.
    Related source file is "../../lib/techmap/maps/outpad.vhd".
Unit <outpadv_4> synthesized.


Synthesizing Unit <iopadv>.
    Related source file is "../../lib/techmap/maps/iopad.vhd".
Unit <iopadv> synthesized.


Synthesizing Unit <outpadv_5>.
    Related source file is "../../lib/techmap/maps/outpad.vhd".
Unit <outpadv_5> synthesized.


Synthesizing Unit <cachemem>.
    Related source file is "../../lib/gaisler/leon3/cachemem.vhd".
WARNING:Xst:647 - Input <crami.dcramin.ptag<0><11:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <crami.dcramin.ptag<1:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <crami.icramin.ldramin.write> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <crami.icramin.dpar> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <crami.dcramin.tpar> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <crami.dcramin.ldramin.read> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <crami.icramin.ldramin.enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <crami.icramin.ctx> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <crami.icramin.ldramin.read> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <crami.dcramin.address<19:10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <crami.dcramin.ldramin.address<23:10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <crami.dcramin.saddress<19:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <crami.dcramin.tag<0><11:10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <crami.dcramin.tag<0><8:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <crami.dcramin.tag<1:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <crami.icramin.tpar> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <crami.dcramin.spar> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <crami.dcramin.ldramin.write> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <crami.dcramin.flush> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <crami.dcramin.tdiag> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <crami.dcramin.ctx> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <crami.dcramin.dpar> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <crami.icramin.address<19:10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <crami.dcramin.ldramin.enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <crami.icramin.tag<0><11:10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <crami.icramin.tag<0><8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <crami.icramin.tag<1><11:10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <crami.icramin.tag<1><8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <crami.icramin.tag<2:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <crami.dcramin.ddiag> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <crami.dcramin.stag> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1780 - Signal <vitdatain<0:1>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1781 - Signal <vitdatain<2:3>> is used but never assigned. Tied to default value.
WARNING:Xst:1780 - Signal <vdtdatain<0>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1781 - Signal <vdtdatain<1:3>> is used but never assigned. Tied to default value.
WARNING:Xst:646 - Signal <vcc> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <lddatain> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ldataout> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ldaddr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <itwrite<2:3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <itdataout<2:3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <itdatain<0><28>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <itdatain<1><28>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <itdatain<2:3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ildataout> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ildaddr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <idwrite<2:3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <iddataout<2:3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <gnd> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dtwrite3> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dtwrite2<1:3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dtwrite<1:3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dtenable2<1:3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dtenable<1:3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <dtdataout3<0>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dtdataout3<1:3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dtdataout2<1:3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dtdataout<1:3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dtdatainu> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dtdatain3> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dtdatain2<0><24>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dtdatain2<1:3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dtdatain<0><24>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dtdatain<1:3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ddwrite<1:3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ddenable<1:3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dddataout<1:3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dddatain<1:3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <cachemem> synthesized.


Synthesizing Unit <tbufmem>.
    Related source file is "../../lib/gaisler/leon3/tbufmem.vhd".
WARNING:Xst:647 - Input <di.addr<11:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <tbufmem> synthesized.


Synthesizing Unit <mips_core>.
    Related source file is "../../lib/gaisler/vlog/core1.v".
WARNING:Xst:1780 - Signal <NET1375> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <BUS9884> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <BUS7772> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <BUS27031> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <BUS22401> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <BUS18211> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <BUS15471> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Unit <mips_core> synthesized.


Synthesizing Unit <top>.
    Related source file is "../../lib/gaisler/leon3/top.vhd".
Unit <top> synthesized.


Synthesizing Unit <proc3>.
    Related source file is "../../lib/gaisler/leon3/proc3.vhd".
WARNING:Xst:1305 - Output <cpi.e.trap> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <cpi.m.annul> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <fpi.m.cnt> is never assigned. Tied to value 00.
WARNING:Xst:647 - Input <cpo.exc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <tbo.data> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <cpi.x.cnt> is never assigned. Tied to value 00.
WARNING:Xst:647 - Input <dbgi.berror> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dbgi.ddata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dbgi.dsuen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <fpo.dbg.data> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <dbgo.ipend> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <cpi.m.cnt> is never assigned. Tied to value 00.
WARNING:Xst:1305 - Output <cpi.d.inst> is never assigned. Tied to value 00000000000000000000000000000000.
WARNING:Xst:647 - Input <cpo.cc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <cpi.d.annul> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <dbgi.reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <fpi.dbg.data> is never assigned. Tied to value 00000000000000000000000000000000.
WARNING:Xst:647 - Input <dbgi.step> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <fpi.m.inst> is never assigned. Tied to value 00000000000000000000000000000000.
WARNING:Xst:1305 - Output <fpi.d.pc> is never assigned. Tied to value 00000000000000000000000000000000.
WARNING:Xst:1305 - Output <cpi.a.annul> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <fpi.exack> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <fpi.dbg.fsr> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <tbi.addr> is never assigned. Tied to value 000000000000.
WARNING:Xst:1305 - Output <cpi.e.inst> is never assigned. Tied to value 00000000000000000000000000000000.
WARNING:Xst:1305 - Output <dbgo.halt> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <cpi.x.trap> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <fpo.data> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <fpi.d.pv> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <fpi.a.trap> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <dbgi.timer> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dbgi.dbreak> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <fpi.dbg.enable> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <irqo.irl> is never assigned. Tied to value 0000.
WARNING:Xst:1305 - Output <fpi.a.cnt> is never assigned. Tied to value 00.
WARNING:Xst:1305 - Output <cpi.lddata> is never assigned. Tied to value 00000000000000000000000000000000.
WARNING:Xst:647 - Input <irqi.rstvec> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dbgi.bsoft> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cpo.dbg.data> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <cpi.exack> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <dbgo.dsumode> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <fpo.cc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <fpi.e.pc> is never assigned. Tied to value 00000000000000000000000000000000.
WARNING:Xst:1305 - Output <cpi.dbg.data> is never assigned. Tied to value 00000000000000000000000000000000.
WARNING:Xst:1305 - Output <cpi.a.cnt> is never assigned. Tied to value 00.
WARNING:Xst:1305 - Output <fpi.e.pv> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <fpi.m.annul> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <irqi.irl> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <cpi.d.pc> is never assigned. Tied to value 00000000000000000000000000000000.
WARNING:Xst:1305 - Output <fpi.d.trap> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <cpi.x.inst> is never assigned. Tied to value 00000000000000000000000000000000.
WARNING:Xst:1305 - Output <dbgo.dsu> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <tbi.write> is never assigned. Tied to value 0000.
WARNING:Xst:1305 - Output <fpi.a.inst> is never assigned. Tied to value 00000000000000000000000000000000.
WARNING:Xst:647 - Input <cpo.data> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <cpi.d.pv> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <cpi.dbg.enable> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <fpi.x.pc> is never assigned. Tied to value 00000000000000000000000000000000.
WARNING:Xst:1305 - Output <dbgo.idle> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <dbgo.icnt> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <fpi.x.pv> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <cpi.e.annul> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <fpi.e.trap> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <cpo.ldlock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <cpi.m.trap> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <irqo.pwd> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <fpi.d.annul> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <fpi.e.cnt> is never assigned. Tied to value 00.
WARNING:Xst:1305 - Output <cpi.x.annul> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <irqo.intack> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <dbgi.dwrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cpo.holdn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <fpi.a.annul> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <cpi.e.pc> is never assigned. Tied to value 00000000000000000000000000000000.
WARNING:Xst:1305 - Output <dbgo.data> is never assigned. Tied to value 00000000000000000000000000000000.
WARNING:Xst:1305 - Output <cpi.e.pv> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <fpi.d.inst> is never assigned. Tied to value 00000000000000000000000000000000.
WARNING:Xst:1305 - Output <cpi.e.cnt> is never assigned. Tied to value 00.
WARNING:Xst:647 - Input <dbgi.daddr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dbgi.denable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <dbgo.error> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <fpi.m.pc> is never assigned. Tied to value 00000000000000000000000000000000.
WARNING:Xst:1305 - Output <cpi.x.pc> is never assigned. Tied to value 00000000000000000000000000000000.
WARNING:Xst:1305 - Output <tbi.data> is never assigned. Tied to value 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000.
WARNING:Xst:1305 - Output <fpi.m.pv> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <fpi.e.inst> is never assigned. Tied to value 00000000000000000000000000000000.
WARNING:Xst:1305 - Output <fpi.x.trap> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <cpi.x.pv> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <fpi.dbg.addr> is never assigned. Tied to value 00000.
WARNING:Xst:647 - Input <irqi.rst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dbgi.btrapa> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <irqi.run> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <fpi.a.pc> is never assigned. Tied to value 00000000000000000000000000000000.
WARNING:Xst:647 - Input <dbgi.btrape> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <fpi.d.cnt> is never assigned. Tied to value 00.
WARNING:Xst:1305 - Output <fpi.a_rs1> is never assigned. Tied to value 00000.
WARNING:Xst:1305 - Output <cpi.m.inst> is never assigned. Tied to value 00000000000000000000000000000000.
WARNING:Xst:647 - Input <dbgi.tenable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <fpi.a.pv> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <cpi.dbg.write> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <cpi.a.trap> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <fpi.lddata> is never assigned. Tied to value 00000000000000000000000000000000.
WARNING:Xst:647 - Input <fpo.ccv> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <fpi.flush> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <dbgo.pwd> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <cpi.d.cnt> is never assigned. Tied to value 00.
WARNING:Xst:1305 - Output <cpi.a_rs1> is never assigned. Tied to value 00000.
WARNING:Xst:1305 - Output <tbi.diag> is never assigned. Tied to value 0000.
WARNING:Xst:647 - Input <dbgi.halt> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <cpi.dbg.fsr> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <fpi.e.annul> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <cpo.ccv> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <cpi.m.pc> is never assigned. Tied to value 00000000000000000000000000000000.
WARNING:Xst:1305 - Output <fpi.dbg.write> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <cpi.dbg.addr> is never assigned. Tied to value 00000.
WARNING:Xst:1305 - Output <fpi.x.annul> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <fpi.x.inst> is never assigned. Tied to value 00000000000000000000000000000000.
WARNING:Xst:1305 - Output <cpi.m.pv> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <dbgo.crdy> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <rfi.diag> is never assigned. Tied to value 0000.
WARNING:Xst:647 - Input <dbgi.bwatch> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <cpi.flush> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <cpi.a.pc> is never assigned. Tied to value 00000000000000000000000000000000.
WARNING:Xst:1305 - Output <cpi.d.trap> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <cpi.a.pv> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <cpi.a.inst> is never assigned. Tied to value 00000000000000000000000000000000.
WARNING:Xst:1305 - Output <fpi.x.cnt> is never assigned. Tied to value 00.
WARNING:Xst:1305 - Output <tbi.enable> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <fpo.ldlock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <fpi.m.trap> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <fpo.exc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <mulo.result> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <mulo.ready> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <mulo.nready> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <mulo.icc> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <muli.start> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <muli.signed> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <muli.op2> is used but never assigned. This sourceless signal will be automatically connected to value 000000000000000000000000000000000.
WARNING:Xst:653 - Signal <muli.op1> is used but never assigned. This sourceless signal will be automatically connected to value 000000000000000000000000000000000.
WARNING:Xst:653 - Signal <muli.mac> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <muli.flush> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <muli.acc> is used but never assigned. This sourceless signal will be automatically connected to value 0000000000000000000000000000000000000000.
WARNING:Xst:646 - Signal <ico.mexc> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ico.idle> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ico.flush> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ico.diagrdy> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ico.diagdata> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ico.cfg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <ici.su> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ici.pnull> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ici.dpc> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:646 - Signal <divo.result> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <divo.ready> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <divo.nready> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <divo.icc> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <divi.y> is used but never assigned. This sourceless signal will be automatically connected to value 000000000000000000000000000000000.
WARNING:Xst:653 - Signal <divi.start> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <divi.signed> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <divi.op2> is used but never assigned. This sourceless signal will be automatically connected to value 000000000000000000000000000000000.
WARNING:Xst:653 - Signal <divi.op1> is used but never assigned. This sourceless signal will be automatically connected to value 000000000000000000000000000000000.
WARNING:Xst:653 - Signal <divi.flush> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:646 - Signal <dco.werr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dco.testen> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dco.scanen> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dco.mexc> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dco.idle> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dco.icdiag.tag> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dco.icdiag.scanen> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dco.icdiag.read> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dco.icdiag.pflushtyp> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dco.icdiag.pflushaddr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dco.icdiag.pflush> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dco.icdiag.ilramen> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dco.icdiag.ilock> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dco.icdiag.flush> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dco.icdiag.enable> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dco.icdiag.ctx> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dco.icdiag.cctrl.ifrz> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dco.icdiag.cctrl.ics> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dco.icdiag.cctrl.dsnoop> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dco.icdiag.cctrl.dfrz> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dco.icdiag.cctrl.dcs> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dco.icdiag.cctrl.burst> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dco.icdiag.addr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dco.cache> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <proc3> synthesized.


Synthesizing Unit <leon3s>.
    Related source file is "../../lib/gaisler/leon3/leon3s.vhd".
WARNING:Xst:1780 - Signal <wd> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <rd2> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <rd1> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <holdn> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <fpo.exc> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <fpo.dbg.data> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <fpo.data> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <fpo.cc> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:646 - Signal <fpi.x.trap> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.x.pv> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.x.pc> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.x.inst> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.x.cnt> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.x.annul> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.m.trap> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.m.pv> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.m.pc> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.m.inst> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.m.cnt> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.m.annul> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.lddata> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.flush> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.exack> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.e.trap> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.e.pv> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.e.pc> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.e.inst> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.e.cnt> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.e.annul> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.dbg.write> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.dbg.fsr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.dbg.enable> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.dbg.data> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.dbg.addr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.d.trap> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.d.pv> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.d.pc> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.d.inst> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.d.cnt> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.d.annul> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.a_rs1> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.a.trap> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.a.pv> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.a.pc> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.a.inst> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.a.cnt> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fpi.a.annul> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.x.trap> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.x.pv> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.x.pc> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.x.inst> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.x.cnt> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.x.annul> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.m.trap> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.m.pv> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.m.pc> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.m.inst> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.m.cnt> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.m.annul> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.lddata> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.flush> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.exack> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.e.trap> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.e.pv> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.e.pc> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.e.inst> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.e.cnt> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.e.annul> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.dbg.write> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.dbg.fsr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.dbg.enable> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.dbg.data> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.dbg.addr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.d.trap> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.d.pv> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.d.pc> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.d.inst> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.d.cnt> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.d.annul> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.a_rs1> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.a.trap> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.a.pv> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.a.pc> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.a.inst> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.a.cnt> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cpi.a.annul> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 1-bit register for signal <rst>.
    Summary:
        inferred   1 D-type flip-flop(s).
Unit <leon3s> synthesized.


Synthesizing Unit <leon3mp>.
    Related source file is "leon3mp.vhd".
WARNING:Xst:2565 - Inout <usb_d(4)> is never assigned.
WARNING:Xst:2565 - Inout <usb_d(5)> is never assigned.
WARNING:Xst:647 - Input <usb_txready> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2565 - Inout <usb_d(6)> is never assigned.
WARNING:Xst:647 - Input <ata_intrq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2565 - Inout <usb_d(7)> is never assigned.
WARNING:Xst:2565 - Inout <usb_d(10)> is never assigned.
WARNING:Xst:647 - Input <usb_vbus> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1306 - Output <ata_dior> is never assigned.
WARNING:Xst:2565 - Inout <usb_d(8)> is never assigned.
WARNING:Xst:2565 - Inout <usb_d(11)> is never assigned.
WARNING:Xst:1306 - Output <ata_diow> is never assigned.
WARNING:Xst:2565 - Inout <usb_d(9)> is never assigned.
WARNING:Xst:1306 - Output <spw_txsn> is never assigned.
WARNING:Xst:2565 - Inout <usb_d(12)> is never assigned.
WARNING:Xst:647 - Input <ata_iordy> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1306 - Output <spw_txsp> is never assigned.
WARNING:Xst:2565 - Inout <ata_data(0)> is never assigned.
WARNING:Xst:2565 - Inout <usb_d(13)> is never assigned.
WARNING:Xst:647 - Input <spw_clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1306 - Output <etxd> is never assigned.
WARNING:Xst:2565 - Inout <ata_data(1)> is never assigned.
WARNING:Xst:2565 - Inout <usb_d(14)> is never assigned.
WARNING:Xst:2565 - Inout <ata_data(2)> is never assigned.
WARNING:Xst:2565 - Inout <usb_d(15)> is never assigned.
WARNING:Xst:2565 - Inout <ata_data(3)> is never assigned.
WARNING:Xst:647 - Input <usb_linestate> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <erx_dv> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2565 - Inout <ata_data(4)> is never assigned.
WARNING:Xst:647 - Input <erx_er> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2565 - Inout <ata_data(5)> is never assigned.
WARNING:Xst:2565 - Inout <ata_data(6)> is never assigned.
WARNING:Xst:647 - Input <usb_clkout> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2565 - Inout <ata_data(7)> is never assigned.
WARNING:Xst:1306 - Output <ata_dmack> is never assigned.
WARNING:Xst:2565 - Inout <ata_data(8)> is never assigned.
WARNING:Xst:1306 - Output <usb_opmode> is never assigned.
WARNING:Xst:1306 - Output <usb_reset> is never assigned.
WARNING:Xst:647 - Input <erx_clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ctsn2> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2565 - Inout <ata_data(9)> is never assigned.
WARNING:Xst:2565 - Inout <emdio> is never assigned.
WARNING:Xst:2565 - Inout <ata_data(10)> is never assigned.
WARNING:Xst:2565 - Inout <ata_data(11)> is never assigned.
WARNING:Xst:647 - Input <spw_rxdn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1306 - Output <ata_csel> is never assigned.
WARNING:Xst:647 - Input <erx_col> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2565 - Inout <ata_data(12)> is never assigned.
WARNING:Xst:647 - Input <spw_rxdp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2565 - Inout <ata_data(13)> is never assigned.
WARNING:Xst:1306 - Output <ata_cs0> is never assigned.
WARNING:Xst:1306 - Output <ata_cs1> is never assigned.
WARNING:Xst:1306 - Output <usb_xcvrsel> is never assigned.
WARNING:Xst:2565 - Inout <ata_data(14)> is never assigned.
WARNING:Xst:1306 - Output <usb_suspend> is never assigned.
WARNING:Xst:2565 - Inout <ata_data(15)> is never assigned.
WARNING:Xst:1306 - Output <ata_rstn> is never assigned.
WARNING:Xst:647 - Input <erx_crs> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <usb_rxactive> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1306 - Output <etx_en> is never assigned.
WARNING:Xst:2565 - Inout <usb_validh> is never assigned.
WARNING:Xst:1306 - Output <etx_er> is never assigned.
WARNING:Xst:1306 - Output <emdc> is never assigned.
WARNING:Xst:1306 - Output <spw_txdn> is never assigned.
WARNING:Xst:647 - Input <etx_clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1306 - Output <spw_txdp> is never assigned.
WARNING:Xst:647 - Input <ata_dmarq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <spw_rxsn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1306 - Output <usb_txvalid> is never assigned.
WARNING:Xst:647 - Input <spw_rxsp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1306 - Output <usb_termsel> is never assigned.
WARNING:Xst:647 - Input <usb_rxerror> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2565 - Inout <usb_d(0)> is never assigned.
WARNING:Xst:647 - Input <erxd> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2565 - Inout <usb_d(1)> is never assigned.
WARNING:Xst:647 - Input <usb_rxvalid> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2565 - Inout <usb_d(2)> is never assigned.
WARNING:Xst:1306 - Output <ata_da> is never assigned.
WARNING:Xst:2565 - Inout <usb_d(3)> is never assigned.
WARNING:Xst:653 - Signal <wpo.wprothit> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:1780 - Signal <wdogl> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <vcc<4:1>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbo.xcvrselect> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbo.txvalidh> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbo.txvalid> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbo.txbitstuffenableh> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbo.txbitstuffenable> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbo.tx_se0> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbo.tx_enable_n> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbo.tx_dat> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbo.termselect> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbo.suspendm> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbo.stp> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbo.reset> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbo.opmode> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbo.oen> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbo.idpullup> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbo.fslsserialmode> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbo.drvvbus> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbo.dppulldown> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbo.dmpulldown> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbo.dischrgvbus> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbo.dataout> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbo.databus16_8> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbo.chrgvbus> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbi.vbusvalid> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbi.txready> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbi.rxvalidh> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbi.rxvalid> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbi.rxerror> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbi.rxactive> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbi.nxt> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbi.linestate> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbi.hostdisconnect> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbi.dir> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <usbi.datain> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <uclk> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <u2o.txen> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <u2o.txd> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <u2o.scaler> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <u2o.rxen> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <u2o.rtsn> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <u2o.flow> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <u2i.rxd> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <u2i.extclk> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <u2i.ctsn> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <u1o.txen> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <u1o.scaler> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <u1o.rxen> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <u1o.flow> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <tms> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:646 - Signal <tdo> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <tdi> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:1780 - Signal <tckn> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <tck> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:1780 - Signal <stati.cerror> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwo(2).tickout> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwo(2).s> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwo(2).linkdis> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwo(2).d> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwo(1).tickout> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwo(1).s> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwo(1).linkdis> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwo(1).d> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwo(0).tickout> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwo(0).s> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwo(0).linkdis> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwo(0).d> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwi(2).timerrstval> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwi(2).tickin> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwi(2).s> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwi(2).rmapen> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwi(2).dcrstval> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwi(2).d> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwi(2).clkdiv10> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwi(1).timerrstval> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwi(1).tickin> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwi(1).s> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwi(1).rmapen> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwi(1).dcrstval> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwi(1).d> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwi(1).clkdiv10> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwi(0).timerrstval> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwi(0).tickin> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwi(0).s> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwi(0).rmapen> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwi(0).dcrstval> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwi(0).d> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spwi(0).clkdiv10> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <spw_clkl> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo3.vbdrive> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo3.sdwen> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo3.sdcsn> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo3.sdcke> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo3.sdck> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo3.rasn> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo3.qdrive> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo3.odt> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo3.moben> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo3.dqm> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo3.data> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo3.conf> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo3.ce> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo3.cb> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo3.casn> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo3.cal_rst> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo3.cal_pll> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo3.cal_inc> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo3.cal_en> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo3.bdrive> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo3.ba> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo3.address> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo2.vbdrive> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo2.sdwen> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo2.sdcsn> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo2.sdcke> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo2.sdck> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo2.rasn> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo2.qdrive> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo2.odt> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo2.moben> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo2.dqm> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo2.data> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo2.conf> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo2.ce> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo2.cb> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo2.casn> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo2.cal_rst> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo2.cal_pll> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo2.cal_inc> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo2.cal_en> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo2.bdrive> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo2.ba> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdo2.address> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <sdo.sdcke> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <sdo.dqm<7:4>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdi.wprot> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdi.data> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sdi.cb> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <moui.ps2_data_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <moui.ps2_clk_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <memo.vcdrive> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <memo.vbdrive> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <memo.svcdrive> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <memo.svbdrive> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <memo.sddata> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <memo.scb> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <memo.sa> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <memo.romsn<7:2>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <memo.romn> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <memo.ramsn<7:5>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <memo.ramoen<7:5>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <memo.ramn> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <memo.mben> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <memo.ce> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <memo.cb> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <memo.address<31:28>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <memi.sd> is used but never assigned. This sourceless signal will be automatically connected to value 0000000000000000000000000000000000000000000000000000000000000000.
WARNING:Xst:653 - Signal <memi.scb> is used but never assigned. This sourceless signal will be automatically connected to value 0000000000000000.
WARNING:Xst:653 - Signal <memi.edac> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <memi.cb> is used but never assigned. This sourceless signal will be automatically connected to value 0000000000000000.
WARNING:Xst:646 - Signal <kbdi.ps2_data_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <kbdi.ps2_clk_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ideo.rstn> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ideo.oen> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ideo.dmack> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ideo.diow> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ideo.dior> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ideo.ddo> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ideo.da> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ideo.cs1> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ideo.cs0> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <idei.iordy> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <idei.intrq> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <idei.dmarq> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <idei.ddi> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <gpto.wdogn> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <gpto.wdog> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <gpto.timer1> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <gpto.tick> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <gpioo.val> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <gpioo.sig_out> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <gpioo.oen<31:18>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <gpioo.dout<31:18>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <gpioi.sig_in> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <gpioi.sig_en> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <gpioi.din<31:18>> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000.
WARNING:Xst:646 - Signal <gnd<4:1>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <etho2.txd> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <etho2.tx_er> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <etho2.tx_en> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <etho2.reset> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <etho2.mdio_oe> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <etho2.mdio_o> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <etho2.mdc> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <etho1.txd> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <etho1.tx_er> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <etho1.tx_en> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <etho1.reset> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <etho1.mdio_oe> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <etho1.mdio_o> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <etho1.mdc> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <etho.txd> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <etho.tx_er> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <etho.tx_en> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <etho.reset> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <etho.mdio_oe> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <etho.mdio_o> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <etho.mdc> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi2.tx_clk> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi2.rxd> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi2.rx_er> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi2.rx_dv> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi2.rx_crs> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi2.rx_col> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi2.rx_clk> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi2.rmii_clk> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi2.phyrstaddr> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi2.mdio_i> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi2.gtx_clk> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi2.edcladdr> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi1.tx_clk> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi1.rxd> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi1.rx_er> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi1.rx_dv> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi1.rx_crs> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi1.rx_col> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi1.rx_clk> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi1.rmii_clk> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi1.phyrstaddr> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi1.mdio_i> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi1.gtx_clk> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi1.edcladdr> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi.tx_clk> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi.rxd> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi.rx_er> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi.rx_dv> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi.rx_crs> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi.rx_col> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi.rx_clk> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi.rmii_clk> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi.phyrstaddr> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi.mdio_i> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi.gtx_clk> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ethi.edcladdr> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ethclk> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <duo.txen> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <duo.scaler> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <duo.rxen> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <duo.rtsn> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <duo.flow> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <dui.extclk> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <dui.ctsn> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:646 - Signal <dsuo.pwd> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <dac_clk> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <clk_sel> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1580 - Signal <clk50> with a "KEEP" property is assigned but never used. Related logic will not be removed.
WARNING:Xst:646 - Signal <cgo.pcilock> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <cgi.clksel> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:1780 - Signal <can_ltx> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <can_lrx> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <apbo(15).prdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <apbo(15).pirq> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <apbo(15).pindex> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1781 - Signal <apbo(15).pconfig> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <apbo(14).prdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <apbo(14).pirq> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <apbo(14).pindex> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1781 - Signal <apbo(14).pconfig> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <apbo(13).prdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <apbo(13).pirq> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <apbo(13).pindex> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1781 - Signal <apbo(13).pconfig> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <apbo(12).prdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <apbo(12).pirq> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <apbo(12).pindex> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1781 - Signal <apbo(12).pconfig> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <apbo(11).prdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <apbo(11).pirq> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <apbo(11).pindex> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1781 - Signal <apbo(11).pconfig> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <apbo(10).prdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <apbo(10).pirq> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <apbo(10).pindex> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1781 - Signal <apbo(10).pconfig> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <ahbso(9).hsplit> is used but never assigned. This sourceless signal will be automatically connected to value 0000000000000000.
WARNING:Xst:653 - Signal <ahbso(9).hresp> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:653 - Signal <ahbso(9).hready> is used but never assigned. This sourceless signal will be automatically connected to value 1.
WARNING:Xst:653 - Signal <ahbso(9).hrdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbso(9).hirq> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbso(9).hindex> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1781 - Signal <ahbso(9).hconfig> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <ahbso(9).hcache> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbso(8).hsplit> is used but never assigned. This sourceless signal will be automatically connected to value 0000000000000000.
WARNING:Xst:653 - Signal <ahbso(8).hresp> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:653 - Signal <ahbso(8).hready> is used but never assigned. This sourceless signal will be automatically connected to value 1.
WARNING:Xst:653 - Signal <ahbso(8).hrdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbso(8).hirq> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbso(8).hindex> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1781 - Signal <ahbso(8).hconfig> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <ahbso(8).hcache> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbso(7).hsplit> is used but never assigned. This sourceless signal will be automatically connected to value 0000000000000000.
WARNING:Xst:653 - Signal <ahbso(7).hresp> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:653 - Signal <ahbso(7).hready> is used but never assigned. This sourceless signal will be automatically connected to value 1.
WARNING:Xst:653 - Signal <ahbso(7).hrdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbso(7).hirq> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbso(7).hindex> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1781 - Signal <ahbso(7).hconfig> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <ahbso(7).hcache> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbso(6).hsplit> is used but never assigned. This sourceless signal will be automatically connected to value 0000000000000000.
WARNING:Xst:653 - Signal <ahbso(6).hresp> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:653 - Signal <ahbso(6).hready> is used but never assigned. This sourceless signal will be automatically connected to value 1.
WARNING:Xst:653 - Signal <ahbso(6).hrdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbso(6).hirq> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbso(6).hindex> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1781 - Signal <ahbso(6).hconfig> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <ahbso(6).hcache> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbso(5).hsplit> is used but never assigned. This sourceless signal will be automatically connected to value 0000000000000000.
WARNING:Xst:653 - Signal <ahbso(5).hresp> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:653 - Signal <ahbso(5).hready> is used but never assigned. This sourceless signal will be automatically connected to value 1.
WARNING:Xst:653 - Signal <ahbso(5).hrdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbso(5).hirq> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbso(5).hindex> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1781 - Signal <ahbso(5).hconfig> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <ahbso(5).hcache> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbso(4).hsplit> is used but never assigned. This sourceless signal will be automatically connected to value 0000000000000000.
WARNING:Xst:653 - Signal <ahbso(4).hresp> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:653 - Signal <ahbso(4).hready> is used but never assigned. This sourceless signal will be automatically connected to value 1.
WARNING:Xst:653 - Signal <ahbso(4).hrdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbso(4).hirq> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbso(4).hindex> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1781 - Signal <ahbso(4).hconfig> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <ahbso(4).hcache> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbso(3).hsplit> is used but never assigned. This sourceless signal will be automatically connected to value 0000000000000000.
WARNING:Xst:653 - Signal <ahbso(3).hresp> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:653 - Signal <ahbso(3).hready> is used but never assigned. This sourceless signal will be automatically connected to value 1.
WARNING:Xst:653 - Signal <ahbso(3).hrdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbso(3).hirq> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbso(3).hindex> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1781 - Signal <ahbso(3).hconfig> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <ahbso(3).hcache> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbso(15).hsplit> is used but never assigned. This sourceless signal will be automatically connected to value 0000000000000000.
WARNING:Xst:653 - Signal <ahbso(15).hresp> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:653 - Signal <ahbso(15).hready> is used but never assigned. This sourceless signal will be automatically connected to value 1.
WARNING:Xst:653 - Signal <ahbso(15).hrdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbso(15).hirq> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbso(15).hindex> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1781 - Signal <ahbso(15).hconfig> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <ahbso(15).hcache> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbso(14).hsplit> is used but never assigned. This sourceless signal will be automatically connected to value 0000000000000000.
WARNING:Xst:653 - Signal <ahbso(14).hresp> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:653 - Signal <ahbso(14).hready> is used but never assigned. This sourceless signal will be automatically connected to value 1.
WARNING:Xst:653 - Signal <ahbso(14).hrdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbso(14).hirq> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbso(14).hindex> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1781 - Signal <ahbso(14).hconfig> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <ahbso(14).hcache> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbso(13).hsplit> is used but never assigned. This sourceless signal will be automatically connected to value 0000000000000000.
WARNING:Xst:653 - Signal <ahbso(13).hresp> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:653 - Signal <ahbso(13).hready> is used but never assigned. This sourceless signal will be automatically connected to value 1.
WARNING:Xst:653 - Signal <ahbso(13).hrdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbso(13).hirq> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbso(13).hindex> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1781 - Signal <ahbso(13).hconfig> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <ahbso(13).hcache> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbso(12).hsplit> is used but never assigned. This sourceless signal will be automatically connected to value 0000000000000000.
WARNING:Xst:653 - Signal <ahbso(12).hresp> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:653 - Signal <ahbso(12).hready> is used but never assigned. This sourceless signal will be automatically connected to value 1.
WARNING:Xst:653 - Signal <ahbso(12).hrdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbso(12).hirq> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbso(12).hindex> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1781 - Signal <ahbso(12).hconfig> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <ahbso(12).hcache> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbso(11).hsplit> is used but never assigned. This sourceless signal will be automatically connected to value 0000000000000000.
WARNING:Xst:653 - Signal <ahbso(11).hresp> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:653 - Signal <ahbso(11).hready> is used but never assigned. This sourceless signal will be automatically connected to value 1.
WARNING:Xst:653 - Signal <ahbso(11).hrdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbso(11).hirq> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbso(11).hindex> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1781 - Signal <ahbso(11).hconfig> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <ahbso(11).hcache> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbso(10).hsplit> is used but never assigned. This sourceless signal will be automatically connected to value 0000000000000000.
WARNING:Xst:653 - Signal <ahbso(10).hresp> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:653 - Signal <ahbso(10).hready> is used but never assigned. This sourceless signal will be automatically connected to value 1.
WARNING:Xst:653 - Signal <ahbso(10).hrdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbso(10).hirq> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbso(10).hindex> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1781 - Signal <ahbso(10).hconfig> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <ahbso(10).hcache> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(9).hwrite> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(9).hwdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(9).htrans> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:653 - Signal <ahbmo(9).hsize> is used but never assigned. This sourceless signal will be automatically connected to value 000.
WARNING:Xst:653 - Signal <ahbmo(9).hprot> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:653 - Signal <ahbmo(9).hlock> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(9).hirq> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(9).hindex> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1781 - Signal <ahbmo(9).hconfig> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <ahbmo(9).hbusreq> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(9).hburst> is used but never assigned. This sourceless signal will be automatically connected to value 000.
WARNING:Xst:653 - Signal <ahbmo(9).haddr> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(8).hwrite> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(8).hwdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(8).htrans> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:653 - Signal <ahbmo(8).hsize> is used but never assigned. This sourceless signal will be automatically connected to value 000.
WARNING:Xst:653 - Signal <ahbmo(8).hprot> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:653 - Signal <ahbmo(8).hlock> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(8).hirq> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(8).hindex> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1781 - Signal <ahbmo(8).hconfig> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <ahbmo(8).hbusreq> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(8).hburst> is used but never assigned. This sourceless signal will be automatically connected to value 000.
WARNING:Xst:653 - Signal <ahbmo(8).haddr> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(7).hwrite> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(7).hwdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(7).htrans> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:653 - Signal <ahbmo(7).hsize> is used but never assigned. This sourceless signal will be automatically connected to value 000.
WARNING:Xst:653 - Signal <ahbmo(7).hprot> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:653 - Signal <ahbmo(7).hlock> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(7).hirq> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(7).hindex> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1781 - Signal <ahbmo(7).hconfig> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <ahbmo(7).hbusreq> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(7).hburst> is used but never assigned. This sourceless signal will be automatically connected to value 000.
WARNING:Xst:653 - Signal <ahbmo(7).haddr> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(6).hwrite> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(6).hwdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(6).htrans> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:653 - Signal <ahbmo(6).hsize> is used but never assigned. This sourceless signal will be automatically connected to value 000.
WARNING:Xst:653 - Signal <ahbmo(6).hprot> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:653 - Signal <ahbmo(6).hlock> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(6).hirq> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(6).hindex> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1781 - Signal <ahbmo(6).hconfig> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <ahbmo(6).hbusreq> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(6).hburst> is used but never assigned. This sourceless signal will be automatically connected to value 000.
WARNING:Xst:653 - Signal <ahbmo(6).haddr> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(5).hwrite> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(5).hwdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(5).htrans> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:653 - Signal <ahbmo(5).hsize> is used but never assigned. This sourceless signal will be automatically connected to value 000.
WARNING:Xst:653 - Signal <ahbmo(5).hprot> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:653 - Signal <ahbmo(5).hlock> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(5).hirq> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(5).hindex> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1781 - Signal <ahbmo(5).hconfig> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <ahbmo(5).hbusreq> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(5).hburst> is used but never assigned. This sourceless signal will be automatically connected to value 000.
WARNING:Xst:653 - Signal <ahbmo(5).haddr> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(4).hwrite> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(4).hwdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(4).htrans> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:653 - Signal <ahbmo(4).hsize> is used but never assigned. This sourceless signal will be automatically connected to value 000.
WARNING:Xst:653 - Signal <ahbmo(4).hprot> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:653 - Signal <ahbmo(4).hlock> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(4).hirq> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(4).hindex> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1781 - Signal <ahbmo(4).hconfig> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <ahbmo(4).hbusreq> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(4).hburst> is used but never assigned. This sourceless signal will be automatically connected to value 000.
WARNING:Xst:653 - Signal <ahbmo(4).haddr> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(3).hwrite> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(3).hwdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(3).htrans> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:653 - Signal <ahbmo(3).hsize> is used but never assigned. This sourceless signal will be automatically connected to value 000.
WARNING:Xst:653 - Signal <ahbmo(3).hprot> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:653 - Signal <ahbmo(3).hlock> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(3).hirq> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(3).hindex> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1781 - Signal <ahbmo(3).hconfig> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <ahbmo(3).hbusreq> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(3).hburst> is used but never assigned. This sourceless signal will be automatically connected to value 000.
WARNING:Xst:653 - Signal <ahbmo(3).haddr> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(15).hwrite> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(15).hwdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(15).htrans> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:653 - Signal <ahbmo(15).hsize> is used but never assigned. This sourceless signal will be automatically connected to value 000.
WARNING:Xst:653 - Signal <ahbmo(15).hprot> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:653 - Signal <ahbmo(15).hlock> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(15).hirq> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(15).hindex> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1781 - Signal <ahbmo(15).hconfig> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <ahbmo(15).hbusreq> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(15).hburst> is used but never assigned. This sourceless signal will be automatically connected to value 000.
WARNING:Xst:653 - Signal <ahbmo(15).haddr> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(14).hwrite> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(14).hwdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(14).htrans> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:653 - Signal <ahbmo(14).hsize> is used but never assigned. This sourceless signal will be automatically connected to value 000.
WARNING:Xst:653 - Signal <ahbmo(14).hprot> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:653 - Signal <ahbmo(14).hlock> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(14).hirq> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(14).hindex> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1781 - Signal <ahbmo(14).hconfig> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <ahbmo(14).hbusreq> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(14).hburst> is used but never assigned. This sourceless signal will be automatically connected to value 000.
WARNING:Xst:653 - Signal <ahbmo(14).haddr> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(13).hwrite> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(13).hwdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(13).htrans> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:653 - Signal <ahbmo(13).hsize> is used but never assigned. This sourceless signal will be automatically connected to value 000.
WARNING:Xst:653 - Signal <ahbmo(13).hprot> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:653 - Signal <ahbmo(13).hlock> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(13).hirq> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(13).hindex> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1781 - Signal <ahbmo(13).hconfig> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <ahbmo(13).hbusreq> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(13).hburst> is used but never assigned. This sourceless signal will be automatically connected to value 000.
WARNING:Xst:653 - Signal <ahbmo(13).haddr> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(12).hwrite> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(12).hwdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(12).htrans> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:653 - Signal <ahbmo(12).hsize> is used but never assigned. This sourceless signal will be automatically connected to value 000.
WARNING:Xst:653 - Signal <ahbmo(12).hprot> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:653 - Signal <ahbmo(12).hlock> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(12).hirq> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(12).hindex> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1781 - Signal <ahbmo(12).hconfig> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <ahbmo(12).hbusreq> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(12).hburst> is used but never assigned. This sourceless signal will be automatically connected to value 000.
WARNING:Xst:653 - Signal <ahbmo(12).haddr> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(11).hwrite> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(11).hwdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(11).htrans> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:653 - Signal <ahbmo(11).hsize> is used but never assigned. This sourceless signal will be automatically connected to value 000.
WARNING:Xst:653 - Signal <ahbmo(11).hprot> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:653 - Signal <ahbmo(11).hlock> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(11).hirq> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(11).hindex> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1781 - Signal <ahbmo(11).hconfig> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <ahbmo(11).hbusreq> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(11).hburst> is used but never assigned. This sourceless signal will be automatically connected to value 000.
WARNING:Xst:653 - Signal <ahbmo(11).haddr> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(10).hwrite> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(10).hwdata> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(10).htrans> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:653 - Signal <ahbmo(10).hsize> is used but never assigned. This sourceless signal will be automatically connected to value 000.
WARNING:Xst:653 - Signal <ahbmo(10).hprot> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:653 - Signal <ahbmo(10).hlock> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(10).hirq> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ahbmo(10).hindex> is used but never assigned. This sourceless signal will be automatically connected to value 0000.
WARNING:Xst:1781 - Signal <ahbmo(10).hconfig> is used but never assigned. Tied to default value.
WARNING:Xst:653 - Signal <ahbmo(10).hbusreq> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <ahbmo(10).hburst> is used but never assigned. This sourceless signal will be automatically connected to value 000.
WARNING:Xst:653 - Signal <ahbmo(10).haddr> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
Unit <leon3mp> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
WARNING:Xst:524 - All outputs of the instance <CAL_CPI> of the block <cal_cpi> are unconnected in block <rf_stage>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <U9> of the block <dmem_ctl_reg> are unconnected in block <pipelinedregs>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 2
 32x32-bit dual-port RAM                               : 2
# ROMs                                                 : 2
 16x3-bit ROM                                          : 2
# Multipliers                                          : 1
 33x33-bit multiplier                                  : 1
# Adders/Subtractors                                   : 50
 12-bit subtractor                                     : 1
 15-bit subtractor                                     : 1
 18-bit addsub                                         : 1
 2-bit adder                                           : 5
 3-bit adder                                           : 10
 3-bit subtractor                                      : 4
 30-bit adder                                          : 2
 32-bit adder                                          : 5
 32-bit adder carry out                                : 1
 32-bit subtractor                                     : 1
 33-bit adder                                          : 10
 4-bit subtractor                                      : 3
 5-bit adder                                           : 1
 6-bit subtractor                                      : 1
 7-bit adder                                           : 1
 8-bit adder                                           : 2
 9-bit subtractor                                      : 1
# Counters                                             : 7
 2-bit up counter                                      : 3
 6-bit up counter                                      : 2
 7-bit up counter                                      : 1
 8-bit up counter                                      : 1
# Registers                                            : 622
 1-bit register                                        : 427
 11-bit register                                       : 2
 12-bit register                                       : 2
 14-bit register                                       : 1
 15-bit register                                       : 8
 16-bit register                                       : 1
 18-bit register                                       : 6
 19-bit register                                       : 1
 2-bit register                                        : 36
 20-bit register                                       : 1
 22-bit register                                       : 1
 25-bit register                                       : 1
 28-bit register                                       : 1
 3-bit register                                        : 25
 30-bit register                                       : 2
 32-bit register                                       : 34
 33-bit register                                       : 2
 35-bit register                                       : 1
 4-bit register                                        : 20
 5-bit register                                        : 19
 6-bit register                                        : 6
 64-bit register                                       : 3
 65-bit register                                       : 1
 66-bit register                                       : 1
 7-bit register                                        : 1
 8-bit register                                        : 19
# Latches                                              : 1
 1-bit latch                                           : 1
# Comparators                                          : 143
 12-bit comparator equal                               : 108
 14-bit comparator equal                               : 1
 14-bit comparator greater                             : 1
 14-bit comparator lessequal                           : 1
 14-bit comparator not equal                           : 1
 2-bit comparator greatequal                           : 3
 2-bit comparator not equal                            : 2
 20-bit comparator equal                               : 4
 22-bit comparator equal                               : 1
 28-bit comparator equal                               : 1
 3-bit comparator not equal                            : 1
 32-bit comparator equal                               : 1
 32-bit comparator less                                : 1
 32-bit comparator not equal                           : 1
 33-bit comparator equal                               : 2
 5-bit comparator equal                                : 12
 7-bit comparator equal                                : 1
 8-bit comparator equal                                : 1
# Multiplexers                                         : 223
 1-bit 128-to-1 multiplexer                            : 1
 1-bit 16-to-1 multiplexer                             : 2
 1-bit 4-to-1 multiplexer                              : 177
 1-bit 8-to-1 multiplexer                              : 5
 10-bit 4-to-1 multiplexer                             : 1
 13-bit 4-to-1 multiplexer                             : 1
 2-bit 4-to-1 multiplexer                              : 1
 3-bit 4-to-1 multiplexer                              : 4
 32-bit 16-to-1 multiplexer                            : 2
 32-bit 3-to-1 multiplexer                             : 1
 32-bit 4-to-1 multiplexer                             : 15
 32-bit 8-to-1 multiplexer                             : 10
 4-bit 4-to-1 multiplexer                              : 1
 8-bit 4-to-1 multiplexer                              : 2
# Priority Encoders                                    : 2
 32-bit 1-of-6 priority encoder                        : 2
# Xors                                                 : 12
 1-bit xor2                                            : 11
 32-bit xor2                                           : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

WARNING:Xst:2404 -  FFs/Latches <r.bstate<7:6>> (without init value) have a constant value of 0 in block <mctrl>.

Synthesizing (advanced) Unit <generic_regfile_3p>.
INFO:Xst - The RAM <Mram_memarr_ren> will be implemented as a BLOCK RAM, absorbing the following register(s): <ra2>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 32-word x 32-bit                    |          |
    |     mode           | write-first                         |          |
    |     clkA           | connected to signal <wclk>          | rise     |
    |     weA            | connected to signal <wr>            | high     |
    |     addrA          | connected to signal <wa>            |          |
    |     diA            | connected to signal <din>           |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 32-word x 32-bit                    |          |
    |     mode           | write-first                         |          |
    |     clkB           | connected to signal <wclk>          | rise     |
    |     enB            | connected to signal <re2>           | high     |
    |     addrB          | connected to signal <raddr2>        |          |
    |     doB            | connected to internal node          |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
INFO:Xst - The RAM <Mram_memarr> will be implemented as a BLOCK RAM, absorbing the following register(s): <ra1>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 32-word x 32-bit                    |          |
    |     mode           | write-first                         |          |
    |     clkA           | connected to signal <wclk>          | rise     |
    |     weA            | connected to signal <wr>            | high     |
    |     addrA          | connected to signal <wa>            |          |
    |     diA            | connected to signal <din>           |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 32-word x 32-bit                    |          |
    |     mode           | write-first                         |          |
    |     clkB           | connected to signal <wclk>          | rise     |
    |     enB            | connected to signal <re1>           | high     |
    |     addrB          | connected to signal <raddr1>        |          |
    |     doB            | connected to internal node          |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
Unit <generic_regfile_3p> synthesized (advanced).

Synthesizing (advanced) Unit <mul32>.
        Found pipelined multiplier on signal <prod_mult0001>:
                - 1 pipeline level(s) found in a register connected to the multiplier macro output.
                Pushing register(s) into the multiplier macro.
INFO:Xst:2385 - HDL ADVISOR - You can improve the performance of the multiplier Mmult_prod_mult0001 by adding 2 register level(s).
Unit <mul32> synthesized (advanced).
WARNING:Xst:2677 - Node <r.haddr_11> of sequential type is unconnected in block <ahbctrl>.
WARNING:Xst:2677 - Node <r.haddr_12> of sequential type is unconnected in block <ahbctrl>.
WARNING:Xst:2677 - Node <r.haddr_13> of sequential type is unconnected in block <ahbctrl>.
WARNING:Xst:2677 - Node <r.haddr_14> of sequential type is unconnected in block <ahbctrl>.
WARNING:Xst:2677 - Node <r.haddr_15> of sequential type is unconnected in block <ahbctrl>.
WARNING:Xst:2677 - Node <r.state_2> of sequential type is unconnected in block <apbctrl>.
WARNING:Xst:2677 - Node <r.state_5> of sequential type is unconnected in block <div32>.
WARNING:Xst:2677 - Node <r.slv.haddr_0> of sequential type is unconnected in block <dsu3x>.
WARNING:Xst:2677 - Node <r.slv.haddr_1> of sequential type is unconnected in block <dsu3x>.
WARNING:Xst:2677 - Node <r.readdata_24> of sequential type is unconnected in block <mctrl>.
WARNING:Xst:2677 - Node <r.readdata_25> of sequential type is unconnected in block <mctrl>.
WARNING:Xst:2677 - Node <r.readdata_26> of sequential type is unconnected in block <mctrl>.
WARNING:Xst:2677 - Node <r.readdata_27> of sequential type is unconnected in block <mctrl>.
WARNING:Xst:2677 - Node <r.readdata_28> of sequential type is unconnected in block <mctrl>.
WARNING:Xst:2677 - Node <r.readdata_29> of sequential type is unconnected in block <mctrl>.
WARNING:Xst:2677 - Node <r.readdata_30> of sequential type is unconnected in block <mctrl>.
WARNING:Xst:2677 - Node <r.readdata_31> of sequential type is unconnected in block <mctrl>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 2
 32x32-bit dual-port block RAM                         : 2
# ROMs                                                 : 2
 16x3-bit ROM                                          : 2
# Multipliers                                          : 1
 33x33-bit registered multiplier                       : 1
# Adders/Subtractors                                   : 50
 12-bit subtractor                                     : 1
 15-bit subtractor                                     : 1
 18-bit addsub                                         : 1
 2-bit adder                                           : 5
 3-bit adder                                           : 10
 3-bit subtractor                                      : 4
 30-bit adder                                          : 2
 32-bit adder                                          : 5
 32-bit adder carry out                                : 1
 32-bit subtractor                                     : 1
 33-bit adder                                          : 10
 4-bit subtractor                                      : 3
 5-bit adder                                           : 1
 6-bit subtractor                                      : 1
 7-bit adder                                           : 1
 8-bit adder                                           : 2
 9-bit subtractor                                      : 1
# Counters                                             : 7
 2-bit up counter                                      : 3
 6-bit up counter                                      : 2
 7-bit up counter                                      : 1
 8-bit up counter                                      : 1
# Registers                                            : 2785
 Flip-Flops                                            : 2785
# Latches                                              : 1
 1-bit latch                                           : 1
# Comparators                                          : 143
 12-bit comparator equal                               : 108
 14-bit comparator equal                               : 1
 14-bit comparator greater                             : 1
 14-bit comparator lessequal                           : 1
 14-bit comparator not equal                           : 1
 2-bit comparator greatequal                           : 3
 2-bit comparator not equal                            : 2
 20-bit comparator equal                               : 4
 22-bit comparator equal                               : 1
 28-bit comparator equal                               : 1
 3-bit comparator not equal                            : 1
 32-bit comparator equal                               : 1
 32-bit comparator less                                : 1
 32-bit comparator not equal                           : 1
 33-bit comparator equal                               : 2
 5-bit comparator equal                                : 12
 7-bit comparator equal                                : 1
 8-bit comparator equal                                : 1
# Multiplexers                                         : 219
 1-bit 128-to-1 multiplexer                            : 1
 1-bit 16-to-1 multiplexer                             : 2
 1-bit 4-to-1 multiplexer                              : 173
 1-bit 8-to-1 multiplexer                              : 5
 10-bit 4-to-1 multiplexer                             : 1
 13-bit 4-to-1 multiplexer                             : 1
 2-bit 4-to-1 multiplexer                              : 1
 3-bit 4-to-1 multiplexer                              : 4
 32-bit 16-to-1 multiplexer                            : 2
 32-bit 3-to-1 multiplexer                             : 1
 32-bit 4-to-1 multiplexer                             : 15
 32-bit 8-to-1 multiplexer                             : 10
 4-bit 4-to-1 multiplexer                              : 1
 8-bit 4-to-1 multiplexer                              : 2
# Priority Encoders                                    : 2
 32-bit 1-of-6 priority encoder                        : 2
# Xors                                                 : 12
 1-bit xor2                                            : 11
 32-bit xor2                                           : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch <r.extclk> (without init value) has a constant value of 0 in block <apbuart>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <CurrState_4> (without init value) has a constant value of 0 in block <ctl_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <riack> (without init value) has a constant value of 0 in block <ctl_FSM>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <r.lock> (without init value) has a constant value of 0 in block <icache>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.lrr> (without init value) has a constant value of 0 in block <icache>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <r.lrr> (without init value) has a constant value of 0 in block <dcache>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.ilramen> (without init value) has a constant value of 0 in block <dcache>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.lock> (without init value) has a constant value of 0 in block <dcache>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.dsuset_0> (without init value) has a constant value of 0 in block <dcache>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <r.bdelay> (without init value) has a constant value of 0 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cfg.tcsr_3> (without init value) has a constant value of 0 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cfg.tcsr_2> (without init value) has a constant value of 0 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cfg.tcsr_1> (without init value) has a constant value of 0 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cfg.tcsr_0> (without init value) has a constant value of 0 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cfg.ds_3> (without init value) has a constant value of 0 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cfg.ds_2> (without init value) has a constant value of 0 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cfg.ds_1> (without init value) has a constant value of 0 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cfg.ds_0> (without init value) has a constant value of 0 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cfg.mobileen_1> (without init value) has a constant value of 0 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cfg.mobileen_0> (without init value) has a constant value of 0 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cfg.pmode_2> (without init value) has a constant value of 0 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cfg.pasr_5> (without init value) has a constant value of 0 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cfg.pasr_4> (without init value) has a constant value of 0 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cfg.pasr_3> (without init value) has a constant value of 0 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cfg.pasr_2> (without init value) has a constant value of 0 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cfg.pasr_1> (without init value) has a constant value of 0 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cfg.pasr_0> (without init value) has a constant value of 0 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cfg.txsr_3> (without init value) has a constant value of 1 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cfg.txsr_2> (without init value) has a constant value of 1 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cfg.txsr_1> (without init value) has a constant value of 1 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cfg.txsr_0> (without init value) has a constant value of 1 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <r.sdwritedata_63> (without init value) has a constant value of 0 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdwritedata_62> (without init value) has a constant value of 0 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdwritedata_61> (without init value) has a constant value of 0 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdwritedata_60> (without init value) has a constant value of 0 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdwritedata_59> (without init value) has a constant value of 0 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdwritedata_58> (without init value) has a constant value of 0 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdwritedata_57> (without init value) has a constant value of 0 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdwritedata_56> (without init value) has a constant value of 0 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdwritedata_55> (without init value) has a constant value of 0 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdwritedata_54> (without init value) has a constant value of 0 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdwritedata_53> (without init value) has a constant value of 0 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdwritedata_52> (without init value) has a constant value of 0 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdwritedata_51> (without init value) has a constant value of 0 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdwritedata_50> (without init value) has a constant value of 0 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdwritedata_49> (without init value) has a constant value of 0 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdwritedata_48> (without init value) has a constant value of 0 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdwritedata_47> (without init value) has a constant value of 0 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdwritedata_46> (without init value) has a constant value of 0 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdwritedata_45> (without init value) has a constant value of 0 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdwritedata_44> (without init value) has a constant value of 0 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdwritedata_43> (without init value) has a constant value of 0 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdwritedata_42> (without init value) has a constant value of 0 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdwritedata_41> (without init value) has a constant value of 0 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdwritedata_40> (without init value) has a constant value of 0 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdwritedata_39> (without init value) has a constant value of 0 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdwritedata_38> (without init value) has a constant value of 0 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdwritedata_37> (without init value) has a constant value of 0 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdwritedata_36> (without init value) has a constant value of 0 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdwritedata_35> (without init value) has a constant value of 0 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdwritedata_34> (without init value) has a constant value of 0 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdwritedata_33> (without init value) has a constant value of 0 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdwritedata_32> (without init value) has a constant value of 0 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <op2_reged_32> in Unit <muldiv_ff> is equivalent to the following FF/Latch, which will be removed : <op2_sign_reged> 
INFO:Xst:2261 - The FF/Latch <r.asi_0> in Unit <dcache> is equivalent to the following FF/Latch, which will be removed : <r.asi_2> 
INFO:Xst:2261 - The FF/Latch <r.asi_1> in Unit <dcache> is equivalent to the following FF/Latch, which will be removed : <r.asi_3> 
WARNING:Xst:1710 - FF/Latch <r.hslave_2> (without init value) has a constant value of 0 in block <ahbctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rm.state_0> (without init value) has a constant value of 1 in block <mul32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rm.state_1> (without init value) has a constant value of 0 in block <mul32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rm.start> (without init value) has a constant value of 0 in block <mul32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rm.nready> (without init value) has a constant value of 0 in block <mul32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <r.x_20> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_21> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_22> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_23> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_24> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_25> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_26> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_27> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_28> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_29> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_30> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_31> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.qmsb> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.qzero> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.state_1> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.state_2> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.state_3> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.ovf> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.neg> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.qcorr> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.zcorr> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_0> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_1> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_2> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_3> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_4> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_5> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_6> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_7> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_8> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_9> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_10> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_11> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_12> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_13> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_14> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_15> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_16> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_17> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_18> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_19> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <r.cnt_0> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cnt_1> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cnt_2> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cnt_3> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cnt_4> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.state_4> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <r.x_49> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_50> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_51> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_52> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_53> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_54> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_55> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_56> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_57> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_58> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_59> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_60> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_61> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_62> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_63> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_64> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.state_0> (without init value) has a constant value of 1 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_32> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_33> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_34> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_35> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_36> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_37> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_38> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_39> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_40> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_41> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_42> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_43> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_44> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_45> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_46> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_47> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.x_48> (without init value) has a constant value of 0 in block <div32>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <r.zero> of sequential type is unconnected in block <div32>.
WARNING:Xst:2677 - Node <r.zero2> of sequential type is unconnected in block <div32>.
WARNING:Xst:1710 - FF/Latch <r.su> (without init value) has a constant value of 0 in block <icache>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <r.icenable> (without init value) has a constant value of 0 in block <dcache>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.wb.asi_0> (without init value) has a constant value of 0 in block <dcache>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.wb.asi_2> (without init value) has a constant value of 0 in block <dcache>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.dstate_4> (without init value) has a constant value of 0 in block <dcache>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cctrl.dcs_1> (without init value) has a constant value of 0 in block <dcache>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cctrl.ics_1> (without init value) has a constant value of 0 in block <dcache>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cctrlwr> (without init value) has a constant value of 0 in block <dcache>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.flush> (without init value) has a constant value of 0 in block <dcache>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.asi_0> (without init value) has a constant value of 0 in block <dcache>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.asi_1> (without init value) has a constant value of 1 in block <dcache>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <r.cctrl.dcs_0> in Unit <dcache> is equivalent to the following FF/Latch, which will be removed : <r.cctrl.ics_0> 
WARNING:Xst:1710 - FF/Latch <r.pwd_0> (without init value) has a constant value of 0 in block <dsu3x>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.slv.hrdata_30> (without init value) has a constant value of 0 in block <dsu3x>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.slv.hrdata_31> (without init value) has a constant value of 0 in block <dsu3x>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.en_0> (without init value) has a constant value of 0 in block <dsu3x>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <r.sdstate_16> (without init value) has a constant value of 0 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdstate_17> (without init value) has a constant value of 0 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sdstate_18> (without init value) has a constant value of 0 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.istate_4> (without init value) has a constant value of 0 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cfg.pmode_0> (without init value) has a constant value of 0 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cfg.pmode_1> (without init value) has a constant value of 0 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <r.sref_tmpcom_0> (without init value) has a constant value of 0 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.startsd> (without init value) has a constant value of 0 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <r.sref_tmpcom_1> (without init value) has a constant value of 0 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.sref_tmpcom_2> (without init value) has a constant value of 0 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <r.idlecnt_0> of sequential type is unconnected in block <sdmctrl>.
WARNING:Xst:2677 - Node <r.idlecnt_1> of sequential type is unconnected in block <sdmctrl>.
WARNING:Xst:2677 - Node <r.idlecnt_2> of sequential type is unconnected in block <sdmctrl>.
WARNING:Xst:2677 - Node <r.idlecnt_3> of sequential type is unconnected in block <sdmctrl>.
WARNING:Xst:1710 - FF/Latch <Mmult_prod_mult0001> (without init value) has a constant value of 0 in block <mul32>. This FF/Latch will be trimmed during the optimization process.

Optimizing unit <leon3mp> ...

Optimizing unit <rstgen> ...

Optimizing unit <ahbctrl> ...
WARNING:Xst:2677 - Node <r.htrans_0> of sequential type is unconnected in block <ahbctrl>.

Optimizing unit <apbctrl> ...

Optimizing unit <apbuart> ...

Optimizing unit <irqmp> ...

Optimizing unit <gptimer> ...

Optimizing unit <grgpio> ...

Optimizing unit <r32_reg> ...

Optimizing unit <r32_inst_reg> ...

Optimizing unit <r32_data_reg> ...

Optimizing unit <ctl_FSM> ...

Optimizing unit <pc_gen> ...

Optimizing unit <compare> ...

Optimizing unit <r32_reg_clr_cls> ...

Optimizing unit <alu_muxa> ...

Optimizing unit <alu_muxb> ...

Optimizing unit <r32_reg_cls> ...

Optimizing unit <muldiv_ff> ...

Optimizing unit <alu> ...

Optimizing unit <decoder> ...

Optimizing unit <dmem_ctl_reg_clr> ...

Optimizing unit <alu_func_reg_clr> ...

Optimizing unit <alu_func_reg_clr_cls> ...

Optimizing unit <dmem_ctl_reg_clr_cls> ...

Optimizing unit <icache> ...

Optimizing unit <dcache> ...
WARNING:Xst:1710 - FF/Latch <rs.writebp_0> (without init value) has a constant value of 0 in block <dcache>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cctrl.ifrz> (without init value) has a constant value of 0 in block <dcache>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.wb.asi_1> (without init value) has a constant value of 1 in block <dcache>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.wb.asi_3> (without init value) has a constant value of 1 in block <dcache>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.dstate_2> (without init value) has a constant value of 0 in block <dcache>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cctrl.dcs_0> (without init value) has a constant value of 0 in block <dcache>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cctrl.dsnoop> (without init value) has a constant value of 0 in block <dcache>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cctrl.burst> (without init value) has a constant value of 0 in block <dcache>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.cctrl.dfrz> (without init value) has a constant value of 0 in block <dcache>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rs.snoop> (without init value) has a constant value of 0 in block <dcache>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <rs.readbpx_0> is unconnected in block <dcache>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <rs.addr_4> is unconnected in block <dcache>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <rs.addr_5> is unconnected in block <dcache>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <rs.addr_6> is unconnected in block <dcache>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <rs.addr_7> is unconnected in block <dcache>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <rs.addr_8> is unconnected in block <dcache>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <rs.addr_9> is unconnected in block <dcache>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <rs.addr_10> is unconnected in block <dcache>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <rs.addr_11> is unconnected in block <dcache>.

Optimizing unit <mmu_acache> ...

Optimizing unit <generic_regfile_3p> ...

Optimizing unit <dsu3x> ...

Optimizing unit <ahbmst_1> ...

Optimizing unit <dcom_uart> ...

Optimizing unit <dcom> ...

Optimizing unit <ahbmst_2> ...

Optimizing unit <jtagcom> ...

Optimizing unit <sdmctrl> ...
WARNING:Xst:1710 - FF/Latch <r.dqm_4> (without init value) has a constant value of 1 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.dqm_5> (without init value) has a constant value of 1 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.dqm_6> (without init value) has a constant value of 1 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.dqm_7> (without init value) has a constant value of 1 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <r.cfg.command_0> (without init value) has a constant value of 0 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <r.cfg.command_0> (without init value) has a constant value of 0 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.

Optimizing unit <clkgen_spartan3> ...

Optimizing unit <mctrl> ...
WARNING:Xst:1710 - FF/Latch <r.ramsn_2> (without init value) has a constant value of 1 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.ramsn_3> (without init value) has a constant value of 1 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.ramsn_4> (without init value) has a constant value of 1 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <r.ramsn_2> (without init value) has a constant value of 1 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.ramsn_3> (without init value) has a constant value of 1 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <r.ramsn_4> (without init value) has a constant value of 1 in block <mctrl>. This FF/Latch will be trimmed during the optimization process.

Optimizing unit <rf_stage> ...

Optimizing unit <mips_alu> ...

Optimizing unit <pipelinedregs> ...

Optimizing unit <outpadv_3> ...

Optimizing unit <iopadv> ...

Optimizing unit <cachemem> ...

Optimizing unit <mips_core> ...
WARNING:Xst:1710 - FF/Latch <r.trfc_3> (without init value) has a constant value of 0 in block <sdmctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hmasterlock> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatas_27> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatas_25> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatas_23> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatas_22> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatas_21> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatas_20> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatas_19> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatas_18> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatas_3> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatas_0> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/r.flush> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/r.istate_2> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/r.flush2> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/dcache0/r.wb.lock> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/a0/r.hlocken> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/a0/r.retry> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/a0/r.lock> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <mctrl0/r.hresp_1> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <mctrl0/r.hburst_2> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <mctrl0/r.hburst_1> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/mips/E1/decoder_pipe/pipereg/U15/dmem_ctl_o_4> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/mips/E1/decoder_pipe/pipereg/U15/dmem_ctl_o_0> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/mips/E1/decoder_pipe/pipereg/U3/dmem_ctl_o_4> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/mips/E1/decoder_pipe/pipereg/U3/dmem_ctl_o_0> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatam_31> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatam_30> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatam_29> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatam_28> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatam_27> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatam_26> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatam_25> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatam_23> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatam_22> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatam_21> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatam_20> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatam_19> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatam_18> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatam_17> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatam_11> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatam_10> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatam_9> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatam_8> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatam_7> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatam_6> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatam_5> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatam_4> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatam_3> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatam_2> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatam_1> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahb0/r.hrdatam_0> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ahb0/r.hmasterlockd> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <apb0/r.haddr_1> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <apb0/r.haddr_0> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <irqctrl.irqctrl0/r.irl_0_3> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <irqctrl.irqctrl0/r.irl_0_2> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <irqctrl.irqctrl0/r.irl_0_1> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <irqctrl.irqctrl0/r.irl_0_0> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <irqctrl.irqctrl0/r.cpurst_0> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <gpt.timer0/r.wdogn> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <gpt.timer0/r.wdog> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/m0.c0/icache0/r.diagrdy> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/m0.c0/icache0/r.diagset_0> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/m0.c0/dcache0/rs.addr_31> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/m0.c0/dcache0/rs.addr_30> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/m0.c0/dcache0/rs.addr_29> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/m0.c0/dcache0/rs.addr_28> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/m0.c0/dcache0/rs.addr_27> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/m0.c0/dcache0/rs.addr_26> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/m0.c0/dcache0/rs.addr_25> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/m0.c0/dcache0/rs.addr_24> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/m0.c0/dcache0/rs.addr_23> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/m0.c0/dcache0/rs.addr_22> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/m0.c0/dcache0/rs.addr_21> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/m0.c0/dcache0/rs.addr_20> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/m0.c0/dcache0/rs.addr_19> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/m0.c0/dcache0/rs.addr_18> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/m0.c0/dcache0/rs.addr_17> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/m0.c0/dcache0/rs.addr_16> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/m0.c0/dcache0/rs.addr_15> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/m0.c0/dcache0/rs.addr_14> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/m0.c0/dcache0/rs.addr_13> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/m0.c0/dcache0/rs.addr_12> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/m0.c0/dcache0/r.mexc> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/m0.c0/a0/r.werr> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.hwdata_31> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.hwdata_30> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.hwdata_29> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.hwdata_28> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.hwdata_27> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.hwdata_26> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.hwdata_25> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.hwdata_24> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.hwdata_23> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.hwdata_22> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.hwdata_21> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.hwdata_20> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.hwdata_19> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.hwdata_18> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.hwdata_17> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.hwdata_16> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.hwdata_15> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.hwdata_14> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.hwdata_13> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.hwdata_12> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.hwdata_11> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.hwdata_10> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.hwdata_9> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.hwdata_8> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.hwdata_7> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.hwdata_6> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.hwdata_5> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.hwdata_4> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.hwdata_3> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.hwdata_2> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.hwdata_1> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.hwdata_0> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.haddr_24> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.haddr_23> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.haddr_19> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.haddr_18> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.haddr_17> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.haddr_16> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.haddr_15> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.haddr_14> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.haddr_13> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.haddr_12> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.haddr_11> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.haddr_10> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.haddr_9> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.haddr_8> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.slv.haddr_7> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.reset_0> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.dsugen.dsu0/x0/r.halt_0> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <dcomgen.dcom0/ahbmst0/r.start> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <ahbjtaggen0.ahbjtag0/ahbmst0/r.start> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sa_14> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sa_13> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sa_12> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sa_11> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sa_10> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sa_9> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sa_8> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sa_7> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sa_6> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sa_5> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sa_4> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sa_3> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sa_2> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sa_1> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sa_0> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.mben_3> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.mben_2> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.mben_1> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.mben_0> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rbdrive_31> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rbdrive_30> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rbdrive_29> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rbdrive_28> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rbdrive_27> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rbdrive_26> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rbdrive_25> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rbdrive_24> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rbdrive_23> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rbdrive_22> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rbdrive_21> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rbdrive_20> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rbdrive_19> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rbdrive_18> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rbdrive_17> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rbdrive_16> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rbdrive_15> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rbdrive_14> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rbdrive_13> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rbdrive_12> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rbdrive_11> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rbdrive_10> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rbdrive_9> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rbdrive_8> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rbdrive_7> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rbdrive_6> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rbdrive_5> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rbdrive_4> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rbdrive_3> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rbdrive_2> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rbdrive_1> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rbdrive_0> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_63> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_62> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_61> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_60> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_59> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_58> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_57> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_56> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_55> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_54> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_53> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_52> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_51> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_50> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_49> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_48> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_47> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_46> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_45> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_44> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_43> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_42> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_41> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_40> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_39> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_38> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_37> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_36> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_35> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_34> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_33> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_32> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_31> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_30> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_29> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_28> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_27> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_26> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_25> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_24> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_23> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_22> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_21> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_20> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_19> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_18> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_17> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_16> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_15> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_14> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_13> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_12> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_11> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_10> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_9> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_8> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_7> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_6> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_5> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_4> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_3> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_2> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_1> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/rsbdrive_0> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.address_31> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.address_30> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.address_29> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.address_28> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sdwritedata_31> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sdwritedata_30> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sdwritedata_29> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sdwritedata_28> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sdwritedata_27> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sdwritedata_26> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sdwritedata_25> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sdwritedata_24> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sdwritedata_23> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sdwritedata_22> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sdwritedata_21> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sdwritedata_20> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sdwritedata_19> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sdwritedata_18> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sdwritedata_17> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sdwritedata_16> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sdwritedata_15> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sdwritedata_14> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sdwritedata_13> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sdwritedata_12> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sdwritedata_11> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sdwritedata_10> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sdwritedata_9> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sdwritedata_8> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sdwritedata_7> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sdwritedata_6> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sdwritedata_5> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sdwritedata_4> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sdwritedata_3> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sdwritedata_2> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sdwritedata_1> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <mctrl0/r.sdwritedata_0> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/mips/E1/iRF_stage/ins_reg/r32_o_31> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/mips/E1/iRF_stage/ins_reg/r32_o_30> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/mips/E1/iRF_stage/ins_reg/r32_o_29> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/mips/E1/iRF_stage/ins_reg/r32_o_28> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/mips/E1/iRF_stage/ins_reg/r32_o_27> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/mips/E1/iRF_stage/ins_reg/r32_o_26> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/r.valid_7> is unconnected in block <leon3mp>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/r.hit> is unconnected in block <leon3mp>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/r.valid_6> is unconnected in block <leon3mp>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/r.valid_5> is unconnected in block <leon3mp>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/r.valid_3> is unconnected in block <leon3mp>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/r.valid_2> is unconnected in block <leon3mp>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/r.valid_1> is unconnected in block <leon3mp>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/r.valid_0> is unconnected in block <leon3mp>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/r.valid_4> is unconnected in block <leon3mp>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <mctrl0/r.hresp_0> is unconnected in block <leon3mp>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <mctrl0/r.sdhsel> is unconnected in block <leon3mp>.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_127> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_10> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_13> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_11> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_12> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_14> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_20> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_21> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_15> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_16> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_22> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_17> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_19> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_23> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_18> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_24> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_25> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_26> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_30> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_31> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_32> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_27> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_29> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_28> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_33> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_34> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_40> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_36> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_35> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_41> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_42> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_37> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ahbjtaggen0.ahbjtag0/ahbmst0/r.retry> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dcomgen.dcom0/ahbmst0/r.retry> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.write> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_99> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_97> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_98> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_100> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_103> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_101> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_102> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_104> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_106> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_105> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_110> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_111> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_107> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_125> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_119> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_126> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_124> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_118> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_117> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_122> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_123> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_121> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_116> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_120> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_115> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_114> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_109> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_108> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_112> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_113> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_74> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_69> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_75> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_1> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_80> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_2> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_3> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_81> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_76> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_82> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_77> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_83> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_4> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_78> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_5> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_6> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_96> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_89> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_94> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_95> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_88> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_93> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_87> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_92> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_9> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_8> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_86> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_7> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_91> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_85> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_90> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_84> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_79> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_44> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_43> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_38> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_39> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_50> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_46> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_45> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_51> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_52> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_47> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_54> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_53> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_48> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_49> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_60> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_56> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_68> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_73> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_0> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_67> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_72> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_66> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_70> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_71> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_65> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_59> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_58> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_63> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_64> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_57> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_62> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_61> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.lru_55> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/m0.c0/icache0/r.faddr_6> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/m0.c0/icache0/r.faddr_5> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/m0.c0/icache0/r.faddr_4> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/m0.c0/icache0/r.faddr_3> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/m0.c0/icache0/r.faddr_2> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/m0.c0/icache0/r.faddr_1> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/m0.c0/icache0/r.faddr_0> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:2677 - Node <l3.cpu[0].u0/p0/m0.c0/a0/r.hcache> of sequential type is unconnected in block <leon3mp>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.waddr_0> is unconnected in block <leon3mp>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.waddr_1> is unconnected in block <leon3mp>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.waddr_5> is unconnected in block <leon3mp>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.waddr_6> is unconnected in block <leon3mp>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.waddr_2> is unconnected in block <leon3mp>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.waddr_3> is unconnected in block <leon3mp>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.waddr_4> is unconnected in block <leon3mp>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/r.setrepl_0> is unconnected in block <leon3mp>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/rl.set_0> is unconnected in block <leon3mp>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <l3.cpu[0].u0/p0/m0.c0/icache0/r.flush3> is unconnected in block <leon3mp>.
WARNING:Xst:1710 - FF/Latch <l3.cpu[0].u0/p0/m0.c0/a0/r.retry2> (without init value) has a constant value of 0 in block <leon3mp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2398 - RAMs <l3.cpu[0].u0/tbmem_gen.tbmem0/mem0[1].ram0/s64.xc2v.x0/a8.r0>, <l3.cpu[0].u0/tbmem_gen.tbmem0/mem0[0].ram0/s64.xc2v.x0/a8.r0> are equivalent
WARNING:Xst:2398 - RAMs <l3.cpu[0].u0/cmem0/ime.im0[0].idata0/xc2v.x0/a10.x[1].r>, <l3.cpu[0].u0/cmem0/ime.im0[1].idata0/xc2v.x0/a10.x[1].r> are equivalent
WARNING:Xst:2398 - RAMs <l3.cpu[0].u0/cmem0/ime.im0[0].idata0/xc2v.x0/a10.x[0].r>, <l3.cpu[0].u0/cmem0/ime.im0[1].idata0/xc2v.x0/a10.x[0].r> are equivalent
WARNING:Xst:2398 - RAMs <l3.cpu[0].u0/cmem0/ime.im0[0].itags0/xc2v.x0/a8.x[0].r0>, <l3.cpu[0].u0/cmem0/ime.im0[1].itags0/xc2v.x0/a8.x[0].r0> are equivalent

Mapping all equations...
Building and optimizing final netlist ...
INFO:Xst:2261 - The FF/Latch <ahb0/r.hrdatam_13> in Unit <leon3mp> is equivalent to the following FF/Latch, which will be removed : <ahb0/r.hrdatam_12> 
INFO:Xst:2261 - The FF/Latch <l3.cpu[0].u0/p0/mips/E1/decoder_pipe/pipereg/U3/dmem_ctl_o_3> in Unit <leon3mp> is equivalent to the following FF/Latch, which will be removed : <l3.cpu[0].u0/p0/mips/E1/decoder_pipe/pipereg/U3/dmem_ctl_o_2> 
INFO:Xst:2261 - The FF/Latch <ahb0/r.hrdatam_16> in Unit <leon3mp> is equivalent to the following FF/Latch, which will be removed : <ahb0/r.hrdatam_15> 
INFO:Xst:2261 - The FF/Latch <l3.cpu[0].u0/p0/mips/E1/decoder_pipe/pipereg/U15/dmem_ctl_o_3> in Unit <leon3mp> is equivalent to the following FF/Latch, which will be removed : <l3.cpu[0].u0/p0/mips/E1/decoder_pipe/pipereg/U15/dmem_ctl_o_2> 
Replicating register mctrl0/r.iosn_0 to handle IOB=TRUE attribute
Replicating register mctrl0/r.read to handle IOB=TRUE attribute
Replicating register mctrl0/sd0.sdctrl/r.rasn to handle IOB=TRUE attribute
Replicating register mctrl0/sd0.sdctrl/r.sdwen to handle IOB=TRUE attribute
Replicating register mctrl0/r.oen to handle IOB=TRUE attribute
Replicating register mctrl0/sd0.sdctrl/r.casn to handle IOB=TRUE attribute
Replicating register mctrl0/r.writen to handle IOB=TRUE attribute
Replicating register dcomgen.dcom0/dcom_uart0/r.tshift_0 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dir_17 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dout_17 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dir_16 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dout_16 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dir_15 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dout_15 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dir_14 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dout_14 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dir_13 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dout_13 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dir_12 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dout_12 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dir_11 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dout_11 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dir_10 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dout_10 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dir_9 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dout_9 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dir_8 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dout_8 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dir_7 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dout_7 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dir_6 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dout_6 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dir_5 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dout_5 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dir_4 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dout_4 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dir_3 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dout_3 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dir_2 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dout_2 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dir_1 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dout_1 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dir_0 to handle IOB=TRUE attribute
Replicating register gpio0.grgpio0/r.dout_0 to handle IOB=TRUE attribute
Replicating register mctrl0/r.bdrive_0 to handle IOB=TRUE attribute
Replicating register mctrl0/r.writedata_31 to handle IOB=TRUE attribute
Replicating register mctrl0/r.writedata_30 to handle IOB=TRUE attribute
Replicating register mctrl0/r.writedata_29 to handle IOB=TRUE attribute
Replicating register mctrl0/r.writedata_28 to handle IOB=TRUE attribute
Replicating register mctrl0/r.writedata_27 to handle IOB=TRUE attribute
Replicating register mctrl0/r.writedata_26 to handle IOB=TRUE attribute
Replicating register mctrl0/r.writedata_25 to handle IOB=TRUE attribute
Replicating register mctrl0/r.writedata_24 to handle IOB=TRUE attribute
Replicating register mctrl0/r.bdrive_1 to handle IOB=TRUE attribute
Replicating register mctrl0/r.writedata_23 to handle IOB=TRUE attribute
Replicating register mctrl0/r.writedata_22 to handle IOB=TRUE attribute
Replicating register mctrl0/r.writedata_21 to handle IOB=TRUE attribute
Replicating register mctrl0/r.writedata_20 to handle IOB=TRUE attribute
Replicating register mctrl0/r.writedata_19 to handle IOB=TRUE attribute
Replicating register mctrl0/r.writedata_18 to handle IOB=TRUE attribute
Replicating register mctrl0/r.writedata_17 to handle IOB=TRUE attribute
Replicating register mctrl0/r.writedata_16 to handle IOB=TRUE attribute
Replicating register mctrl0/r.bdrive_2 to handle IOB=TRUE attribute
Replicating register mctrl0/r.writedata_15 to handle IOB=TRUE attribute
Replicating register mctrl0/r.writedata_14 to handle IOB=TRUE attribute
Replicating register mctrl0/r.writedata_13 to handle IOB=TRUE attribute
Replicating register mctrl0/r.writedata_12 to handle IOB=TRUE attribute
Replicating register mctrl0/r.writedata_11 to handle IOB=TRUE attribute
Replicating register mctrl0/r.writedata_10 to handle IOB=TRUE attribute
Replicating register mctrl0/r.writedata_9 to handle IOB=TRUE attribute
Replicating register mctrl0/r.writedata_8 to handle IOB=TRUE attribute
Replicating register mctrl0/r.bdrive_3 to handle IOB=TRUE attribute
Replicating register mctrl0/r.writedata_7 to handle IOB=TRUE attribute
Replicating register mctrl0/r.writedata_6 to handle IOB=TRUE attribute
Replicating register mctrl0/r.writedata_5 to handle IOB=TRUE attribute
Replicating register mctrl0/r.writedata_4 to handle IOB=TRUE attribute
Replicating register mctrl0/r.writedata_3 to handle IOB=TRUE attribute
Replicating register mctrl0/r.writedata_2 to handle IOB=TRUE attribute
Replicating register mctrl0/r.writedata_1 to handle IOB=TRUE attribute
Replicating register mctrl0/r.writedata_0 to handle IOB=TRUE attribute
Replicating register mctrl0/sd0.sdctrl/r.sdcsn_1 to handle IOB=TRUE attribute
Replicating register mctrl0/sd0.sdctrl/r.sdcsn_0 to handle IOB=TRUE attribute
Replicating register mctrl0/sd0.sdctrl/r.dqm_3 to handle IOB=TRUE attribute
Replicating register mctrl0/sd0.sdctrl/r.dqm_2 to handle IOB=TRUE attribute
Replicating register mctrl0/sd0.sdctrl/r.dqm_1 to handle IOB=TRUE attribute
Replicating register mctrl0/sd0.sdctrl/r.dqm_0 to handle IOB=TRUE attribute
Replicating register mctrl0/r.ramsn_1 to handle IOB=TRUE attribute
Replicating register mctrl0/r.ramsn_0 to handle IOB=TRUE attribute
Replicating register mctrl0/r.address_27 to handle IOB=TRUE attribute
Replicating register mctrl0/r.address_26 to handle IOB=TRUE attribute
Replicating register mctrl0/r.address_25 to handle IOB=TRUE attribute
Replicating register mctrl0/r.address_24 to handle IOB=TRUE attribute
Replicating register mctrl0/r.address_23 to handle IOB=TRUE attribute
Replicating register mctrl0/r.address_22 to handle IOB=TRUE attribute
Replicating register mctrl0/r.address_21 to handle IOB=TRUE attribute
Replicating register mctrl0/r.address_20 to handle IOB=TRUE attribute
Replicating register mctrl0/r.address_19 to handle IOB=TRUE attribute
Replicating register mctrl0/r.address_18 to handle IOB=TRUE attribute
Replicating register mctrl0/r.address_17 to handle IOB=TRUE attribute
Replicating register mctrl0/r.address_16 to handle IOB=TRUE attribute
Replicating register mctrl0/r.address_15 to handle IOB=TRUE attribute
Replicating register mctrl0/r.address_14 to handle IOB=TRUE attribute
Replicating register mctrl0/r.address_13 to handle IOB=TRUE attribute
Replicating register mctrl0/r.address_12 to handle IOB=TRUE attribute
Replicating register mctrl0/r.address_11 to handle IOB=TRUE attribute
Replicating register mctrl0/r.address_10 to handle IOB=TRUE attribute
Replicating register mctrl0/r.address_9 to handle IOB=TRUE attribute
Replicating register mctrl0/r.address_8 to handle IOB=TRUE attribute
Replicating register mctrl0/r.address_7 to handle IOB=TRUE attribute
Replicating register mctrl0/r.address_6 to handle IOB=TRUE attribute
Replicating register mctrl0/r.address_5 to handle IOB=TRUE attribute
Replicating register mctrl0/r.address_4 to handle IOB=TRUE attribute
Replicating register mctrl0/r.address_3 to handle IOB=TRUE attribute
Replicating register mctrl0/r.address_2 to handle IOB=TRUE attribute
Replicating register mctrl0/r.address_1 to handle IOB=TRUE attribute
Replicating register mctrl0/r.address_0 to handle IOB=TRUE attribute
Replicating register mctrl0/r.romsn_1 to handle IOB=TRUE attribute
Replicating register mctrl0/r.romsn_0 to handle IOB=TRUE attribute
Replicating register mctrl0/r.ramoen_4 to handle IOB=TRUE attribute
Replicating register mctrl0/r.ramoen_3 to handle IOB=TRUE attribute
Replicating register mctrl0/r.ramoen_2 to handle IOB=TRUE attribute
Replicating register mctrl0/r.ramoen_1 to handle IOB=TRUE attribute
Replicating register mctrl0/r.ramoen_0 to handle IOB=TRUE attribute
Replicating register mctrl0/r.wrn_3 to handle IOB=TRUE attribute
Replicating register mctrl0/r.wrn_2 to handle IOB=TRUE attribute
Replicating register mctrl0/r.wrn_1 to handle IOB=TRUE attribute
Replicating register mctrl0/r.wrn_0 to handle IOB=TRUE attribute

FlipFlop l3.cpu[0].u0/p0/m0.c0/dcache0/r.req has been replicated 1 time(s)
FlipFlop l3.cpu[0].u0/p0/m0.c0/icache0/r.req has been replicated 1 time(s)
FlipFlop l3.cpu[0].u0/p0/mips/E1/decoder_pipe/pipereg/U12/wb_we_o_0 has been replicated 1 time(s)
FlipFlop l3.cpu[0].u0/p0/mips/E1/decoder_pipe/pipereg/U18/wb_mux_ctl_o_0 has been replicated 1 time(s)
FlipFlop l3.cpu[0].u0/p0/mips/E1/rnd_pass2/r5_o_2 has been replicated 1 time(s)
FlipFlop l3.cpu[0].u0/p0/mips/E1/rnd_pass2/r5_o_3 has been replicated 1 time(s)

Final Macro Processing ...

Processing Unit <leon3mp> :
        Found 2-bit shift register for signal <ahbjtaggen0.ahbjtag0/jtagcom0/r.tdi2>.
        Found 2-bit shift register for signal <ahbjtaggen0.ahbjtag0/jtagcom0/r.shift2>.
        Found 4-bit shift register for signal <clkgen0/xc3s.v/dll1rst_0>.
Unit <leon3mp> processed.

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 2292
 Flip-Flops                                            : 2292
# Shift Registers                                      : 3
 2-bit shift register                                  : 2
 4-bit shift register                                  : 1

=========================================================================

=========================================================================
*                           Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : leon3mp
Output Format                      : ngc
Optimization Goal                  : SPEED
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 264

Cell Usage :
# BELS                             : 10621
#      GND                         : 1
#      INV                         : 86
#      LUT1                        : 150
#      LUT2                        : 781
#      LUT2_D                      : 16
#      LUT2_L                      : 8
#      LUT3                        : 1627
#      LUT3_D                      : 27
#      LUT3_L                      : 65
#      LUT4                        : 5068
#      LUT4_D                      : 147
#      LUT4_L                      : 524
#      MULT_AND                    : 30
#      MUXCY                       : 739
#      MUXF5                       : 806
#      MUXF6                       : 31
#      MUXF7                       : 22
#      VCC                         : 1
#      XORCY                       : 492
# FlipFlops/Latches                : 2300
#      FD                          : 424
#      FDC                         : 7
#      FDE                         : 952
#      FDP                         : 67
#      FDPE                        : 36
#      FDR                         : 78
#      FDRE                        : 219
#      FDRS                        : 30
#      FDS                         : 416
#      FDSE                        : 70
#      LD                          : 1
# RAMS                             : 13
#      RAMB16_S18                  : 6
#      RAMB16_S36_S36              : 7
# Shift Registers                  : 3
#      SRL16                       : 3
# Clock Buffers                    : 2
#      BUFG                        : 2
# IO Buffers                       : 159
#      IBUF                        : 9
#      IBUFG                       : 2
#      IOBUF                       : 54
#      OBUF                        : 92
#      OBUFT                       : 2
# DCMs                             : 2
#      DCM                         : 2
# Others                           : 1
#      BSCAN_SPARTAN3              : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s1500fg456-4 

 Number of Slices:                     4538  out of  13312    34%  
 Number of Slice Flip Flops:           2086  out of  26624     7%  
 Number of 4 input LUTs:               8502  out of  26624    31%  
    Number used as logic:              8499
    Number used as Shift registers:       3
 Number of IOs:                         264
 Number of bonded IOBs:                 159  out of    333    47%  
    IOB Flip Flops:                     214
 Number of BRAMs:                        13  out of     32    40%  
 Number of GCLKs:                         2  out of      8    25%  
 Number of DCMs:                          2  out of      4    50%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------+-------+
Clock Signal                                                                                                                 | Clock buffer(FF name)                                     | Load  |
-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------+-------+
clk                                                                                                                          | clkgen0/xc3s.v/dll0:CLKFX                                 | 2309  |
l3.cpu[0].u0/p0/mips/E1/iRF_stage/i_pc_gen/branch_cmp_eq0000(l3.cpu[0].u0/p0/mips/E1/iRF_stage/i_pc_gen/branch_cmp_eq00001:O)| NONE(*)(l3.cpu[0].u0/p0/mips/E1/iRF_stage/i_pc_gen/branch)| 1     |
-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------------------------------------+-----------------------------------------+-------+
Control Signal                                                   | Buffer(FF name)                         | Load  |
-----------------------------------------------------------------+-----------------------------------------+-------+
ahb0/rst_inv(ua1.uart1/rst_inv1_INV_0:O)                         | NONE(gpio0.grgpio0/r.dir_11)            | 100   |
clkgen0/xc3s.v/dll0rst(rst0/rstoutraw_inv1_INV_0:O)              | NONE(rst0/r_0)                          | 6     |
clkgen0/xc3s.v/dll0lock_inv(clkgen0/xc3s.v/dll0lock_inv1_INV_0:O)| NONE(clkgen0/xc3s.v/dll0lock_inv_shift2)| 4     |
-----------------------------------------------------------------+-----------------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 21.148ns (Maximum Frequency: 47.286MHz)
   Minimum input arrival time before clock: 1.970ns
   Maximum output required time after clock: 8.517ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 21.148ns (frequency: 47.286MHz)
  Total number of paths / destination ports: 22934353 / 4492
-------------------------------------------------------------------------
Delay:               26.435ns (Levels of Logic = 43)
  Source:            l3.cpu[0].u0/p0/mips/E1/iforward/fw_reg_rnt/q_4 (FF)
  Destination:       l3.cpu[0].u0/p0/m0.c0/dcache0/r.hit (FF)
  Source Clock:      clk rising 0.8X
  Destination Clock: clk rising 0.8X

  Data Path: l3.cpu[0].u0/p0/mips/E1/iforward/fw_reg_rnt/q_4 to l3.cpu[0].u0/p0/m0.c0/dcache0/r.hit
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   0.720   1.216  l3.cpu[0].u0/p0/mips/E1/iforward/fw_reg_rnt/q_4 (l3.cpu[0].u0/p0/mips/E1/iforward/fw_reg_rnt/q_4)
     LUT4:I0->O           17   0.551   1.371  l3.cpu[0].u0/p0/mips/E1/iforward/fw_alu_rt/mux_fw_cmp_eq0001526 (l3.cpu[0].u0/p0/mips/E1/iforward/fw_alu_rt/mux_fw_cmp_eq0001526)
     LUT4:I3->O           51   0.551   1.988  l3.cpu[0].u0/p0/mips/E1/iforward/fw_alu_rt/mux_fw_cmp_eq0001578 (l3.cpu[0].u0/p0/mips/E1/iforward/fw_alu_rt/mux_fw_cmp_eq0001)
     LUT4_D:I3->O         26   0.551   1.845  l3.cpu[0].u0/p0/mips/E1/iexec_stage/dmem_fw_mux/dout(0)11 (l3.cpu[0].u0/p0/mips/E1/BUS1196(1))
     LUT4:I3->O            2   0.551   0.903  l3.cpu[0].u0/p0/mips/E1/iexec_stage/i_alu_muxb/Mmux_b_o121_SW3 (N1796)
     LUT4:I3->O           38   0.551   2.082  l3.cpu[0].u0/p0/mips/E1/iexec_stage/i_alu_muxb/Mmux_b_o3945 (l3.cpu[0].u0/p0/mips/E1/iexec_stage/BUS468(2))
     LUT2:I1->O            1   0.551   0.000  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_lut(2) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_lut(2))
     MUXCY:S->O            1   0.500   0.000  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(2) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(2))
     MUXCY:CI->O           1   0.064   0.000  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(3) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(3))
     MUXCY:CI->O           1   0.064   0.000  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(4) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(4))
     MUXCY:CI->O           1   0.064   0.000  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(5) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(5))
     MUXCY:CI->O           1   0.064   0.000  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(6) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(6))
     MUXCY:CI->O           1   0.064   0.000  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(7) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(7))
     MUXCY:CI->O           1   0.064   0.000  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(8) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(8))
     MUXCY:CI->O           1   0.064   0.000  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(9) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(9))
     MUXCY:CI->O           1   0.064   0.000  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(10) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(10))
     MUXCY:CI->O           1   0.064   0.000  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(11) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(11))
     MUXCY:CI->O           1   0.064   0.000  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(12) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(12))
     MUXCY:CI->O           1   0.064   0.000  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(13) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(13))
     MUXCY:CI->O           1   0.064   0.000  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(14) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(14))
     MUXCY:CI->O           1   0.064   0.000  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(15) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(15))
     MUXCY:CI->O           1   0.064   0.000  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(16) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(16))
     MUXCY:CI->O           1   0.064   0.000  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(17) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(17))
     MUXCY:CI->O           1   0.064   0.000  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(18) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(18))
     MUXCY:CI->O           1   0.064   0.000  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(19) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(19))
     MUXCY:CI->O           1   0.064   0.000  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(20) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(20))
     MUXCY:CI->O           1   0.064   0.000  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(21) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(21))
     MUXCY:CI->O           1   0.064   0.000  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(22) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(22))
     MUXCY:CI->O           1   0.064   0.000  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(23) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(23))
     MUXCY:CI->O           1   0.064   0.000  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(24) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(24))
     MUXCY:CI->O           1   0.064   0.000  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(25) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(25))
     MUXCY:CI->O           1   0.064   0.000  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(26) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(26))
     MUXCY:CI->O           1   0.064   0.000  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(27) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(27))
     MUXCY:CI->O           1   0.064   0.000  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(28) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(28))
     MUXCY:CI->O           1   0.064   0.000  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(29) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_cy(29))
     XORCY:CI->O           1   0.904   0.869  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0001_xor(30) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/alu_out_addsub0001(30))
     LUT3:I2->O            1   0.551   0.869  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/alu_out_mux0001(30)1 (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/alu_out_mux0001(30))
     LUT3:I2->O            1   0.551   0.000  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0000_lut(30) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0000_lut(30))
     MUXCY:S->O            0   0.500   0.000  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0000_cy(30) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0000_cy(30))
     XORCY:CI->O           2   0.904   1.072  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/Madd_alu_out_addsub0000_xor(31) (l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/mips_alu/alu_out_addsub0000(31))
     LUT3:I1->O            7   0.551   1.134  l3.cpu[0].u0/p0/mips/E1/iexec_stage/MIPS_alu/c(31)465 (l3.cpu[0].u0/p0/dci_maddress(31))
     LUT4:I2->O            1   0.551   0.000  l3.cpu[0].u0/p0/m0.c0/dcache0/Mcompar_hitv_cmp_eq0000_lut(9) (l3.cpu[0].u0/p0/m0.c0/dcache0/Mcompar_hitv_cmp_eq0000_lut(9))
     MUXCY:S->O            1   0.739   0.827  l3.cpu[0].u0/p0/m0.c0/dcache0/Mcompar_hitv_cmp_eq0000_cy(9) (l3.cpu[0].u0/p0/m0.c0/dcache0/Mcompar_hitv_cmp_eq0000_cy(9))
     LUT4:I3->O            1   0.551   0.000  l3.cpu[0].u0/p0/m0.c0/dcache0/r_hit_mux000033 (l3.cpu[0].u0/p0/m0.c0/dcache0/r_hit_mux0000)
     FDR:D                     0.203          l3.cpu[0].u0/p0/m0.c0/dcache0/r.hit
    ----------------------------------------
    Total                     26.435ns (12.259ns logic, 14.176ns route)
                                       (46.4% logic, 53.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 65 / 63
-------------------------------------------------------------------------
Offset:              1.970ns (Levels of Logic = 1)
  Source:            ahbjtaggen0.ahbjtag0/tap0/xc3s.u0/u0:SEL1 (PAD)
  Destination:       ahbjtaggen0.ahbjtag0/jtagcom0/r.tck_0 (FF)
  Destination Clock: clk rising 0.8X

  Data Path: ahbjtaggen0.ahbjtag0/tap0/xc3s.u0/u0:SEL1 to ahbjtaggen0.ahbjtag0/jtagcom0/r.tck_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    BSCAN_SPARTAN3:SEL1    2   0.000   1.216  ahbjtaggen0.ahbjtag0/tap0/xc3s.u0/u0 (ahbjtaggen0.ahbjtag0/ltapo_asel)
     LUT3:I0->O            1   0.551   0.000  ahbjtaggen0.ahbjtag0/tap0/xc3s.u0/tapo_tck1 (ahbjtaggen0.ahbjtag0/tapo_tck)
     FD:D                      0.203          ahbjtaggen0.ahbjtag0/jtagcom0/r.tck_0
    ----------------------------------------
    Total                      1.970ns (0.754ns logic, 1.216ns route)
                                       (38.3% logic, 61.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 164 / 110
-------------------------------------------------------------------------
Offset:              8.517ns (Levels of Logic = 2)
  Source:            l3.dsugen.dsu0/x0/r.act (FF)
  Destination:       dsuact (PAD)
  Source Clock:      clk rising 0.8X

  Data Path: l3.dsugen.dsu0/x0/r.act to dsuact
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   0.720   0.801  l3.dsugen.dsu0/x0/r.act (l3.dsugen.dsu0/x0/r.act)
     INV:I->O              1   0.551   0.801  ndsuact1_INV_0 (ndsuact)
     OBUF:I->O                 5.644          l3.dsugen.dsuact_pad/xcv.x0/ttl0.slow0.op (dsuact)
    ----------------------------------------
    Total                      8.517ns (6.915ns logic, 1.602ns route)
                                       (81.2% logic, 18.8% route)

=========================================================================
WARNING:Xst:616 - Invalid property "dont_touch TRUE": Did not attach to ahbjtaggen0.ahbjtag0/tap0/xc3s.u0/u0.


Total REAL time to Xst completion: 267.00 secs
Total CPU time to Xst completion: 267.09 secs
 
--> 

Total memory usage is 372220 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings : 3284 (   0 filtered)
Number of infos    :   32 (   0 filtered)

../../bin/route_ngc leon3mp leon3mp.ucf xc3s1500-fg456-4 high ../../boards/gr-xc3s-1500/default.ut ../../netlists/xilinx/spartan3
ngdbuild leon3mp.ngc -aul -uc leon3mp.ucf -p xc3s1500-fg456-4 -sd ../../netlists/xilinx/spartan3/xst -sd ../../netlists/xilinx/spartan3
Release 11.1 - ngdbuild L.33 (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.

Command Line: c:\Xilinx\11.1\ISE\bin\nt\unwrapped\ngdbuild.exe leon3mp.ngc -aul
-uc leon3mp.ucf -p xc3s1500-fg456-4 -sd ../../netlists/xilinx/spartan3/xst -sd
../../netlists/xilinx/spartan3

Reading NGO file
"c:/grlib-gpl-1.0.19-b3188/designs/leon3-gr-xc3s-1500/leon3mp.ngc" ...
Gathering constraint information from source properties...
Done.

Applying constraints in "leon3mp.ucf" to the design...
Resolving constraint associations...
Checking Constraint Associations...
INFO:ConstraintSystem:59 - Constraint <INST "clkgen0_xc3s_v_dll0" LOC =
   DCM_X1Y0;> [leon3mp.ucf(32)]: INST "clkgen0_xc3s_v_dll0" not found.  Please
   verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <INST "clkgen0_xc3s_v_sd0_dll1" LOC =
   DCM_X0Y0;> [leon3mp.ucf(33)]: INST "clkgen0_xc3s_v_sd0_dll1" not found. 
   Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <INST "clkgen0_v_dll0" LOC = DCM_X1Y0;>
   [leon3mp.ucf(34)]: INST "clkgen0_v_dll0" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <INST "clkgen0_v_dll1" LOC = DCM_X0Y0;>
   [leon3mp.ucf(35)]: INST "clkgen0_v_dll1" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <INST "clkgen0/v/dll0" LOC = DCM_X1Y0;>
   [leon3mp.ucf(36)]: INST "clkgen0/v/dll0" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <INST "clkgen0/v/dll1" LOC = DCM_X0Y0;>
   [leon3mp.ucf(37)]: INST "clkgen0/v/dll1" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <INST "clkgen0.xc3s.v.dll0" LOC =
   DCM_X1Y0;> [leon3mp.ucf(40)]: INST "clkgen0.xc3s.v.dll0" not found.  Please
   verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <INST "clkgen0.xc3s.v.sd0.dll1" LOC =
   DCM_X0Y0;> [leon3mp.ucf(41)]: INST "clkgen0.xc3s.v.sd0.dll1" not found. 
   Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <INST "spw.swloop.0.sw0/grspwc0/rxclko"
   LOC = "SLICE_X0Y62";> [leon3mp.ucf(53)]: INST
   "spw.swloop.0.sw0/grspwc0/rxclko" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <INST "spw.swloop[0].sw0/grspwc0/rxclko"
   LOC = "SLICE_X0Y62";> [leon3mp.ucf(54)]: INST
   "spw.swloop[0].sw0/grspwc0/rxclko" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <INST "spw.swloop.1.sw0/grspwc0/rxclko"
   LOC = "SLICE_X0Y48";> [leon3mp.ucf(55)]: INST
   "spw.swloop.1.sw0/grspwc0/rxclko" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <INST "spw.swloop[1].sw0/grspwc0/rxclko"
   LOC = "SLICE_X0Y48";> [leon3mp.ucf(56)]: INST
   "spw.swloop[1].sw0/grspwc0/rxclko" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <INST "spw.swloop.2.sw0/grspwc0/rxclko"
   LOC = "SLICE_X0Y24";> [leon3mp.ucf(57)]: INST
   "spw.swloop.2.sw0/grspwc0/rxclko" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <INST "spw.swloop[2].sw0/grspwc0/rxclko"
   LOC = "SLICE_X0Y24";> [leon3mp.ucf(58)]: INST
   "spw.swloop[2].sw0/grspwc0/rxclko" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <INST "sw00/grspwc0/rxclko" LOC =
   SLICE_X0Y62;> [leon3mp.ucf(59)]: INST "sw00/grspwc0/rxclko" not found. 
   Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <INST "sw01/grspwc0/rxclko" LOC =
   SLICE_X0Y48;> [leon3mp.ucf(60)]: INST "sw01/grspwc0/rxclko" not found. 
   Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <INST "sw02/grspwc0/rxclko" LOC =
   SLICE_X0Y24;> [leon3mp.ucf(61)]: INST "sw02/grspwc0/rxclko" not found. 
   Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "clk2" LOC = "ab12" |>
   [leon3mp.ucf(94)]: NET "clk2" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(94)]:
   NET "clk2" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "emdint" LOC = "c2" |>
   [leon3mp.ucf(130)]: NET "emdint" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(130)]:
   NET "emdint" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(0)" LOC = "m6" |>
   [leon3mp.ucf(149)]: NET "genio(0)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(149)]:
   NET "genio(0)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(1)"  LOC = "m5" |>
   [leon3mp.ucf(150)]: NET "genio(1)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(150)]:
   NET "genio(1)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(10)" LOC = "t6" |>
   [leon3mp.ucf(151)]: NET "genio(10)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(151)]:
   NET "genio(10)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(11)" LOC = "t5" |>
   [leon3mp.ucf(152)]: NET "genio(11)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(152)]:
   NET "genio(11)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(12)" LOC = "v5" |>
   [leon3mp.ucf(153)]: NET "genio(12)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(153)]:
   NET "genio(12)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(13)" LOC = "u5" |>
   [leon3mp.ucf(154)]: NET "genio(13)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(154)]:
   NET "genio(13)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(14)" LOC = "w4" |>
   [leon3mp.ucf(155)]: NET "genio(14)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(155)]:
   NET "genio(14)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(15)" LOC = "w3" |>
   [leon3mp.ucf(156)]: NET "genio(15)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(156)]:
   NET "genio(15)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(16)" LOC = "y3" |>
   [leon3mp.ucf(157)]: NET "genio(16)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(157)]:
   NET "genio(16)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(17)" LOC = "y2" |>
   [leon3mp.ucf(158)]: NET "genio(17)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(158)]:
   NET "genio(17)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(18)" LOC = "y1" |>
   [leon3mp.ucf(159)]: NET "genio(18)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(159)]:
   NET "genio(18)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(19)" LOC = "u6" |>
   [leon3mp.ucf(160)]: NET "genio(19)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(160)]:
   NET "genio(19)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(2)" LOC = "n6" |>
   [leon3mp.ucf(161)]: NET "genio(2)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(161)]:
   NET "genio(2)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(20)" LOC = "d22" |>
   [leon3mp.ucf(162)]: NET "genio(20)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(162)]:
   NET "genio(20)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(21)" LOC = "g17" |>
   [leon3mp.ucf(163)]: NET "genio(21)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(163)]:
   NET "genio(21)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(22)" LOC = "e21" |>
   [leon3mp.ucf(164)]: NET "genio(22)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(164)]:
   NET "genio(22)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(23)" LOC = "g22" |>
   [leon3mp.ucf(165)]: NET "genio(23)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(165)]:
   NET "genio(23)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(24)" LOC = "g21" |>
   [leon3mp.ucf(166)]: NET "genio(24)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(166)]:
   NET "genio(24)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(25)" LOC = "g19" |>
   [leon3mp.ucf(167)]: NET "genio(25)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(167)]:
   NET "genio(25)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(26)" LOC = "h22" |>
   [leon3mp.ucf(168)]: NET "genio(26)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(168)]:
   NET "genio(26)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(27)" LOC = "g18" |>
   [leon3mp.ucf(169)]: NET "genio(27)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(169)]:
   NET "genio(27)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(28)" LOC = "j18" |>
   [leon3mp.ucf(170)]: NET "genio(28)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(170)]:
   NET "genio(28)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(29)" LOC = "j21" |>
   [leon3mp.ucf(171)]: NET "genio(29)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(171)]:
   NET "genio(29)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(3)" LOC = "n5" |>
   [leon3mp.ucf(172)]: NET "genio(3)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(172)]:
   NET "genio(3)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(30)" LOC = "j22" |>
   [leon3mp.ucf(173)]: NET "genio(30)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(173)]:
   NET "genio(30)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(31)" LOC = "h21" |>
   [leon3mp.ucf(174)]: NET "genio(31)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(174)]:
   NET "genio(31)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(32)" LOC = "k22" |>
   [leon3mp.ucf(175)]: NET "genio(32)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(175)]:
   NET "genio(32)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(33)" LOC = "k21" |>
   [leon3mp.ucf(176)]: NET "genio(33)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(176)]:
   NET "genio(33)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(34)" LOC = "k18" |>
   [leon3mp.ucf(177)]: NET "genio(34)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(177)]:
   NET "genio(34)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(35)" LOC = "l19" |>
   [leon3mp.ucf(178)]: NET "genio(35)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(178)]:
   NET "genio(35)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(36)" LOC = "l18" |>
   [leon3mp.ucf(179)]: NET "genio(36)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(179)]:
   NET "genio(36)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(37)" LOC = "k17" |>
   [leon3mp.ucf(180)]: NET "genio(37)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(180)]:
   NET "genio(37)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(38)" LOC = "l17" |>
   [leon3mp.ucf(181)]: NET "genio(38)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(181)]:
   NET "genio(38)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(39)" LOC = "j17" |>
   [leon3mp.ucf(182)]: NET "genio(39)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(182)]:
   NET "genio(39)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(4)" LOC = "r5" |>
   [leon3mp.ucf(183)]: NET "genio(4)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(183)]:
   NET "genio(4)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(40)" LOC = "e19" |>
   [leon3mp.ucf(184)]: NET "genio(40)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(184)]:
   NET "genio(40)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(41)" LOC = "f18" |>
   [leon3mp.ucf(185)]: NET "genio(41)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(185)]:
   NET "genio(41)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(42)" LOC = "e20" |>
   [leon3mp.ucf(186)]: NET "genio(42)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(186)]:
   NET "genio(42)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(43)" LOC = "f19" |>
   [leon3mp.ucf(187)]: NET "genio(43)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(187)]:
   NET "genio(43)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(44)" LOC = "f20" |>
   [leon3mp.ucf(188)]: NET "genio(44)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(188)]:
   NET "genio(44)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(45)" LOC = "f21" |>
   [leon3mp.ucf(189)]: NET "genio(45)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(189)]:
   NET "genio(45)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(46)" LOC = "e22" |>
   [leon3mp.ucf(190)]: NET "genio(46)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(190)]:
   NET "genio(46)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(47)" LOC = "e18" |>
   [leon3mp.ucf(191)]: NET "genio(47)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(191)]:
   NET "genio(47)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(48)" LOC = "g20" |>
   [leon3mp.ucf(192)]: NET "genio(48)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(192)]:
   NET "genio(48)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(49)" LOC = "h19" |>
   [leon3mp.ucf(193)]: NET "genio(49)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(193)]:
   NET "genio(49)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(5)" LOC = "p6" |>
   [leon3mp.ucf(194)]: NET "genio(5)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(194)]:
   NET "genio(5)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(50)" LOC = "h18" |>
   [leon3mp.ucf(195)]: NET "genio(50)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(195)]:
   NET "genio(50)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(51)" LOC = "j19" |>
   [leon3mp.ucf(196)]: NET "genio(51)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(196)]:
   NET "genio(51)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(52)" LOC = "k20" |>
   [leon3mp.ucf(197)]: NET "genio(52)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(197)]:
   NET "genio(52)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(53)" LOC = "k19" |>
   [leon3mp.ucf(198)]: NET "genio(53)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(198)]:
   NET "genio(53)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(54)" LOC = "l20" |>
   [leon3mp.ucf(199)]: NET "genio(54)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(199)]:
   NET "genio(54)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(55)" LOC = "l21" |>
   [leon3mp.ucf(200)]: NET "genio(55)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(200)]:
   NET "genio(55)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(56)" LOC = "m20" |>
   [leon3mp.ucf(201)]: NET "genio(56)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(201)]:
   NET "genio(56)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(57)" LOC = "m19" |>
   [leon3mp.ucf(202)]: NET "genio(57)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(202)]:
   NET "genio(57)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(58)" LOC = "m22" |>
   [leon3mp.ucf(203)]: NET "genio(58)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(203)]:
   NET "genio(58)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(59)" LOC = "m21" |>
   [leon3mp.ucf(204)]: NET "genio(59)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(204)]:
   NET "genio(59)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(6)" LOC = "t2" |>
   [leon3mp.ucf(205)]: NET "genio(6)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(205)]:
   NET "genio(6)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(7)" LOC = "t1" |>
   [leon3mp.ucf(206)]: NET "genio(7)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(206)]:
   NET "genio(7)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(8)" LOC = "u4" |>
   [leon3mp.ucf(207)]: NET "genio(8)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(207)]:
   NET "genio(8)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "genio(9)" LOC = "t4" |>
   [leon3mp.ucf(208)]: NET "genio(9)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(208)]:
   NET "genio(9)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "switch(0)" LOC = "f16" |>
   [leon3mp.ucf(318)]: NET "switch(0)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(318)]:
   NET "switch(0)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "switch(1)" LOC = "f13" |>
   [leon3mp.ucf(319)]: NET "switch(1)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(319)]:
   NET "switch(1)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "switch(2)" LOC = "f12" |>
   [leon3mp.ucf(322)]: NET "switch(2)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(322)]:
   NET "switch(2)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "switch(3)" LOC = "e16" |>
   [leon3mp.ucf(323)]: NET "switch(3)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(323)]:
   NET "switch(3)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "switch(4)" LOC = "c22" |>
   [leon3mp.ucf(324)]: NET "switch(4)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(324)]:
   NET "switch(4)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "switch(5)" LOC = "c20" |>
   [leon3mp.ucf(325)]: NET "switch(5)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(325)]:
   NET "switch(5)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "switch(6)" LOC = "c21" |>
   [leon3mp.ucf(326)]: NET "switch(6)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(326)]:
   NET "switch(6)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "switch(8)" LOC = "d19" |>
   [leon3mp.ucf(328)]: NET "switch(8)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(328)]:
   NET "switch(8)" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "usb_clock" LOC = "b12" |>
   [leon3mp.ucf(333)]: NET "usb_clock" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(333)]:
   NET "usb_clock" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "usb_enablen" LOC = "b18" |>
   [leon3mp.ucf(350)]: NET "usb_enablen" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(350)]:
   NET "usb_enablen" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "usb_faultn" LOC = "c19" |>
   [leon3mp.ucf(351)]: NET "usb_faultn" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(351)]:
   NET "usb_faultn" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "vid_sda" LOC = "a3" |>
   [leon3mp.ucf(394)]: NET "vid_sda" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(394)]:
   NET "vid_sda" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "vid_sdc" LOC = "a9" |>
   [leon3mp.ucf(395)]: NET "vid_sdc" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(395)]:
   NET "vid_sdc" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <NET "ata_dasp"     LOC = "j17" |>
   [leon3mp.ucf(436)]: NET "ata_dasp" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

INFO:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL;> [leon3mp.ucf(436)]:
   NET "ata_dasp" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

Done...

Checking expanded design ...
WARNING:NgdBuild:470 - bidirect pad net 'usb_d(4)' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'usb_d(5)' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'usb_d(6)' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'usb_d(7)' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'usb_d(10)' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'usb_d(8)' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'usb_d(11)' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'usb_d(9)' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'usb_d(12)' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'ata_data(0)' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'usb_d(13)' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'ata_data(1)' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'usb_d(14)' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'ata_data(2)' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'usb_d(15)' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'ata_data(3)' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'ata_data(4)' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'ata_data(5)' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'ata_data(6)' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'ata_data(7)' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'ata_data(8)' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'ata_data(9)' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'emdio' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'ata_data(10)' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'ata_data(11)' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'ata_data(12)' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'ata_data(13)' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'ata_data(14)' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'ata_data(15)' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'usb_validh' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'usb_d(0)' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'usb_d(1)' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'usb_d(2)' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'usb_d(3)' has no legal driver

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  34

Writing NGD file "leon3mp.ngd" ...
Total REAL time to NGDBUILD completion:  7 sec
Total CPU time to NGDBUILD completion:   7 sec

Writing NGDBUILD log file "leon3mp.bld"...

NGDBUILD done.
map -pr b -p xc3s1500-fg456-4 leon3mp
Release 11.1 - Map L.33 (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
Using target part "3s1500fg456-4".
WARNING:LIT:243 - Logical network clk50 has no load.
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 73
   more times for the following (max. 5 shown):
   spw_clk,
   usb_d(4)_IBUF,
   usb_d(5)_IBUF,
   usb_d(6)_IBUF,
   usb_d(7)_IBUF
   To see the details of these warning messages, please use the -detail switch.
Mapping design into LUTs...
WARNING:MapLib:160 - Cannot push net timing constraints on signal clk3 through
   input buffer. Timing constraints on that signal will be lost.
WARNING:MapLib:701 - Signal clk3 connected to top level port clk3 has been
   removed.
WARNING:MapLib:701 - Signal wdogn connected to top level port wdogn has been
   removed.
WARNING:MapLib:701 - Signal ps2data(1) connected to top level port ps2data(1)
   has been removed.
WARNING:MapLib:701 - Signal ps2clk(1) connected to top level port ps2clk(1) has
   been removed.
WARNING:MapLib:701 - Signal ps2data(0) connected to top level port ps2data(0)
   has been removed.
WARNING:MapLib:701 - Signal ps2clk(0) connected to top level port ps2clk(0) has
   been removed.
WARNING:MapLib:39 - The timing specification "PERIOD=40000 pS HIGH 50%" on net
   "clk3" has been discarded, because the net was optimized out of the design.
Writing file leon3mp.ngm...
Running directed packing...
WARNING:Pack:1542 - The register mctrl0/r.bdrive_1_5 has the property IOB=TRUE,
   but was not packed into the output side of an I/O component. Register
   mctrl0/r.bdrive_1_5 set/reset disagrees with another register in the I/O
   component.
WARNING:Pack:1542 - The register mctrl0/r.bdrive_1_6 has the property IOB=TRUE,
   but was not packed into the output side of an I/O component. Register
   mctrl0/r.bdrive_1_6 set/reset disagrees with another register in the I/O
   component.
WARNING:Pack:1542 - The register mctrl0/r.bdrive_0_7 has the property IOB=TRUE,
   but was not packed into the output side of an I/O component. Register
   mctrl0/r.bdrive_0_7 set/reset disagrees with another register in the I/O
   component.
WARNING:Pack:1542 - The register mctrl0/r.bdrive_1_7 has the property IOB=TRUE,
   but was not packed into the output side of an I/O component. Register
   mctrl0/r.bdrive_1_7 set/reset disagrees with another register in the I/O
   component.
WARNING:Pack:1542 - The register mctrl0/r.bdrive_0_8 has the property IOB=TRUE,
   but was not packed into the output side of an I/O component. Register
   mctrl0/r.bdrive_0_8 set/reset disagrees with another register in the I/O
   component.
WARNING:Pack:1542 - The register mctrl0/r.bdrive_1_8 has the property IOB=TRUE,
   but was not packed into the output side of an I/O component. Register
   mctrl0/r.bdrive_1_8 set/reset disagrees with another register in the I/O
   component.
WARNING:Pack:1542 - The register mctrl0/r.bdrive_0_1 has the property IOB=TRUE,
   but was not packed into the output side of an I/O component. Register
   mctrl0/r.bdrive_0_1 set/reset disagrees with another register in the I/O
   component.
WARNING:Pack:1542 - The register mctrl0/r.bdrive_1_1 has the property IOB=TRUE,
   but was not packed into the output side of an I/O component. Register
   mctrl0/r.bdrive_1_1 set/reset disagrees with another register in the I/O
   component.
WARNING:Pack:1542 - The register mctrl0/r.bdrive_0_2 has the property IOB=TRUE,
   but was not packed into the output side of an I/O component. Register
   mctrl0/r.bdrive_0_2 set/reset disagrees with another register in the I/O
   component.
WARNING:Pack:1542 - The register mctrl0/r.bdrive_1_2 has the property IOB=TRUE,
   but was not packed into the output side of an I/O component. Register
   mctrl0/r.bdrive_1_2 set/reset disagrees with another register in the I/O
   component.
WARNING:Pack:1542 - The register mctrl0/r.bdrive_0_3 has the property IOB=TRUE,
   but was not packed into the output side of an I/O component. Register
   mctrl0/r.bdrive_0_3 set/reset disagrees with another register in the I/O
   component.
WARNING:Pack:1542 - The register mctrl0/r.bdrive_1_3 has the property IOB=TRUE,
   but was not packed into the output side of an I/O component. Register
   mctrl0/r.bdrive_1_3 set/reset disagrees with another register in the I/O
   component.
WARNING:Pack:1542 - The register mctrl0/r.bdrive_0_4 has the property IOB=TRUE,
   but was not packed into the output side of an I/O component. Register
   mctrl0/r.bdrive_0_4 set/reset disagrees with another register in the I/O
   component.
WARNING:Pack:1542 - The register mctrl0/r.bdrive_1_4 has the property IOB=TRUE,
   but was not packed into the output side of an I/O component. Register
   mctrl0/r.bdrive_1_4 set/reset disagrees with another register in the I/O
   component.
WARNING:Pack:1542 - The register mctrl0/r.bdrive_0_5 has the property IOB=TRUE,
   but was not packed into the output side of an I/O component. Register
   mctrl0/r.bdrive_0_5 set/reset disagrees with another register in the I/O
   component.
WARNING:Pack:1542 - The register mctrl0/r.bdrive_0_6 has the property IOB=TRUE,
   but was not packed into the output side of an I/O component. Register
   mctrl0/r.bdrive_0_6 set/reset disagrees with another register in the I/O
   component.
WARNING:Pack:1542 - The register l3.dsugen.dsu0/x0/r.act has the property
   IOB=TRUE, but was not packed into the output side of an I/O component. The
   register symbol l3.dsugen.dsu0/x0/r.act has no connections inside the I/O
   component.
Running delay-based LUT packing...
Running related packing...
Updating timing models...
Writing design file "leon3mp.ncd"...
WARNING:Pack:1375 - STEPPING Levels are not supported for this device.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   l3.cpu[0].u0/p0/mips/E1/iRF_stage/i_pc_gen/branch_cmp_eq0000 is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:368 - The signal <usb_xcvrsel_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:367 - The signal <usb_rxactive_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <usb_rxerror_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <usb_rxvalid_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:368 - The signal <usb_suspend_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:367 - The signal <usb_txready_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:368 - The signal <usb_txvalid_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:367 - The signal <spw_rxdn(0)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <spw_rxdn(1)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <spw_rxdn(2)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <spw_rxdp(0)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <spw_rxdp(1)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <spw_rxdp(2)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:368 - The signal <emdc_OBUF> is incomplete. The signal
   is not driven by any source pin in the design.
WARNING:PhysDesignRules:368 - The signal <ata_da(0)_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:368 - The signal <ata_da(1)_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:368 - The signal <ata_da(2)_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:368 - The signal <spw_txdn(0)_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:368 - The signal <spw_txdn(1)_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:368 - The signal <spw_txdn(2)_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:368 - The signal <spw_txdp(0)_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:368 - The signal <spw_txdp(1)_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:368 - The signal <spw_txdp(2)_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:367 - The signal <spw_rxsn(0)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <spw_rxsn(1)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <spw_rxsn(2)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <spw_rxsp(0)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <spw_rxsp(1)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <spw_rxsp(2)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:368 - The signal <spw_txsn(0)_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:368 - The signal <spw_txsn(1)_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:368 - The signal <spw_txsn(2)_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:368 - The signal <spw_txsp(0)_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:368 - The signal <spw_txsp(1)_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:368 - The signal <spw_txsp(2)_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:368 - The signal <ata_dmack_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:367 - The signal <ata_dmarq_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ata_iordy_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ata_intrq_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:368 - The signal <ata_cs0_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:368 - The signal <ata_cs1_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:367 - The signal <erxd(0)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <erxd(1)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <erxd(2)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <erxd(3)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:368 - The signal <etxd(0)_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:368 - The signal <etxd(1)_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:368 - The signal <etxd(2)_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:368 - The signal <etxd(3)_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:367 - The signal <emdio_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ctsn2_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <erx_clk_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <erx_col_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <erx_crs_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <etx_clk_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <usb_linestate(0)_IBUF> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <usb_linestate(1)_IBUF> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <usb_clkout_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <usb_validh_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:368 - The signal <ata_dior_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:368 - The signal <ata_diow_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:368 - The signal <ata_csel_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:367 - The signal <ata_data(10)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ata_data(11)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ata_data(12)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ata_data(13)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ata_data(14)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ata_data(15)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:368 - The signal <ata_rstn_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:367 - The signal <usb_d(10)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <usb_d(11)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <usb_d(12)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <usb_d(13)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <usb_d(14)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <usb_d(15)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <erx_er_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <erx_dv_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:368 - The signal <etx_en_OBUF> is incomplete. The signal
   is not driven by any source pin in the design.
WARNING:PhysDesignRules:368 - The signal <etx_er_OBUF> is incomplete. The signal
   is not driven by any source pin in the design.
WARNING:PhysDesignRules:368 - The signal <usb_reset_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:367 - The signal <ata_data(0)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ata_data(1)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ata_data(2)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ata_data(3)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ata_data(4)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ata_data(5)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ata_data(6)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ata_data(7)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ata_data(8)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ata_data(9)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <usb_d(0)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <usb_d(1)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <usb_d(2)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <usb_d(3)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <usb_d(4)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <usb_d(5)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <usb_d(6)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <usb_d(7)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <usb_d(8)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <usb_d(9)_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <usb_vbus_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:368 - The signal <usb_opmode(0)_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:368 - The signal <usb_opmode(1)_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:368 - The signal <usb_termsel_OBUF> is incomplete. The
   signal is not driven by any source pin in the design.
WARNING:PhysDesignRules:812 - Dangling pin <DOB0> on
   block:<l3.cpu[0].u0/cmem0/ime.im0[0].itags0/xc2v.x0/a8.x[0].r0.B>:<RAMB16_RAM
   B16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB1> on
   block:<l3.cpu[0].u0/cmem0/ime.im0[0].itags0/xc2v.x0/a8.x[0].r0.B>:<RAMB16_RAM
   B16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB2> on
   block:<l3.cpu[0].u0/cmem0/ime.im0[0].itags0/xc2v.x0/a8.x[0].r0.B>:<RAMB16_RAM
   B16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB3> on
   block:<l3.cpu[0].u0/cmem0/ime.im0[0].itags0/xc2v.x0/a8.x[0].r0.B>:<RAMB16_RAM
   B16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB4> on
   block:<l3.cpu[0].u0/cmem0/ime.im0[0].itags0/xc2v.x0/a8.x[0].r0.B>:<RAMB16_RAM
   B16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB5> on
   block:<l3.cpu[0].u0/cmem0/ime.im0[0].itags0/xc2v.x0/a8.x[0].r0.B>:<RAMB16_RAM
   B16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB6> on
   block:<l3.cpu[0].u0/cmem0/ime.im0[0].itags0/xc2v.x0/a8.x[0].r0.B>:<RAMB16_RAM
   B16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB7> on
   block:<l3.cpu[0].u0/cmem0/ime.im0[0].itags0/xc2v.x0/a8.x[0].r0.B>:<RAMB16_RAM
   B16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB28> on
   block:<l3.cpu[0].u0/cmem0/ime.im0[0].itags0/xc2v.x0/a8.x[0].r0.B>:<RAMB16_RAM
   B16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB29> on
   block:<l3.cpu[0].u0/cmem0/ime.im0[0].itags0/xc2v.x0/a8.x[0].r0.B>:<RAMB16_RAM
   B16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB30> on
   block:<l3.cpu[0].u0/cmem0/ime.im0[0].itags0/xc2v.x0/a8.x[0].r0.B>:<RAMB16_RAM
   B16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB31> on
   block:<l3.cpu[0].u0/cmem0/ime.im0[0].itags0/xc2v.x0/a8.x[0].r0.B>:<RAMB16_RAM
   B16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB0> on
   block:<l3.cpu[0].u0/cmem0/ime.im0[1].itags0/xc2v.x0/a8.x[0].r0.B>:<RAMB16_RAM
   B16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB1> on
   block:<l3.cpu[0].u0/cmem0/ime.im0[1].itags0/xc2v.x0/a8.x[0].r0.B>:<RAMB16_RAM
   B16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB2> on
   block:<l3.cpu[0].u0/cmem0/ime.im0[1].itags0/xc2v.x0/a8.x[0].r0.B>:<RAMB16_RAM
   B16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB3> on
   block:<l3.cpu[0].u0/cmem0/ime.im0[1].itags0/xc2v.x0/a8.x[0].r0.B>:<RAMB16_RAM
   B16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB4> on
   block:<l3.cpu[0].u0/cmem0/ime.im0[1].itags0/xc2v.x0/a8.x[0].r0.B>:<RAMB16_RAM
   B16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB5> on
   block:<l3.cpu[0].u0/cmem0/ime.im0[1].itags0/xc2v.x0/a8.x[0].r0.B>:<RAMB16_RAM
   B16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB6> on
   block:<l3.cpu[0].u0/cmem0/ime.im0[1].itags0/xc2v.x0/a8.x[0].r0.B>:<RAMB16_RAM
   B16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB7> on
   block:<l3.cpu[0].u0/cmem0/ime.im0[1].itags0/xc2v.x0/a8.x[0].r0.B>:<RAMB16_RAM
   B16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB28> on
   block:<l3.cpu[0].u0/cmem0/ime.im0[1].itags0/xc2v.x0/a8.x[0].r0.B>:<RAMB16_RAM
   B16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB29> on
   block:<l3.cpu[0].u0/cmem0/ime.im0[1].itags0/xc2v.x0/a8.x[0].r0.B>:<RAMB16_RAM
   B16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB30> on
   block:<l3.cpu[0].u0/cmem0/ime.im0[1].itags0/xc2v.x0/a8.x[0].r0.B>:<RAMB16_RAM
   B16B>.
WARNING:PhysDesignRules:812 - Dangling pin <DOB31> on
   block:<l3.cpu[0].u0/cmem0/ime.im0[1].itags0/xc2v.x0/a8.x[0].r0.B>:<RAMB16_RAM
   B16B>.
WARNING:PhysDesignRules:1054 - The DCM comp clkgen0/xc3s.v/dll0 is configured
   with CLK2X to CLKFB programming. Feedback of the CLK2X signal may not be
   supported on some Spartan 3 silicon. Please check the Spartan 3 Errata for
   details.

Design Summary:
Number of errors:      0
Number of warnings:  158
Logic Utilization:
  Total Number Slice Registers:       2,096 out of  26,624    7%
    Number used as Flip Flops:        2,095
    Number used as Latches:               1
  Number of 4 input LUTs:             8,241 out of  26,624   30%
Logic Distribution:
  Number of occupied Slices:          4,741 out of  13,312   35%
    Number of Slices containing only related logic:   4,741 out of   4,741 100%
    Number of Slices containing unrelated logic:          0 out of   4,741   0%
      *See NOTES below for an explanation of the effects of unrelated logic.
  Total Number of 4 input LUTs:       8,414 out of  26,624   31%
    Number used as logic:             8,238
    Number used as a route-thru:        173
    Number used as Shift registers:       3

  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

  Number of bonded IOBs:                257 out of     333   77%
    IOB Flip Flops:                     198
  Number of RAMB16s:                     10 out of      32   31%
  Number of BUFGMUXs:                     2 out of       8   25%
  Number of DCMs:                         2 out of       4   50%
  Number of BSCANs:                       1 out of       1  100%

Average Fanout of Non-Clock Nets:                3.68

Peak Memory Usage:  247 MB
Total REAL time to MAP completion:  15 secs 
Total CPU time to MAP completion:   12 secs 

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "leon3mp.mrp" for details.
par -ol high -w leon3mp leon3mp.ncd
Release 11.1 - par L.33 (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.



Constraints file: leon3mp.pcf.
Loading device for application Rf_Device from file '3s1500.nph' in environment c:\Xilinx\11.1\ISE.
   "leon3mp" is an NCD, version 3.2, device xc3s1500, package fg456, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

WARNING:Timing:3224 - The clock erx_clk associated with OFFSET = IN 10 ns BEFORE COMP "erx_clk"; does not clock any
   registered input components.
WARNING:Timing:3225 - Timing constraint OFFSET = IN 10 ns BEFORE COMP "erx_clk"; ignored during timing analysis
WARNING:Timing:3224 - The clock etx_clk associated with OFFSET = OUT 20 ns AFTER COMP "etx_clk"; does not clock any
   registered output components.
WARNING:Timing:3225 - Timing constraint OFFSET = OUT 20 ns AFTER COMP "etx_clk"; ignored during timing analysis
WARNING:Timing:3224 - The clock etx_clk associated with OFFSET = IN 10 ns BEFORE COMP "etx_clk"; does not clock any
   registered input components.
WARNING:Timing:3225 - Timing constraint OFFSET = IN 10 ns BEFORE COMP "etx_clk"; ignored during timing analysis
WARNING:Timing:3224 - The clock usb_clkout associated with OFFSET = OUT 10 ns AFTER COMP "usb_clkout"; does not clock
   any registered output components.
WARNING:Timing:3225 - Timing constraint OFFSET = OUT 10 ns AFTER COMP "usb_clkout"; ignored during timing analysis
WARNING:Timing:3224 - The clock usb_clkout associated with OFFSET = IN 8 ns BEFORE COMP "usb_clkout"; does not clock any
   registered input components.
WARNING:Timing:3225 - Timing constraint OFFSET = IN 8 ns BEFORE COMP "usb_clkout"; ignored during timing analysis

Device speed data version:  "PRODUCTION 1.39 2009-03-03".


Device Utilization Summary:

   Number of BSCANs                          1 out of 1     100%
   Number of BUFGMUXs                        2 out of 8      25%
   Number of DCMs                            2 out of 4      50%
      Number of LOCed DCMs                   2 out of 2     100%

   Number of External IOBs                 257 out of 333    77%
      Number of LOCed IOBs                 257 out of 257   100%

   Number of RAMB16s                        10 out of 32     31%
   Number of Slices                       4741 out of 13312  35%
      Number of SLICEMs                     47 out of 6656    1%



Overall effort level (-ol):   High 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    High 

Starting initial Timing Analysis.  REAL time: 5 secs 
Finished initial Timing Analysis.  REAL time: 6 secs 

WARNING:Par:289 - The signal usb_xcvrsel_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal usb_rxactive_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal usb_rxerror_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal usb_rxvalid_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal usb_suspend_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal usb_txready_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal usb_txvalid_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal spw_rxdn(0)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal spw_rxdn(1)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal spw_rxdn(2)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal spw_rxdp(0)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal spw_rxdp(1)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal spw_rxdp(2)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal emdc_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal ata_da(0)_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal ata_da(1)_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal ata_da(2)_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal spw_txdn(0)_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal spw_txdn(1)_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal spw_txdn(2)_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal spw_txdp(0)_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal spw_txdp(1)_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal spw_txdp(2)_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal spw_rxsn(0)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal spw_rxsn(1)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal spw_rxsn(2)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal spw_rxsp(0)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal spw_rxsp(1)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal spw_rxsp(2)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal spw_txsn(0)_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal spw_txsn(1)_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal spw_txsn(2)_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal spw_txsp(0)_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal spw_txsp(1)_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal spw_txsp(2)_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal ata_dmack_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal ata_dmarq_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal ata_iordy_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal ata_intrq_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal ata_cs0_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal ata_cs1_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal erxd(0)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal erxd(1)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal erxd(2)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal erxd(3)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal etxd(0)_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal etxd(1)_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal etxd(2)_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal etxd(3)_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal emdio_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal ctsn2_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal erx_clk_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal erx_col_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal erx_crs_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal etx_clk_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal usb_linestate(0)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal usb_linestate(1)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal usb_clkout_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal usb_validh_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal ata_dior_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal ata_diow_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal ata_csel_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal ata_data(10)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal ata_data(11)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal ata_data(12)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal ata_data(13)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal ata_data(14)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal ata_data(15)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal ata_rstn_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal usb_d(10)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal usb_d(11)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal usb_d(12)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal usb_d(13)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal usb_d(14)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal usb_d(15)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal erx_er_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal erx_dv_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal etx_en_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal etx_er_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal usb_reset_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal ata_data(0)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal ata_data(1)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal ata_data(2)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal ata_data(3)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal ata_data(4)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal ata_data(5)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal ata_data(6)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal ata_data(7)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal ata_data(8)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal ata_data(9)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal usb_d(0)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal usb_d(1)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal usb_d(2)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal usb_d(3)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal usb_d(4)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal usb_d(5)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal usb_d(6)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal usb_d(7)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal usb_d(8)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal usb_d(9)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal usb_vbus_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal usb_opmode(0)_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal usb_opmode(1)_OBUF has no driver.  PAR will not attempt to route this signal.
WARNING:Par:289 - The signal usb_termsel_OBUF has no driver.  PAR will not attempt to route this signal.

Starting Placer
Total REAL time at the beginning of Placer: 6 secs 
Total CPU  time at the beginning of Placer: 6 secs 

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:2ec84053) REAL time: 8 secs 

Phase 2.7  Design Feasibility Check
Phase 2.7  Design Feasibility Check (Checksum:2ec84053) REAL time: 8 secs 

Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:df2f4153) REAL time: 8 secs 

Phase 4.2  Initial Clock and IO Placement

Phase 4.2  Initial Clock and IO Placement (Checksum:ab3a93db) REAL time: 9 secs 

Phase 5.8  Global Placement
...........................
..................................
..........
......................................................
...............
.................
........
...............................
Phase 5.8  Global Placement (Checksum:8373cefc) REAL time: 31 secs 

Phase 6.5  Local Placement Optimization
Phase 6.5  Local Placement Optimization (Checksum:8373cefc) REAL time: 31 secs 

Phase 7.18  Placement Optimization
Phase 7.18  Placement Optimization (Checksum:77abaa7e) REAL time: 42 secs 

Phase 8.5  Local Placement Optimization
Phase 8.5  Local Placement Optimization (Checksum:77abaa7e) REAL time: 42 secs 

Total REAL time to Placer completion: 43 secs 
Total CPU  time to Placer completion: 42 secs 
Writing design to file leon3mp.ncd



Starting Router


Phase  1  : 35132 unrouted;      REAL time: 46 secs 

Phase  2  : 33118 unrouted;      REAL time: 48 secs 

Phase  3  : 10375 unrouted;      REAL time: 54 secs 

Phase  4  : 10400 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 57 secs 

Phase  5  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 1 mins 10 secs 

Updating file: leon3mp.ncd with current fully routed design.

Phase  6  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 1 mins 15 secs 

Phase  7  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 1 mins 16 secs 

Phase  8  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 1 mins 21 secs 
WARNING:Route:455 - CLK Net:clkm may have excessive skew because 
      0 CLK pins and 1 NON_CLK pins failed to route using a CLK template.

Total REAL time to Router completion: 1 mins 21 secs 
Total CPU time to Router completion: 1 mins 18 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|                clkm |      BUFGMUX3| No   | 1837 |  0.609     |  1.349      |
+---------------------+--------------+------+------+------------+-------------+
|l3.cpu[0].u0/p0/mips |              |      |      |            |             |
|/E1/iRF_stage/i_pc_g |              |      |      |            |             |
|en/branch_cmp_eq0000 |              |      |      |            |             |
|                     |         Local|      |    1 |  0.000     |  1.128      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)

Number of Timing Constraints that were not applied: 9

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                            |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
  PERIOD analysis for net "clkgen0/xc3s.v/c | SETUP       |     0.197ns|    24.803ns|       0|           0
  lk0B" derived from  NET "lclk" PERIOD = 2 | HOLD        |     0.800ns|            |       0|           0
  0 ns HIGH 50%                             |             |            |            |        |            
------------------------------------------------------------------------------------------------------
  OFFSET = IN 8 ns BEFORE COMP "clk"        | SETUP       |     5.030ns|     2.970ns|       0|           0
------------------------------------------------------------------------------------------------------
  NET "lclk" PERIOD = 20 ns HIGH 50%        | MINLOWPULSE |    14.000ns|     6.000ns|       0|           0
------------------------------------------------------------------------------------------------------
  OFFSET = OUT 20 ns AFTER COMP "clk"       | MAXDELAY    |     9.011ns|    10.989ns|       0|           0
------------------------------------------------------------------------------------------------------
  NET "usb_clkout_IBUF" PERIOD = 16.667 ns  | N/A         |         N/A|         N/A|     N/A|         N/A
  HIGH 50%                                  |             |            |            |        |            
------------------------------------------------------------------------------------------------------
  NET "erx_clk_IBUF" PERIOD = 40 ns HIGH 50 | N/A         |         N/A|         N/A|     N/A|         N/A
  %                                         |             |            |            |        |            
------------------------------------------------------------------------------------------------------
  NET "etx_clk_IBUF" PERIOD = 40 ns HIGH 50 | N/A         |         N/A|         N/A|     N/A|         N/A
  %                                         |             |            |            |        |            
------------------------------------------------------------------------------------------------------
  OFFSET = IN 10 ns BEFORE COMP "erx_clk"   | N/A         |         N/A|         N/A|     N/A|         N/A
------------------------------------------------------------------------------------------------------
  OFFSET = OUT 20 ns AFTER COMP "etx_clk"   | N/A         |         N/A|         N/A|     N/A|         N/A
------------------------------------------------------------------------------------------------------
  OFFSET = IN 10 ns BEFORE COMP "etx_clk"   | N/A         |         N/A|         N/A|     N/A|         N/A
------------------------------------------------------------------------------------------------------
  OFFSET = OUT 10 ns AFTER COMP "usb_clkout | N/A         |         N/A|         N/A|     N/A|         N/A
  "                                         |             |            |            |        |            
------------------------------------------------------------------------------------------------------
  OFFSET = IN 8 ns BEFORE COMP "usb_clkout" | N/A         |         N/A|         N/A|     N/A|         N/A
------------------------------------------------------------------------------------------------------


Derived Constraint Report
Derived Constraints for lclk
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|lclk                           |     20.000ns|      6.000ns|     19.842ns|            0|            0|            0|     17167694|
| clkgen0/xc3s.v/clk0B          |     25.000ns|     24.803ns|          N/A|            0|            0|     17167694|            0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the 
   constraint does not cover any paths or that it has no requested value.


Generating Pad Report.

All signals are completely routed.

WARNING:Par:283 - There are 68 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

WARNING:Par:284 - There are 36 sourceless signals in this design. This design will not pass the DRC check run by Bitgen.

Total REAL time to PAR completion: 1 mins 25 secs 
Total CPU time to PAR completion: 1 mins 22 secs 

Peak Memory Usage:  333 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 119
Number of info messages: 0

Writing design to file leon3mp.ncd



PAR done!
trce -v 25 leon3mp.ncd leon3mp.pcf
Release 11.1 - Trace  (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.


Loading device for application Rf_Device from file '3s1500.nph' in environment
c:\Xilinx\11.1\ISE.
   "leon3mp" is an NCD, version 3.2, device xc3s1500, package fg456, speed -4
WARNING:Timing:3224 - The clock erx_clk associated with OFFSET = IN 10 ns BEFORE
   COMP "erx_clk"; does not clock any registered input components.
WARNING:Timing:3225 - Timing constraint OFFSET = IN 10 ns BEFORE COMP "erx_clk";
   ignored during timing analysis
WARNING:Timing:3224 - The clock etx_clk associated with OFFSET = OUT 20 ns AFTER
   COMP "etx_clk"; does not clock any registered output components.
WARNING:Timing:3225 - Timing constraint OFFSET = OUT 20 ns AFTER COMP "etx_clk";
   ignored during timing analysis
WARNING:Timing:3224 - The clock etx_clk associated with OFFSET = IN 10 ns BEFORE
   COMP "etx_clk"; does not clock any registered input components.
WARNING:Timing:3225 - Timing constraint OFFSET = IN 10 ns BEFORE COMP "etx_clk";
   ignored during timing analysis
WARNING:Timing:3224 - The clock usb_clkout associated with OFFSET = OUT 10 ns
   AFTER COMP "usb_clkout"; does not clock any registered output components.
WARNING:Timing:3225 - Timing constraint OFFSET = OUT 10 ns AFTER COMP
   "usb_clkout"; ignored during timing analysis
WARNING:Timing:3224 - The clock usb_clkout associated with OFFSET = IN 8 ns
   BEFORE COMP "usb_clkout"; does not clock any registered input components.
WARNING:Timing:3225 - Timing constraint OFFSET = IN 8 ns BEFORE COMP
   "usb_clkout"; ignored during timing analysis
--------------------------------------------------------------------------------
Release 11.1 Trace  (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.

c:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -v 25 leon3mp.ncd leon3mp.pcf


Design file:              leon3mp.ncd
Physical constraint file: leon3mp.pcf
Device,speed:             xc3s1500,-4 (PRODUCTION 1.39 2009-03-03)
Report level:             verbose report, limited to 25 items per constraint
--------------------------------------------------------------------------------

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a
   50 Ohm transmission line loading model.  For the details of this model, and
   for more information on accounting for different loading conditions, please
   see the device datasheet.


Timing summary:
---------------

Timing errors: 0  Score: 0 (Setup/Max: 0, Hold: 0)

Constraints cover 17167909 paths, 0 nets, and 34838 connections

Design statistics:
   Minimum period:  24.803ns (Maximum frequency:  40.318MHz)
   Minimum input required time before clock:   2.970ns
   Minimum output required time after clock:  10.989ns


Analysis completed Tue Aug 18 18:40:13 2009
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 10
Number of info messages: 2
Total time: 12 secs 
bitgen leon3mp -l -m -w -d -f ../../boards/gr-xc3s-1500/default.ut
Release 11.1 - Bitgen L.33 (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
Loading device for application Rf_Device from file '3s1500.nph' in environment
c:\Xilinx\11.1\ISE.
   "leon3mp" is an NCD, version 3.2, device xc3s1500, package fg456, speed -4
Opened constraints file leon3mp.pcf.

Tue Aug 18 18:40:17 2009

INFO:Bitgen:40 - Replacing "Auto" with "NoWait" for option "Match_cycle".  Most
   commonly, bitgen has determined and will use a specific value instead of the
   generic command-line value of "Auto".  Alternately, this message appears if
   the same option is specified multiple times on the command-line.  In this
   case, the option listed last will be used.
Saving ll file in "leon3mp.ll".
Creating bit map...
Saving bit stream in "leon3mp.bit".
Saving bit stream in "leon3mp.rbt".
Saving Readback bit file leon3mp.rbb.
Saving Readback bit file leon3mp.rba.
Saving Readback golden data file leon3mp.rbd.
Saving mask data in "leon3mp.msd".
Creating bit mask...
Saving mask bit stream in "leon3mp.msk".
Bitstream generation is complete.
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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-gr-xc3s-1500/] [mips.txt] - Rev 2
