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Subversion Repositories mips_enhanced
[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-gr-xc3s-1500/] [modelsim/] [opencores/] [ac97_out_fifo/] [_primary.vhd] - Rev 2
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library verilog; use verilog.vl_types.all; entity ac97_out_fifo is port( clk : in vl_logic; rst : in vl_logic; en : in vl_logic; mode : in vl_logic_vector(1 downto 0); din : in vl_logic_vector(31 downto 0); we : in vl_logic; dout : out vl_logic_vector(19 downto 0); re : in vl_logic; status : out vl_logic_vector(1 downto 0); full : out vl_logic; empty : out vl_logic ); end ac97_out_fifo;