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//*****************************************************************************
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor		    : Xilinx
// \   \   \/    Version            : 3.6.1
//  \   \        Application	    : MIG
//  /   /        Filename	    : data_write.v
// /___/   /\    Date Last Modified : $Date: 2010/11/26 18:25:41 $
// \   \  /  \   Date Created	    : Mon May 2 2005
//  \___\/\___\
// Device	: Spartan-3/3A/3A-DSP
// Design Name	: DDR2 SDRAM
// Purpose	: Data write operation performed through the pipelines in this
//		  module.
//*****************************************************************************
 
`timescale 1ns/100ps
`include "../rtl/ddr_parameters_0.v"
 
module  ddr_data_write_0
  (
   input     [((`DATA_WIDTH*2)-1):0]  user_input_data,
   input [((`DATA_MASK_WIDTH*2)-1):0] user_data_mask,
   input                              clk90,
   input                              write_enable,
   output reg                         write_en_val,
   output [((`DATA_WIDTH)-1):0]       write_data_falling,
   output [((`DATA_WIDTH)-1):0]       write_data_rising,
   output [((`DATA_MASK_WIDTH)-1):0]  data_mask_f,
   output [((`DATA_MASK_WIDTH)-1):0]  data_mask_r
   );
 
   reg                                write_en_P1;
 
   reg [((`DATA_WIDTH*2)-1):0]        write_data1;
   reg [((`DATA_WIDTH*2)-1):0]        write_data2;
   reg [((`DATA_WIDTH*2)-1):0]        write_data3;
   reg [((`DATA_WIDTH*2)-1):0]        write_data4
   /* synthesis syn_srlstyle="registers" */;
   reg [((`DATA_MASK_WIDTH*2)-1):0]   write_data_m1;
   reg [((`DATA_MASK_WIDTH*2)-1):0]   write_data_m2;
   reg [((`DATA_MASK_WIDTH*2)-1):0]   write_data_m3;
   reg [((`DATA_MASK_WIDTH*2)-1):0]   write_data_m4;
 
   reg [(`DATA_WIDTH-1):0]            write_data90;
   reg [(`DATA_WIDTH-1):0]            write_data90_1;
   reg [(`DATA_WIDTH-1):0]            write_data90_2;
   reg [(`DATA_WIDTH-1):0]            write_data270;
   reg [(`DATA_WIDTH-1):0]            write_data270_1;
   reg [(`DATA_WIDTH-1):0]            write_data270_2;
 
   reg [(`DATA_MASK_WIDTH-1):0]       write_data_m90;
   reg [(`DATA_MASK_WIDTH-1):0]       write_data_m90_1;
   reg [(`DATA_MASK_WIDTH-1):0]       write_data_m90_2;
 
   reg [((`DATA_MASK_WIDTH)-1):0]     write_data_m270;
   reg [((`DATA_MASK_WIDTH)-1):0]     write_data_m270_1;
   reg [((`DATA_MASK_WIDTH)-1):0]     write_data_m270_2;
 
   wire [((`DATA_WIDTH*2)-1):0]       write_data0;
   wire [((`DATA_MASK_WIDTH*2)-1):0]  write_data_m0;
 
 
   assign write_data0   = user_input_data;
   assign write_data_m0 = user_data_mask;
 
   always@(posedge clk90) begin
      write_data1 <= write_data0;
      write_data2 <= write_data1;
      write_data3 <= write_data2;
      write_data4 <= write_data3;
   end
 
   always@(posedge clk90) begin
      write_data_m1 <= write_data_m0;
      write_data_m2 <= write_data_m1;
      write_data_m3 <= write_data_m2;
      write_data_m4 <= write_data_m3;
   end
 
   always@(posedge clk90) begin
      write_data90   <= write_data4[`DATA_WIDTH-1 : 0];
      write_data_m90       <= write_data_m4[`DATA_MASK_WIDTH-1:0];
      write_data90_1	  <= write_data90;
      write_data_m90_1    <= write_data_m90;
      write_data90_2	  <= write_data90_1;
      write_data_m90_2    <= write_data_m90_1;
 
   end
 
   always@ (negedge clk90) begin
      write_data270      <= write_data4[(`DATA_WIDTH*2)-1 : `DATA_WIDTH];
      write_data_m270    <= write_data_m4[(`DATA_MASK_WIDTH*2)-1:`DATA_MASK_WIDTH];
 
      write_data270_1    <= write_data270;
      write_data_m270_1  <= write_data_m270;
      write_data270_2    <= write_data270_1;
      write_data_m270_2  <= write_data_m270_1;
 
   end
 
   assign write_data_rising  = write_data270_2;
   assign write_data_falling = write_data90_2;
 
   assign data_mask_r = write_data_m270_2;
   assign data_mask_f = write_data_m90_2;
 
 
// write enable for data path
   always@(posedge clk90) begin
     write_en_P1 <= write_enable;
   end
 
   always@(negedge clk90) begin
     write_en_val   <= write_en_P1;
   end
 
endmodule