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[/] [next186_soc_pc/] [trunk/] [HW/] [ipcore_dir/] [dcm_vga.v] - Rev 2
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//////////////////////////////////////////////////////////////////////////////// // Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. //////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version : 14.5 // \ \ Application : xaw2verilog // / / Filename : dcm_vga.v // /___/ /\ Timestamp : 05/18/2013 01:02:42 // \ \ / \ // \___\/\___\ // //Command: xaw2verilog -st D:/work/xilinx/ddr_186/ddr_186/ipcore_dir/dcm_vga.xaw D:/work/xilinx/ddr_186/ddr_186/ipcore_dir/dcm_vga //Design Name: dcm_vga //Device: xc3s700an-4fgg484 // // Module dcm_vga // Generated by Xilinx Architecture Wizard // Written for synthesis tool: XST // Period Jitter (unit interval) for block DCM_SP_INST = 0.02 UI // Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.83 ns `timescale 1ns / 1ps module dcm_vga(CLKIN_IN, CLKDV_OUT, CLKFX_OUT, CLKIN_IBUFG_OUT, CLK0_OUT, CLK90_OUT, LOCKED_OUT); input CLKIN_IN; output CLKDV_OUT; output CLKFX_OUT; output CLKIN_IBUFG_OUT; output CLK0_OUT; output CLK90_OUT; output LOCKED_OUT; wire CLKDV_BUF; wire CLKFB_IN; wire CLKFX_BUF; wire CLKIN_IBUFG; wire CLK0_BUF; wire CLK90_BUF; wire GND_BIT; assign GND_BIT = 0; assign CLKIN_IBUFG_OUT = CLKIN_IBUFG; assign CLK0_OUT = CLKFB_IN; BUFG CLKDV_BUFG_INST (.I(CLKDV_BUF), .O(CLKDV_OUT)); BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF), .O(CLKFX_OUT)); IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN), .O(CLKIN_IBUFG)); BUFG CLK0_BUFG_INST (.I(CLK0_BUF), .O(CLKFB_IN)); BUFG CLK90_BUFG_INST (.I(CLK90_BUF), .O(CLK90_OUT)); DCM_SP #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(2.0), .CLKFX_DIVIDE(16), .CLKFX_MULTIPLY(3), .CLKIN_DIVIDE_BY_2("FALSE"), .CLKIN_PERIOD(7.500), .CLKOUT_PHASE_SHIFT("NONE"), .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"), .DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"), .FACTORY_JF(16'hC080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") ) DCM_SP_INST (.CLKFB(CLKFB_IN), .CLKIN(CLKIN_IBUFG), .DSSEN(GND_BIT), .PSCLK(GND_BIT), .PSEN(GND_BIT), .PSINCDEC(GND_BIT), .RST(GND_BIT), .CLKDV(CLKDV_BUF), .CLKFX(CLKFX_BUF), .CLKFX180(), .CLK0(CLK0_BUF), .CLK2X(), .CLK2X180(), .CLK90(CLK90_BUF), .CLK180(), .CLK270(), .LOCKED(LOCKED_OUT), .PSDONE(), .STATUS()); endmodule