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[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [doc/] [Terasic/] [DE0_NANO_SOC/] [Demonstrations/] [FPGA/] [my_first_fpga/] [counter_bus_mux.qip] - Rev 221
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set_global_assignment -name IP_TOOL_NAME "LPM_MUX"set_global_assignment -name IP_TOOL_VERSION "14.1"set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "counter_bus_mux.v"]set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "counter_bus_mux.bsf"]set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "counter_bus_mux_bb.v"]