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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen/] [ram_16x1k_dp/] [implement/] [implement.sh] - Rev 167
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#!/bin/sh # Clean up the results directory rm -rf results mkdir results #Synthesize the Wrapper Files echo 'Synthesizing example design with XST'; xst -ifn xst.scr cp ram_16x1k_dp_exdes.ngc ./results/ # Copy the netlist generated by Coregen echo 'Copying files from the netlist directory to the results directory' cp ../../ram_16x1k_dp.ngc results/ # Copy the constraints files generated by Coregen echo 'Copying files from constraints directory to results directory' cp ../example_design/ram_16x1k_dp_exdes.ucf results/ cd results echo 'Running ngdbuild' ngdbuild -p xc6slx9-csg324-2 ram_16x1k_dp_exdes echo 'Running map' map ram_16x1k_dp_exdes -o mapped.ncd -pr i echo 'Running par' par mapped.ncd routed.ncd echo 'Running trce' trce -e 10 routed.ncd mapped.pcf -o routed echo 'Running design through bitgen' bitgen -w routed echo 'Running netgen to create gate level Verilog model' netgen -ofmt verilog -sim -tm ram_16x1k_dp_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v