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//*****************************************************************************
//   ____  ____
//  /	/\/   /
// /___/  \  /   Vendor		    : Xilinx
// \   \   \/    Version            : 3.6.1
//  \	\        Application		: MIG
//  /	/        Filename		: s3adsp_ddr2_parameters_0.v
// /___/   /\    Date Last Modified : $Date: 2010/11/26 18:25:42 $
// \   \  /  \   Date Created	    : Mon May 2 2005
//  \___\/\___\
// Device	: Spartan-3/3A/3A-DSP
// Design Name	: DDR2 SDRAM
// Purpose	: This module has the parameters used in the design
//*****************************************************************************
 
//`timescale 1ns/100ps
 
// The reset polarity is set to active low by default. 
// You can change this by editing the parameter RESET_ACTIVE_LOW.
// Please do not change any of the other parameters directly by editing the RTL. 
// All other changes should be done through the GUI.
 
`define   DATA_WIDTH                               32
`define   DATA_STROBE_WIDTH                        4
`define   DATA_MASK_WIDTH                          4
`define   CLK_WIDTH                                2
`define   CKE_WIDTH                                1
`define   ROW_ADDRESS                              13
`define   MEMORY_WIDTH                             8
`define   REGISTERED                               0
`define   DATABITSPERSTROBE                        8
`define   RESET_PORT                               0
`define   MASK_ENABLE                              1
`define   USE_DM_PORT                              1
`define   COLUMN_ADDRESS                           10
`define   BANK_ADDRESS                             2
`define   DEBUG_EN                                 0
`define   CLK_TYPE                                 "SINGLE_ENDED"
`define   LOAD_MODE_REGISTER                       13'b0010100110011
`define   EXT_LOAD_MODE_REGISTER                   13'b0000000000000
`define   RESET_ACTIVE_LOW                         1'b1
`define   RAS_COUNT_VALUE                          5'b00101
`define   RP_COUNT_VALUE                           3'b001
`define   RFC_COUNT_VALUE                          8'b00001101
`define   TWR_COUNT_VALUE                          3'b010
`define   MAX_REF_WIDTH                            10
`define   MAX_REF_CNT                              10'b1111100111
 
`include "synthesis-defines.v"
`ifndef SYNTHESIS
// To skip the 200us wait at simulation start
 `define simulation
`endif