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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [PPC440_Xilinx_Virtex5_GCC/] [system.log] - Rev 599
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Xilinx Platform Studio (XPS)
Xilinx EDK 11.2 Build EDK_LS3.47
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line 251 - deprecated core for architecture 'virtex5fx'!
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line 296 - deprecated core for architecture 'virtex5fx'!
Generating Block Diagram to Buffer
Generated Block Diagram SVG
At Local date and time: Mon Jun 29 21:01:23 2009
make -f system.make program started...
*********************************************
Creating software libraries...
*********************************************
libgen -mhs system.mhs -p xc5vfx70tff1136-1 -msg __xps/ise/xmsgprops.lst system.mss
libgen
Xilinx EDK 11.2 Build EDK_LS3.47
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
Command Line: libgen -mhs system.mhs -p xc5vfx70tff1136-1 -msg
__xps/ise/xmsgprops.lst system.mss
Release 11.2 - psf2Edward EDK_LS3.47 (nt)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste
m.mhs line 251 - deprecated core for architecture 'virtex5fx'!
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste
m.mhs line 296 - deprecated core for architecture 'virtex5fx'!
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste
m.mhs line 251 - deprecated core for architecture 'virtex5fx'!
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste
m.mhs line 296 - deprecated core for architecture 'virtex5fx'!
Checking platform configuration ...
IPNAME:plb_v46 INSTANCE:plb_v46_0 -
C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\system.m
hs line 107 - 1 master(s) : 12 slave(s)
IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\system.m
hs line 288 - 1 master(s) : 1 slave(s)
Checking port drivers...
WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -
C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste
m.mhs line 446 - floating connection!
Performing Clock DRCs...
Performing Reset DRCs...
Overriding system level properties...
Running system level update procedures...
Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
Running system level DRCs...
Performing System level DRCs on properties...
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
WARNING:EDK:494 -
C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\synth
esis\ not found.
WARNING:EDK:2530 - Timing and Resource utilization information not added
WARNING:EDK:411 - pcie -
C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste
m.mss line 77 - deprecated driver!
WARNING:EDK:411 - emaclite -
C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste
m.mss line 83 - deprecated driver!
INFO:EDK:1740 - List of peripherals connected to processor instance ppc440_0:
- DDR2_SDRAM
- DIP_Switches_8Bit
- Ethernet_MAC
- IIC_EEPROM
- LEDs_8Bit
- LEDs_Positions
- PCIe_Bridge
- Push_Buttons_5Bit
- RS232_Uart_1
- SRAM
- SysACE_CompactFlash
- xps_bram_if_cntlr_1
- xps_intc_0
-- Generating libraries for processor: ppc440_0 --
Staging source files.
Running DRCs.
Running generate.
Running post_generate.
Running include - 'make -s include "COMPILER=powerpc-eabi-gcc"
"ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mcpu=440 -O2 -c"
"EXTRA_COMPILER_FLAGS=-g"'.
Running libs - 'make -s libs "COMPILER=powerpc-eabi-gcc"
"ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mcpu=440 -O2 -c"
"EXTRA_COMPILER_FLAGS=-g"'.
Compiling common
powerpc-eabi-ar: creating ../../../lib/libxil.a
Compiling lldma
Compiling standalone
Compiling gpio
Compiling emaclite
Compiling iic
Compiling pci
Compiling uartlite
Compiling sysace
Compiling intc
Compiling cpu_ppc440
Running execs_generate.
powerpc-eabi-gcc -O0 /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/Temp/WA00101_002/WA00101
_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC
/PPC440_Xilinx/portasm.S /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \
-mcpu=440 -Wl,-T -Wl,/cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \
-D GCC_PPC440 -mregnames
powerpc-eabi-size RTOSDemo/executable.elf
text data bss dec hex filename
53754 372 86524 140650 2256a RTOSDemo/executable.elf
Done!
Writing filter settings....
Done writing filter settings to:
C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters
Done writing Tab View settings to:
C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 11.2 Build EDK_LS3.47
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 237 - deprecated core for architecture 'virtex5fx'!
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 282 - deprecated core for architecture 'virtex5fx'!
Generating Block Diagram to Buffer
Generated Block Diagram SVG
At Local date and time: Tue Jun 30 18:32:58 2009
make -f system.make hwclean started...
rm -f implementation/system.ngc
rm -f platgen.log
rm -f __xps/ise/_xmsgs/platgen.xmsgs
rm -f implementation/system.bmm
rm -f implementation/system.bit
rm -f implementation/system.ncd
rm -f implementation/system_bd.bmm
rm -f implementation/system_map.ncd
rm -f __xps/system_routed
rm -rf implementation synthesis xst hdl
rm -rf xst.srp system.srp
rm -f __xps/ise/_xmsgs/bitinit.xmsgs
Done!
At Local date and time: Tue Jun 30 18:33:07 2009
make -f system.make netlistclean started...
rm -f implementation/system.ngc
rm -f platgen.log
rm -f __xps/ise/_xmsgs/platgen.xmsgs
rm -f implementation/system.bmm
Done!
At Local date and time: Tue Jun 30 18:33:13 2009
make -f system.make bitsclean started...
rm -f implementation/system.bit
rm -f implementation/system.ncd
rm -f implementation/system_bd.bmm
rm -f implementation/system_map.ncd
rm -f __xps/system_routed
Done!
At Local date and time: Tue Jun 30 18:33:24 2009
make -f system.make libsclean started...
rm -rf ppc440_0/
rm -f libgen.log
rm -f __xps/ise/_xmsgs/libgen.xmsgs
Done!
At Local date and time: Tue Jun 30 18:33:31 2009
make -f system.make programclean started...
rm -f RTOSDemo/executable.elf
Done!
At Local date and time: Tue Jun 30 18:33:37 2009
make -f system.make swclean started...
rm -rf ppc440_0/
rm -f libgen.log
rm -f __xps/ise/_xmsgs/libgen.xmsgs
rm -f RTOSDemo/executable.elf
Done!
Writing filter settings....
Done writing filter settings to:
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters
Done writing Tab View settings to:
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 11.2 Build EDK_LS3.47
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 237 - deprecated core for architecture 'virtex5fx'!
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 282 - deprecated core for architecture 'virtex5fx'!
Generating Block Diagram to Buffer
Generated Block Diagram SVG
At Local date and time: Tue Jun 30 20:53:14 2009
make -f system.make program started...
*********************************************
Creating software libraries...
*********************************************
libgen -mhs system.mhs -p xc5vfx70tff1136-1 -msg __xps/ise/xmsgprops.lst system.mss
libgen
Xilinx EDK 11.2 Build EDK_LS3.47
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
Command Line: libgen -mhs system.mhs -p xc5vfx70tff1136-1 -msg
__xps/ise/xmsgprops.lst system.mss
Release 11.2 - psf2Edward EDK_LS3.47 (nt)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
251 - deprecated core for architecture 'virtex5fx'!
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
296 - deprecated core for architecture 'virtex5fx'!
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
251 - deprecated core for architecture 'virtex5fx'!
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
296 - deprecated core for architecture 'virtex5fx'!
Checking platform configuration ...
IPNAME:plb_v46 INSTANCE:plb_v46_0 -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
107 - 1 master(s) : 12 slave(s)
IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
288 - 1 master(s) : 1 slave(s)
Checking port drivers...
WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
446 - floating connection!
Performing Clock DRCs...
Performing Reset DRCs...
Overriding system level properties...
Running system level update procedures...
Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
Running system level DRCs...
Performing System level DRCs on properties...
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
WARNING:EDK:494 -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\synthesis\ not
found.
WARNING:EDK:2530 - Timing and Resource utilization information not added
WARNING:EDK:411 - pcie -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mss line
77 - deprecated driver!
WARNING:EDK:411 - emaclite -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mss line
83 - deprecated driver!
INFO:EDK:1740 - List of peripherals connected to processor instance ppc440_0:
- DDR2_SDRAM
- DIP_Switches_8Bit
- Ethernet_MAC
- IIC_EEPROM
- LEDs_8Bit
- LEDs_Positions
- PCIe_Bridge
- Push_Buttons_5Bit
- RS232_Uart_1
- SRAM
- SysACE_CompactFlash
- xps_bram_if_cntlr_1
- xps_intc_0
-- Generating libraries for processor: ppc440_0 --
Staging source files.
Running DRCs.
Running generate.
Running post_generate.
Running include - 'make -s include "COMPILER=powerpc-eabi-gcc"
"ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mcpu=440 -O2 -c"
"EXTRA_COMPILER_FLAGS=-g"'.
Running libs - 'make -s libs "COMPILER=powerpc-eabi-gcc"
"ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mcpu=440 -O2 -c"
"EXTRA_COMPILER_FLAGS=-g"'.
Compiling common
powerpc-eabi-ar: creating ../../../lib/libxil.a
Compiling lldma
Compiling standalone
Compiling gpio
Compiling emaclite
Compiling iic
Compiling pci
Compiling uartlite
Compiling sysace
Compiling intc
Compiling cpu_ppc440
Running execs_generate.
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygd
rive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/D
ev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \
-mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \
-D GCC_PPC440 -mregnames
powerpc-eabi-size RTOSDemo/executable.elf
text data bss dec hex filename
53754 372 86524 140650 2256a RTOSDemo/executable.elf
Done!
Writing filter settings....
Done writing filter settings to:
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters
Done writing Tab View settings to:
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 11.2 Build EDK_LS3.47
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 237 - deprecated core for architecture 'virtex5fx'!
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 282 - deprecated core for architecture 'virtex5fx'!
Generating Block Diagram to Buffer
Generated Block Diagram SVG
At Local date and time: Tue Jun 30 21:05:40 2009
make -f system.make bits started...
****************************************************
Creating system netlist for hardware specification..
****************************************************
platgen -p xc5vfx70tff1136-1 -lang vhdl -msg __xps/ise/xmsgprops.lst system.mhs
Release 11.2 - platgen Xilinx EDK 11.2 Build EDK_LS3.47
(nt)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
Command Line: platgen -p xc5vfx70tff1136-1 -lang vhdl -msg
__xps/ise/xmsgprops.lst system.mhs
Parse C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/system.mhs
...
Read MPD definitions ...
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
251 - deprecated core for architecture 'virtex5fx'!
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
296 - deprecated core for architecture 'virtex5fx'!
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
251 - deprecated core for architecture 'virtex5fx'!
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
296 - deprecated core for architecture 'virtex5fx'!
Overriding IP level properties ...
Performing IP level DRCs on properties...
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
Address Map for Processor ppc440_0
(0b0000000000-0b0011111111) ppc440_0
(0000000000-0x0fffffff) DDR2_SDRAM ppc440_0_PPC440MC
(0x81000000-0x8100ffff) Ethernet_MAC plb_v46_0
(0x81400000-0x8140ffff) Push_Buttons_5Bit plb_v46_0
(0x81420000-0x8142ffff) LEDs_Positions plb_v46_0
(0x81440000-0x8144ffff) LEDs_8Bit plb_v46_0
(0x81460000-0x8146ffff) DIP_Switches_8Bit plb_v46_0
(0x81600000-0x8160ffff) IIC_EEPROM plb_v46_0
(0x81800000-0x8180ffff) xps_intc_0 plb_v46_0
(0x83600000-0x8360ffff) SysACE_CompactFlash plb_v46_0
(0x84000000-0x8400ffff) RS232_Uart_1 plb_v46_0
(0x85c00000-0x85c0ffff) PCIe_Bridge plb_v46_0
(0xc0000000-0xdfffffff) PCIe_Bridge plb_v46_0
(0xe0000000-0xefffffff) PCIe_Bridge plb_v46_0
(0xf8000000-0xf80fffff) SRAM plb_v46_0
(0xffffe000-0xffffffff) xps_bram_if_cntlr_1 plb_v46_0
INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_
01_a\data\ppc440_virtex5_v2_1_0.mpd line 175 - tool is overriding PARAMETER
C_SPLB0_P2P value to 0
Computing clock values...
INFO:EDK:1432 - Frequency for Top-Level Input Clock
'fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin' is not specified. Clock DRCs will not be
performed for IPs connected to that clock port, unless they are connected
through the clock generator IP.
INFO:EDK:1432 - Frequency for Top-Level Input Clock
'fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin' is not specified. Clock DRCs will not be
performed for IPs connected to that clock port, unless they are connected
through the clock generator IP.
INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER
C_PLBV46_NUM_MASTERS value to 1
INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER
C_PLBV46_NUM_SLAVES value to 12
INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER
C_PLBV46_MID_WIDTH value to 1
INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH
value to 128
INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 75 - tool is overriding
PARAMETER C_SPLB_DWIDTH value to 128
INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 76 - tool is overriding
PARAMETER C_SPLB_NUM_MASTERS value to 1
INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 80 - tool is overriding
PARAMETER C_SPLB_SMALLEST_MASTER value to 128
INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
\data\bram_block_v2_1_0.mpd line 69 - tool is overriding PARAMETER C_MEMSIZE
value to 0x2000
INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
\data\bram_block_v2_1_0.mpd line 70 - tool is overriding PARAMETER
C_PORT_DWIDTH value to 64
INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
\data\bram_block_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_NUM_WE
value to 8
INFO:EDK:1560 - IPNAME:xps_uartlite INSTANCE:RS232_Uart_1 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_01
_a\data\xps_uartlite_v2_1_0.mpd line 73 - tool is overriding PARAMETER
C_SPLB_DWIDTH value to 128
INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_8Bit -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH
value to 128
INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_Positions -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH
value to 128
INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:Push_Buttons_5Bit -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH
value to 128
INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:DIP_Switches_8Bit -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH
value to 128
INFO:EDK:1560 - IPNAME:xps_iic INSTANCE:IIC_EEPROM -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_iic_v2_01_a\da
ta\xps_iic_v2_1_0.mpd line 79 - tool is overriding PARAMETER C_SPLB_DWIDTH
value to 128
INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_
a\data\xps_mch_emc_v2_1_0.mpd line 82 - tool is overriding PARAMETER
C_SPLB_DWIDTH value to 128
INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_
a\data\xps_mch_emc_v2_1_0.mpd line 84 - tool is overriding PARAMETER
C_SPLB_SMALLEST_MASTER value to 128
INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
b\data\plbv46_pcie_v2_1_0.mpd line 86 - tool is overriding PARAMETER
C_MPLB_DWIDTH value to 128
INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
b\data\plbv46_pcie_v2_1_0.mpd line 87 - tool is overriding PARAMETER
C_MPLB_SMALLEST_SLAVE value to 128
INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
b\data\plbv46_pcie_v2_1_0.mpd line 89 - tool is overriding PARAMETER
C_SPLB_MID_WIDTH value to 1
INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
b\data\plbv46_pcie_v2_1_0.mpd line 90 - tool is overriding PARAMETER
C_SPLB_NUM_MASTERS value to 1
INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
b\data\plbv46_pcie_v2_1_0.mpd line 91 - tool is overriding PARAMETER
C_SPLB_SMALLEST_MASTER value to 128
INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
b\data\plbv46_pcie_v2_1_0.mpd line 95 - tool is overriding PARAMETER
C_SPLB_DWIDTH value to 128
INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER
C_PLBV46_NUM_MASTERS value to 1
INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER
C_PLBV46_NUM_SLAVES value to 1
INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER
C_PLBV46_MID_WIDTH value to 1
INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH
value to 128
INFO:EDK:1560 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ethernetlite_v
2_01_a\data\xps_ethernetlite_v2_1_0.mpd line 75 - tool is overriding
PARAMETER C_SPLB_DWIDTH value to 128
INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
\data\xps_sysace_v2_1_0.mpd line 72 - tool is overriding PARAMETER
C_SPLB_DWIDTH value to 128
INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
\data\xps_sysace_v2_1_0.mpd line 74 - tool is overriding PARAMETER
C_SPLB_MID_WIDTH value to 1
INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
\data\xps_sysace_v2_1_0.mpd line 75 - tool is overriding PARAMETER
C_SPLB_NUM_MASTERS value to 1
INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d
ata\xps_intc_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_SPLB_DWIDTH
value to 128
Checking platform address map ...
Checking platform configuration ...
INFO:EDK:1563 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
296 - This design requires design constraints to guarantee performance.
Please refer to the xps_ethernetlite_v2_00_a data sheet for details.
The PLB clock frequency must be greater than or equal to 50 MHz for 100 Mbs
Ethernet operation and greater than or equal to 5.0 MHz for 10 Mbs Ethernet
operation.
IPNAME:plb_v46 INSTANCE:plb_v46_0 -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
107 - 1 master(s) : 12 slave(s)
IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
288 - 1 master(s) : 1 slave(s)
Checking port drivers...
WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
446 - floating connection!
Performing Clock DRCs...
Performing Reset DRCs...
Overriding system level properties...
INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_
01_a\data\ppc440_virtex5_v2_1_0.mpd line 124 - tcl is overriding PARAMETER
C_PPC440MC_ADDR_BASE value to 0x00000000
INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_
01_a\data\ppc440_virtex5_v2_1_0.mpd line 125 - tcl is overriding PARAMETER
C_PPC440MC_ADDR_HIGH value to 0x0fffffff
INFO:EDK:1560 - IPNAME:jtagppc_cntlr INSTANCE:jtagppc_cntlr_inst -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_0
1_c\data\jtagppc_cntlr_v2_1_0.mpd line 70 - tcl is overriding PARAMETER
C_NUM_PPC_USED value to 1
INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d
ata\xps_intc_v2_1_0.mpd line 79 - tcl is overriding PARAMETER C_KIND_OF_INTR
value to 0b00000000000000000000000000000001
INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d
ata\xps_intc_v2_1_0.mpd line 80 - tcl is overriding PARAMETER C_KIND_OF_EDGE
value to 0b00000000000000000000000000000001
INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d
ata\xps_intc_v2_1_0.mpd line 81 - tcl is overriding PARAMETER C_KIND_OF_LVL
value to 0b00000000000000000000000000000000
Running system level update procedures...
Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
Running system level DRCs...
Performing System level DRCs on properties...
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...
INFO: The PCIe_Bridge core has constraints automatically generated by XPS in
implementation/pcie_bridge_wrapper/pcie_bridge_wrapper.ucf.
It can be overridden by constraints placed in the system.ucf file.
INFO: The Ethernet_MAC core has constraints automatically generated by XPS in
implementation/ethernet_mac_wrapper/ethernet_mac_wrapper.ucf.
It can be overridden by constraints placed in the system.ucf file.
INFO: The DDR2_SDRAM core has constraints automatically generated by XPS in
implementation/ddr2_sdram_wrapper/ddr2_sdram_wrapper.ucf.
It can be overridden by constraints placed in the system.ucf file.
Modify defaults ...
Creating stub ...
Processing licensed instances ...
Completion time: 0.00 seconds
Creating hardware output directories ...
Managing hardware (BBD-specified) netlist files ...
IPNAME:plbv46_pcie INSTANCE:pcie_bridge -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
251 - Copying (BBD-specified) netlist files.
IPNAME:xps_ethernetlite INSTANCE:ethernet_mac -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
296 - Copying (BBD-specified) netlist files.
Managing cache ...
Elaborating instances ...
IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
129 - elaborating IP
Writing HDL for elaborated instances ...
Inserting wrapper level ...
Completion time: 1.00 seconds
Constructing platform-level connectivity ...
Completion time: 1.00 seconds
Writing (top-level) BMM ...
Writing (top-level and wrappers) HDL ...
Generating synthesis project file ...
Running XST synthesis ...
INFO:EDK:2502 - The following instances are synthesized with XST. The MPD option
IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.
INSTANCE:ppc440_0 -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line 78
- Running XST synthesis
INSTANCE:plb_v46_0 -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
107 - Running XST synthesis
INSTANCE:xps_bram_if_cntlr_1 -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
116 - Running XST synthesis
INSTANCE:xps_bram_if_cntlr_1_bram -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
129 - Running XST synthesis
INSTANCE:rs232_uart_1 -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
136 - Running XST synthesis
INSTANCE:leds_8bit -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
152 - Running XST synthesis
INSTANCE:leds_positions -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
166 - Running XST synthesis
INSTANCE:push_buttons_5bit -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
180 - Running XST synthesis
INSTANCE:dip_switches_8bit -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
194 - Running XST synthesis
INSTANCE:iic_eeprom -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
208 - Running XST synthesis
INSTANCE:sram -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
221 - Running XST synthesis
INSTANCE:pcie_bridge -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
251 - Running XST synthesis
INSTANCE:ppc440_0_splb0 -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
288 - Running XST synthesis
INSTANCE:ethernet_mac -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
296 - Running XST synthesis
INSTANCE:ddr2_sdram -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
315 - Running XST synthesis
INSTANCE:sysace_compactflash -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
375 - Running XST synthesis
INSTANCE:clock_generator_0 -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
392 - Running XST synthesis
INSTANCE:jtagppc_cntlr_inst -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
431 - Running XST synthesis
INSTANCE:proc_sys_reset_0 -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
437 - Running XST synthesis
INSTANCE:xps_intc_0 -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
449 - Running XST synthesis
Running NGCBUILD ...
IPNAME:ppc440_0_wrapper INSTANCE:ppc440_0 -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line 78
- Running NGCBUILD
PMSPEC -- Overriding Xilinx file
<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file
<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>
Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p
xc5vfx70tff1136-1 -intstyle silent -uc ppc440_0_wrapper.ucf -sd ..
ppc440_0_wrapper.ngc ../ppc440_0_wrapper.ngc
Reading NGO file
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/pp
c440_0_wrapper/ppc440_0_wrapper.ngc" ...
Applying constraints in "ppc440_0_wrapper.ucf" to the design...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../ppc440_0_wrapper.ngc" ...
Total REAL time to NGCBUILD completion: 7 sec
Total CPU time to NGCBUILD completion: 6 sec
Writing NGCBUILD log file "../ppc440_0_wrapper.blc"...
NGCBUILD done.
IPNAME:rs232_uart_1_wrapper INSTANCE:rs232_uart_1 -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
136 - Running NGCBUILD
PMSPEC -- Overriding Xilinx file
<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file
<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>
Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p
xc5vfx70tff1136-1 -intstyle silent -sd .. rs232_uart_1_wrapper.ngc
../rs232_uart_1_wrapper.ngc
Reading NGO file
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/rs
232_uart_1_wrapper/rs232_uart_1_wrapper.ngc" ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../rs232_uart_1_wrapper.ngc" ...
Total REAL time to NGCBUILD completion: 8 sec
Total CPU time to NGCBUILD completion: 2 sec
Writing NGCBUILD log file "../rs232_uart_1_wrapper.blc"...
NGCBUILD done.
IPNAME:pcie_bridge_wrapper INSTANCE:pcie_bridge -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
251 - Running NGCBUILD
PMSPEC -- Overriding Xilinx file
<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file
<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>
Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p
xc5vfx70tff1136-1 -intstyle silent -uc pcie_bridge_wrapper.ucf -sd ..
pcie_bridge_wrapper.ngc ../pcie_bridge_wrapper.ngc
Reading NGO file
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/pc
ie_bridge_wrapper/pcie_bridge_wrapper.ngc" ...
Executing edif2ngd -noa
"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\implementation\pc
ie_bridge_wrapper_fifo_generator_v4_3.edn"
"pcie_bridge_wrapper_fifo_generator_v4_3.ngo"
Release 11.2 - edif2ngd L.46 (nt)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
INFO:NgdBuild - Release 11.2 edif2ngd L.46 (nt)
INFO:NgdBuild - Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file <C:/devtools/Xilinx/11.1/EDK/data/edif2ngd.pfd>
with local file <C:/devtools/Xilinx/11.1/ISE/data/edif2ngd.pfd>
Writing module to "pcie_bridge_wrapper_fifo_generator_v4_3.ngo"...
Loading design module
"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\implementation\pc
ie_bridge_wrapper\pcie_bridge_wrapper_fifo_generator_v4_3.ngo"...
Loading design module
"../pcie_bridge_wrapper_fifo_generator_v4_3_fifo_generator_v4_3_xst_1.ngc"...
Loading design module
"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\implementation\pc
ie_bridge_wrapper/dpram_70_512.ngc"...
Loading design module
"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\implementation\pc
ie_bridge_wrapper/fifo_71x512.ngc"...
Applying constraints in "pcie_bridge_wrapper.ucf" to the design...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../pcie_bridge_wrapper.ngc" ...
Total REAL time to NGCBUILD completion: 13 sec
Total CPU time to NGCBUILD completion: 9 sec
Writing NGCBUILD log file "../pcie_bridge_wrapper.blc"...
NGCBUILD done.
IPNAME:ethernet_mac_wrapper INSTANCE:ethernet_mac -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
296 - Running NGCBUILD
PMSPEC -- Overriding Xilinx file
<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file
<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>
Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p
xc5vfx70tff1136-1 -intstyle silent -uc ethernet_mac_wrapper.ucf -sd ..
ethernet_mac_wrapper.ngc ../ethernet_mac_wrapper.ngc
Reading NGO file
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/et
hernet_mac_wrapper/ethernet_mac_wrapper.ngc" ...
Executing edif2ngd -noa "ethernetlite_v1_01_b_dmem_v2.edn"
"ethernetlite_v1_01_b_dmem_v2.ngo"
Release 11.2 - edif2ngd L.46 (nt)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
INFO:NgdBuild - Release 11.2 edif2ngd L.46 (nt)
INFO:NgdBuild - Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file <C:/devtools/Xilinx/11.1/EDK/data/edif2ngd.pfd>
with local file <C:/devtools/Xilinx/11.1/ISE/data/edif2ngd.pfd>
Writing module to "ethernetlite_v1_01_b_dmem_v2.ngo"...
Loading design module
"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\implementation\et
hernet_mac_wrapper\ethernetlite_v1_01_b_dmem_v2.ngo"...
Applying constraints in "ethernet_mac_wrapper.ucf" to the design...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../ethernet_mac_wrapper.ngc" ...
Total REAL time to NGCBUILD completion: 9 sec
Total CPU time to NGCBUILD completion: 6 sec
Writing NGCBUILD log file "../ethernet_mac_wrapper.blc"...
NGCBUILD done.
IPNAME:ddr2_sdram_wrapper INSTANCE:ddr2_sdram -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
315 - Running NGCBUILD
PMSPEC -- Overriding Xilinx file
<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file
<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>
Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p
xc5vfx70tff1136-1 -intstyle silent -uc ddr2_sdram_wrapper.ucf -sd ..
ddr2_sdram_wrapper.ngc ../ddr2_sdram_wrapper.ngc
Reading NGO file
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/dd
r2_sdram_wrapper/ddr2_sdram_wrapper.ngc" ...
Applying constraints in "ddr2_sdram_wrapper.ucf" to the design...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../ddr2_sdram_wrapper.ngc" ...
Total REAL time to NGCBUILD completion: 7 sec
Total CPU time to NGCBUILD completion: 7 sec
Writing NGCBUILD log file "../ddr2_sdram_wrapper.blc"...
NGCBUILD done.
IPNAME:xps_intc_0_wrapper INSTANCE:xps_intc_0 -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
449 - Running NGCBUILD
PMSPEC -- Overriding Xilinx file
<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file
<C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>
Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p
xc5vfx70tff1136-1 -intstyle silent -sd .. xps_intc_0_wrapper.ngc
../xps_intc_0_wrapper.ngc
Reading NGO file
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/xp
s_intc_0_wrapper/xps_intc_0_wrapper.ngc" ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../xps_intc_0_wrapper.ngc" ...
Total REAL time to NGCBUILD completion: 1 sec
Total CPU time to NGCBUILD completion: 1 sec
Writing NGCBUILD log file "../xps_intc_0_wrapper.blc"...
NGCBUILD done.
Rebuilding cache ...
Total run time: 1039.00 seconds
Running synthesis...
bash -c "cd synthesis; ./synthesis.sh"
xst -ifn system_xst.scr -intstyle silent
Running XST synthesis ...
XST completed
Release 11.2 - ngcbuild L.46 (nt)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
Overriding Xilinx file <ngcflow.csf> with local file
<c:/devtools/Xilinx/11.1/ISE/data/ngcflow.csf>
Command Line: c:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe
./system.ngc ../implementation/system.ngc -sd ../implementation -i -ise
../__xps/ise/system.ise
Reading NGO file
"c:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/synthesis/system.
ngc" ...
Loading design module "../implementation/ppc440_0_wrapper.ngc"...
Loading design module "../implementation/plb_v46_0_wrapper.ngc"...
Loading design module "../implementation/xps_bram_if_cntlr_1_wrapper.ngc"...
Loading design module
"../implementation/xps_bram_if_cntlr_1_bram_wrapper.ngc"...
Loading design module "../implementation/rs232_uart_1_wrapper.ngc"...
Loading design module "../implementation/leds_8bit_wrapper.ngc"...
Loading design module "../implementation/leds_positions_wrapper.ngc"...
Loading design module "../implementation/push_buttons_5bit_wrapper.ngc"...
Loading design module "../implementation/dip_switches_8bit_wrapper.ngc"...
Loading design module "../implementation/iic_eeprom_wrapper.ngc"...
Loading design module "../implementation/sram_wrapper.ngc"...
Loading design module "../implementation/pcie_bridge_wrapper.ngc"...
Loading design module "../implementation/ppc440_0_splb0_wrapper.ngc"...
Loading design module "../implementation/ethernet_mac_wrapper.ngc"...
Loading design module "../implementation/ddr2_sdram_wrapper.ngc"...
Loading design module "../implementation/sysace_compactflash_wrapper.ngc"...
Loading design module "../implementation/clock_generator_0_wrapper.ngc"...
Loading design module "../implementation/jtagppc_cntlr_inst_wrapper.ngc"...
Loading design module "../implementation/proc_sys_reset_0_wrapper.ngc"...
Loading design module "../implementation/xps_intc_0_wrapper.ngc"...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../implementation/system.ngc" ...
Total REAL time to NGCBUILD completion: 10 sec
Total CPU time to NGCBUILD completion: 9 sec
Writing NGCBUILD log file "../implementation/system.blc"...
NGCBUILD done.
*********************************************
Running Xilinx Implementation tools..
*********************************************
xflow -wd implementation -p xc5vfx70tff1136-1 -implement xflow.opt -ise ../__xps/ise/system.ise system.ngc
Release 11.2 - Xflow L.46 (nt)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
xflow.exe -wd implementation -p xc5vfx70tff1136-1 -implement xflow.opt -ise
../__xps/ise/system.ise system.ngc
PMSPEC -- Overriding Xilinx file
<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file
<c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>
.... Copying flowfile c:/devtools/Xilinx/11.1/ISE/xilinx/data/fpga.flw into
working directory
C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation
Using Flow File:
C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/fpg
a.flw
Using Option File(s):
C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/xf
low.opt
Creating Script File ...
#----------------------------------------------#
# Starting program ngdbuild
# ngdbuild -ise ../__xps/ise/system.ise -p xc5vfx70tff1136-1 -nt timestamp -bm
system.bmm
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/sy
stem.ngc" -uc system.ucf system.ngd
#----------------------------------------------#
Release 11.2 - ngdbuild L.46 (nt)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file
<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file
<c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>
Command Line: ngdbuild -ise ../__xps/ise/system.ise -p xc5vfx70tff1136-1 -nt
timestamp -bm system.bmm
C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/sys
tem.ngc -uc system.ucf system.ngd
Reading NGO file
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/sy
stem.ngc" ...
Gathering constraint information from source properties...
Done.
Applying constraints in "system.ucf" to the design...
WARNING:NgdBuild:931 - The value of SIM_DEVICE on instance
'clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_
ADV.DCM_ADV_INST' of type DCM_ADV has been changed from 'VIRTEX4' to
'VIRTEX5' to correct post-ngdbuild and timing simulation for this primitive.
In order for functional simulation to be correct, the value of SIM_DEVICE
should be changed in this same manner in the source netlist or constraint
file.
Resolving constraint associations...
Checking Constraint Associations...
WARNING:ConstraintSystem:3 - Constraint <TIMESPEC "TS_MC_RD_DATA_SEL" = FROM
"TNM_RD_DATA_SEL" TO "TNM_CLK0" "TS_clk_div_slow_0_clk_div_slow_0_DDR2_CLK_i"
* 4;> [system.ucf(264)]: This constraint will be ignored because the relative
clock constraint named 'TS_clk_div_slow_0_clk_div_slow_0_DDR2_CLK_i' was not
found.
INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification
'TS_sys_clk_pin', was traced into PLL_ADV instance
clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.
The following new TNM groups and period specifications were generated at the
PLL_ADV output(s):
CLKOUT0: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_0_ =
PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_0_" TS_sys_clk_pin *
1.25 PHASE 2 ns HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification
'TS_sys_clk_pin', was traced into PLL_ADV instance
clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.
The following new TNM groups and period specifications were generated at the
PLL_ADV output(s):
CLKOUT1: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_1_ =
PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_1_" TS_sys_clk_pin *
1.25 HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification
'TS_sys_clk_pin', was traced into PLL_ADV instance
clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.
The following new TNM groups and period specifications were generated at the
PLL_ADV output(s):
CLKOUT2: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_2_ =
PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_2_" TS_sys_clk_pin *
1.25 HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification
'TS_sys_clk_pin', was traced into PLL_ADV instance
clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.
The following new TNM groups and period specifications were generated at the
PLL_ADV output(s):
CLKOUT3: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_3_ =
PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_3_" TS_sys_clk_pin *
2 HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification
'TS_sys_clk_pin', was traced into PLL_ADV instance
clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.
The following new TNM groups and period specifications were generated at the
PLL_ADV output(s):
CLKOUT4: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_4_ =
PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_4_" TS_sys_clk_pin *
0.625 HIGH 50%>
Done...
Checking Partitions ...
Processing BMM file ...
WARNING:NgdBuild:1212 - User specified non-default attribute value
(8.0000000000000000) was detected for the CLKIN_PERIOD attribute on DCM
"clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST".
This does not match the PERIOD constraint value (5 ns.). The uncertainty
calculation will use the non-default attribute value. This could result in
incorrect uncertainty calculated for DCM output clocks.
Checking expanded design ...
WARNING:NgdBuild:443 - SFF primitive
'xps_bram_if_cntlr_1/xps_bram_if_cntlr_1/INCLUDE_BURST_SUPPORT.I_SLAVE_BURST_
ATTACH/I_DBEAT_CONTROL/I_DBEAT_CNTR/STRUCTURAL_A_GEN.I_ADDSUB_GEN[4].FDRE_I'
has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'SRAM/SRAM/EMC_CTRL_I/MEM_STEER_I/SYNC_MEM_DQT.REG_DQT_GEN[2].DQT_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'SRAM/SRAM/EMC_CTRL_I/MEM_STEER_I/GSYNC_MEM_RDACK_GEN.ADDR_ALIGN_PIPE_GEN[3].
ALIGN_PIPE' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
ENT/I_DECODER/GEN_CE_FOR_SHARED.GEN_BKEND_CE_REGISTERS[0].I_BKEND_WRCE_REG'
has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
ENT/I_DECODER/GEN_CE_FOR_SHARED.GEN_BKEND_CE_REGISTERS[0].I_BKEND_RDCE_REG'
has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
ENT/I_BURST_SUPPORT/RESPONSE_DBEAT_CNTR_I/STRUCTURAL_A_GEN.I_ADDSUB_GEN[7].FD
RE_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
ENT/I_BURST_SUPPORT/CONTROL_DBEAT_CNTR_I/STRUCTURAL_A_GEN.I_ADDSUB_GEN[7].FDR
E_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[0].I_FDRSE_BE0to3
' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[1].I_FDRSE_BE0to3
' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[2].I_FDRSE_BE0to3
' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[3].I_FDRSE_BE0to3
' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
ENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG'
has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
ENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG
' has unconnected output pin
WARNING:NgdBuild:486 - Attribute "CLK_FEEDBACK" is not allowed on symbol
"PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.pll_ad
v_i" of type "PLL_ADV". This attribute will be ignored.
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B
URSTXFER.I_STEER_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B
URSTXFER.I_BUS_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B
URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE
_4to7[7].I_FDRSE_BE4to7' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B
URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE
_4to7[6].I_FDRSE_BE4to7' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B
URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE
_4to7[5].I_FDRSE_BE4to7' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B
URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE
_4to7[4].I_FDRSE_BE4to7' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B
URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[3].I_FDRSE_B
E0to3' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B
URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[2].I_FDRSE_B
E0to3' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B
URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[1].I_FDRSE_B
E0to3' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B
URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[0].I_FDRSE_B
E0to3' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_S
_H_ADDR_REG[6].I_ADDR_S_H_REG' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_S
_H_ADDR_REG[7].I_ADDR_S_H_REG' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_RDCE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_WRCE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_RDCE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_WRCE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_RDCE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_WRCE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_RDCE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_WRCE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_RDCE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_WRCE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_RDCE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_WRCE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_RDCE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_WRCE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_RDCE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_WRCE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_RDCE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_WRCE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_RDCE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_WRCE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[32].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[33].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[34].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[35].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[36].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[37].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[38].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[39].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[40].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[41].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[42].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[43].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[44].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[44].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[44].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[46].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[46].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[46].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[53].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[53].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[53].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[54].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[54].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[54].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[55].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[55].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[55].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[56].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[57].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[58].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[59].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[60].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[61].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[61].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[61].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[62].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[62].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[62].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[63].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[63].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[63].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[1].GEN_USER_CE.GEN_ALL_CEs[64].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[1].GEN_USER_CE.GEN_ALL_CEs[64].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[1].GEN_USER_CE.GEN_ALL_CEs[64].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[65].I_BKend_CE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[66].I_BKend_CE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[66].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[67].I_BKend_CE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[68].I_BKend_CE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[68].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[68].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[69].I_BKend_CE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[69].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[69].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[70].I_BKend_CE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[70].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[70].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[71].I_BKend_CE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[71].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[72].I_BKend_CE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[73].I_BKend_CE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[74].I_BKend_CE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[74].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[74].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[75].I_BKend_CE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[76].I_BKend_CE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[76].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[76].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[77].I_BKend_CE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[77].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[77].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[78].I_BKend_CE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[78].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[78].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[79].I_BKend_CE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[79].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[79].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[80].I_BKend_CE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[80].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[80].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[3].GEN_RESET_CE.I_BKend_CE_REG' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[3].GEN_RESET_CE.I_BKend_RDCE_REG' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[4].GEN_USER_CE.GEN_ALL_CEs[82].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[4].GEN_USER_CE.GEN_ALL_CEs[82].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[4].GEN_USER_CE.GEN_ALL_CEs[82].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[5].GEN_USER_CE.GEN_ALL_CEs[83].I_BKend_CE_REG' has unconnected
output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[5].GEN_USER_CE.GEN_ALL_CEs[83].I_BKend_RDCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
E_ASSIGNMENTS[5].GEN_USER_CE.GEN_ALL_CEs[83].I_BKend_WRCE_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_
SIZE2_REG0' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_
SIZE2_REG1' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_
SIZE2_REG2' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'PCIe_Bridge/PCIe_Bridge/comp_plbv46_master/I_RD_CONTROL/I_RD_ABORT_REG' has
unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/COLLISION_SYNC' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU10'
has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU15'
has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU20'
has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU25'
has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU30'
has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU35'
has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU130'
has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU237'
has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU10'
has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU15'
has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU20'
has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU25'
has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU30'
has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU35'
has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU130'
has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU237'
has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib
/gen_rden[1].u_calib_rden_r' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib
/gen_rden[2].u_calib_rden_r' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib
/gen_rden[3].u_calib_rden_r' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib
/gen_rden[4].u_calib_rden_r' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib
/gen_rden[5].u_calib_rden_r' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib
/gen_rden[6].u_calib_rden_r' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib
/gen_rden[7].u_calib_rden_r' has unconnected output pin
WARNING:NgdBuild:486 - Attribute "CLK_FEEDBACK" is not allowed on symbol
"clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst"
of type "PLL_ADV". This attribute will be ignored.
WARNING:NgdBuild:452 - logical net 'N194' has no driver
WARNING:NgdBuild:452 - logical net 'N195' has no driver
WARNING:NgdBuild:452 - logical net 'N196' has no driver
WARNING:NgdBuild:452 - logical net 'N197' has no driver
WARNING:NgdBuild:452 - logical net 'N198' has no driver
WARNING:NgdBuild:452 - logical net 'N199' has no driver
WARNING:NgdBuild:452 - logical net 'N200' has no driver
WARNING:NgdBuild:452 - logical net 'N201' has no driver
WARNING:NgdBuild:452 - logical net 'N202' has no driver
WARNING:NgdBuild:452 - logical net 'N203' has no driver
WARNING:NgdBuild:452 - logical net 'N204' has no driver
WARNING:NgdBuild:452 - logical net 'N205' has no driver
WARNING:NgdBuild:452 - logical net 'N206' has no driver
WARNING:NgdBuild:452 - logical net 'N207' has no driver
WARNING:NgdBuild:452 - logical net 'N208' has no driver
WARNING:NgdBuild:452 - logical net 'N209' has no driver
WARNING:NgdBuild:452 - logical net 'N210' has no driver
WARNING:NgdBuild:452 - logical net 'N211' has no driver
WARNING:NgdBuild:452 - logical net 'N212' has no driver
WARNING:NgdBuild:452 - logical net 'N213' has no driver
WARNING:NgdBuild:452 - logical net 'N214' has no driver
WARNING:NgdBuild:452 - logical net 'N215' has no driver
WARNING:NgdBuild:452 - logical net 'N216' has no driver
WARNING:NgdBuild:452 - logical net 'N217' has no driver
WARNING:NgdBuild:452 - logical net 'N218' has no driver
WARNING:NgdBuild:452 - logical net 'N219' has no driver
WARNING:NgdBuild:452 - logical net 'N220' has no driver
WARNING:NgdBuild:452 - logical net 'N221' has no driver
WARNING:NgdBuild:452 - logical net 'N222' has no driver
WARNING:NgdBuild:452 - logical net 'N223' has no driver
WARNING:NgdBuild:452 - logical net 'N224' has no driver
WARNING:NgdBuild:452 - logical net 'N225' has no driver
WARNING:NgdBuild:452 - logical net 'N226' has no driver
WARNING:NgdBuild:452 - logical net 'N227' has no driver
WARNING:NgdBuild:452 - logical net 'N228' has no driver
WARNING:NgdBuild:452 - logical net 'N229' has no driver
WARNING:NgdBuild:452 - logical net 'N230' has no driver
WARNING:NgdBuild:452 - logical net 'N231' has no driver
WARNING:NgdBuild:452 - logical net 'N232' has no driver
WARNING:NgdBuild:452 - logical net 'N233' has no driver
WARNING:NgdBuild:452 - logical net 'N234' has no driver
WARNING:NgdBuild:452 - logical net 'N235' has no driver
WARNING:NgdBuild:452 - logical net 'N236' has no driver
WARNING:NgdBuild:452 - logical net 'N237' has no driver
WARNING:NgdBuild:452 - logical net 'N238' has no driver
WARNING:NgdBuild:452 - logical net 'N239' has no driver
WARNING:NgdBuild:452 - logical net 'N240' has no driver
WARNING:NgdBuild:452 - logical net 'N241' has no driver
WARNING:NgdBuild:452 - logical net 'N242' has no driver
WARNING:NgdBuild:452 - logical net 'N243' has no driver
WARNING:NgdBuild:452 - logical net 'N244' has no driver
WARNING:NgdBuild:452 - logical net 'N245' has no driver
WARNING:NgdBuild:452 - logical net 'N246' has no driver
WARNING:NgdBuild:452 - logical net 'N247' has no driver
WARNING:NgdBuild:452 - logical net 'N248' has no driver
WARNING:NgdBuild:452 - logical net 'N249' has no driver
WARNING:NgdBuild:452 - logical net 'N250' has no driver
WARNING:NgdBuild:452 - logical net 'N251' has no driver
WARNING:NgdBuild:452 - logical net 'N252' has no driver
WARNING:NgdBuild:452 - logical net 'N253' has no driver
WARNING:NgdBuild:452 - logical net 'N254' has no driver
WARNING:NgdBuild:452 - logical net 'N255' has no driver
WARNING:NgdBuild:452 - logical net 'N256' has no driver
WARNING:NgdBuild:452 - logical net 'N257' has no driver
WARNING:NgdBuild:452 - logical net 'N266' has no driver
WARNING:NgdBuild:452 - logical net 'N267' has no driver
WARNING:NgdBuild:452 - logical net 'N268' has no driver
WARNING:NgdBuild:452 - logical net 'N269' has no driver
WARNING:NgdBuild:452 - logical net 'N270' has no driver
WARNING:NgdBuild:452 - logical net 'N271' has no driver
WARNING:NgdBuild:452 - logical net 'N272' has no driver
WARNING:NgdBuild:452 - logical net 'N273' has no driver
WARNING:NgdBuild:452 - logical net 'N306' has no driver
WARNING:NgdBuild:452 - logical net 'N307' has no driver
WARNING:NgdBuild:452 - logical net 'N308' has no driver
WARNING:NgdBuild:452 - logical net 'N309' has no driver
WARNING:NgdBuild:452 - logical net 'N310' has no driver
WARNING:NgdBuild:452 - logical net 'N311' has no driver
WARNING:NgdBuild:452 - logical net 'N312' has no driver
WARNING:NgdBuild:452 - logical net 'N313' has no driver
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_terrfwd_n'
has no driver
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_rerrfwd_n'
has no driver
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_tsrc_dsc_n'
has no driver
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_tbuf_av<3>'
has no driver
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_trem_n<4>'
has no driver
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 348
Writing NGD file "system.ngd" ...
Total REAL time to NGDBUILD completion: 1 min 58 sec
Total CPU time to NGDBUILD completion: 1 min 28 sec
Writing NGDBUILD log file "system.bld"...
NGDBUILD done.
#----------------------------------------------#
# Starting program map
# map -ise ../__xps/ise/system.ise -o system_map.ncd -w -pr b -ol high -timing
system.ngd system.pcf
#----------------------------------------------#
Release 11.2 - Map L.46 (nt)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file
<C:/devtools/Xilinx/11.1/EDK/data/Xdh_PrimTypeLib.xda> with local file
<c:/devtools/Xilinx/11.1/ISE/data/Xdh_PrimTypeLib.xda>
Using target part "5vfx70tff1136-1".
WARNING:LIT:243 - Logical network N194 has no load.
WARNING:LIT:395 - The above warning message is repeated 1200 more times for the
following (max. 5 shown):
N195,
N196,
N197,
N198,
N199
To see the details of these warning messages, please use the -detail switch.
Mapping design into LUTs...
WARNING:MapLib:701 - Signal fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin
connected to top level port fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin has
been removed.
WARNING:MapLib:701 - Signal fpga_0_Ethernet_MAC_PHY_col_pin connected to top
level port fpga_0_Ethernet_MAC_PHY_col_pin has been removed.
WARNING:MapLib:41 - All members of TNM group "ppc440_0_PPCS0PLBMBUSY" have been
optimized out of the design.
Writing file system_map.ngm...
WARNING:Pack:2874 - Trimming timing constraints from pin
xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0
of frag REGCLKAU connected to power/ground net
xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAU_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0
of frag REGCLKAL connected to power/ground net
xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAL_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1
of frag REGCLKAU connected to power/ground net
xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAU_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1
of frag REGCLKAL connected to power/ground net
xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAL_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst
of frag REGCLKAU connected to power/ground net
PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAU_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst
of frag REGCLKAL connected to power/ground net
PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAL_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst
of frag REGCLKAU connected to power/ground net
PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAU_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst
of frag REGCLKAL connected to power/ground net
PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAL_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r
x_bridge/fifo_inst/oq_fifo/Mram_regBank
of frag RDRCLKU connected to power/ground net
PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r
x_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKU_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r
x_bridge/fifo_inst/oq_fifo/Mram_regBank
of frag RDRCLKL connected to power/ground net
PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r
x_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKL_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0
/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.
noeccerr.SDP
of frag RDRCLKU connected to power/ground net
PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0
/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.
noeccerr.SDP_RDRCLKU_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0
/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.
noeccerr.SDP
of frag RDRCLKL connected to power/ground net
PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0
/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.
noeccerr.SDP_RDRCLKL_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m
em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.
ram/SDP.WIDE_PRIM36.noeccerr.SDP
of frag RDRCLKU connected to power/ground net
PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m
em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.
ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m
em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.
ram/SDP.WIDE_PRIM36.noeccerr.SDP
of frag RDRCLKL connected to power/ground net
PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m
em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.
ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM
P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi
nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
of frag RDRCLKU connected to power/ground net
PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM
P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi
nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM
P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi
nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
of frag RDRCLKL connected to power/ground net
PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM
P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi
nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2
/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM
36.noeccerr.SDP
of frag RDRCLKU connected to power/ground net
PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2
/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM
36.noeccerr.SDP_RDRCLKU_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2
/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM
36.noeccerr.SDP
of frag RDRCLKL connected to power/ground net
PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2
/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM
36.noeccerr.SDP_RDRCLKL_tiesig
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM
TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP "TNM_CLK0" TS_MC_CLK * 4 ignored during
timing analysis.
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 1 mins 55 secs
Total CPU time at the beginning of Placer: 1 mins 43 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:150b88e2) REAL time: 2 mins 13 secs
Phase 2.7 Design Feasibility Check
WARNING:Place:838 - An IO Bus with more than one IO standard is found.
Components associated with this bus are as follows:
Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<7> IOSTANDARD = LVCMOS25
Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<6> IOSTANDARD = LVCMOS25
Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<5> IOSTANDARD = LVCMOS25
Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<4> IOSTANDARD = LVCMOS18
Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25
Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS18
Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS18
Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS18
WARNING:Place:838 - An IO Bus with more than one IO standard is found.
Components associated with this bus are as follows:
Comp: fpga_0_SRAM_Mem_DQ_pin<31> IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin<30> IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin<29> IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin<28> IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin<27> IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin<26> IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin<25> IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin<24> IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin<23> IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin<22> IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin<21> IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin<20> IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin<19> IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin<18> IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin<17> IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin<16> IOSTANDARD = LVDCI_33
Comp: fpga_0_SRAM_Mem_DQ_pin<15> IOSTANDARD = LVCMOS33
Comp: fpga_0_SRAM_Mem_DQ_pin<14> IOSTANDARD = LVCMOS33
Comp: fpga_0_SRAM_Mem_DQ_pin<13> IOSTANDARD = LVCMOS33
Comp: fpga_0_SRAM_Mem_DQ_pin<12> IOSTANDARD = LVCMOS33
Comp: fpga_0_SRAM_Mem_DQ_pin<11> IOSTANDARD = LVCMOS33
Comp: fpga_0_SRAM_Mem_DQ_pin<10> IOSTANDARD = LVCMOS33
Comp: fpga_0_SRAM_Mem_DQ_pin<9> IOSTANDARD = LVCMOS33
Comp: fpga_0_SRAM_Mem_DQ_pin<8> IOSTANDARD = LVCMOS33
Comp: fpga_0_SRAM_Mem_DQ_pin<7> IOSTANDARD = LVCMOS33
Comp: fpga_0_SRAM_Mem_DQ_pin<6> IOSTANDARD = LVCMOS33
Comp: fpga_0_SRAM_Mem_DQ_pin<5> IOSTANDARD = LVCMOS33
Comp: fpga_0_SRAM_Mem_DQ_pin<4> IOSTANDARD = LVCMOS33
Comp: fpga_0_SRAM_Mem_DQ_pin<3> IOSTANDARD = LVCMOS33
Comp: fpga_0_SRAM_Mem_DQ_pin<2> IOSTANDARD = LVCMOS33
Comp: fpga_0_SRAM_Mem_DQ_pin<1> IOSTANDARD = LVCMOS33
Comp: fpga_0_SRAM_Mem_DQ_pin<0> IOSTANDARD = LVCMOS33
Phase 2.7 Design Feasibility Check (Checksum:150b88e2) REAL time: 2 mins 14 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:f23945c2) REAL time: 2 mins 14 secs
Phase 4.37 Local Placement Optimization
Phase 4.37 Local Placement Optimization (Checksum:f23945c2) REAL time: 2 mins 14 secs
Phase 5.33 Local Placement Optimization
Phase 5.33 Local Placement Optimization (Checksum:f23945c2) REAL time: 8 mins 58 secs
Phase 6.32 Local Placement Optimization
Phase 6.32 Local Placement Optimization (Checksum:f23945c2) REAL time: 9 mins 1 secs
Phase 7.2 Initial Clock and IO Placement
There are 16 clock regions on the target FPGA device:
|------------------------------------------|------------------------------------------|
| CLOCKREGION_X0Y7: | CLOCKREGION_X1Y7: |
| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |
| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |
| 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use |
| 4 center BUFIOs available, 0 in use | |
| | |
|------------------------------------------|------------------------------------------|
| CLOCKREGION_X0Y6: | CLOCKREGION_X1Y6: |
| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |
| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |
| 4 edge BUFIOs available, 3 in use | 4 edge BUFIOs available, 0 in use |
| 0 center BUFIOs available, 0 in use | |
| | |
|------------------------------------------|------------------------------------------|
| CLOCKREGION_X0Y5: | CLOCKREGION_X1Y5: |
| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |
| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |
| 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use |
| 2 center BUFIOs available, 0 in use | |
| | |
|------------------------------------------|------------------------------------------|
| CLOCKREGION_X0Y4: | CLOCKREGION_X1Y4: |
| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |
| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |
| 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use |
| 2 center BUFIOs available, 0 in use | |
| | |
|------------------------------------------|------------------------------------------|
| CLOCKREGION_X0Y3: | CLOCKREGION_X1Y3: |
| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |
| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |
| 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use |
| 2 center BUFIOs available, 0 in use | |
| | |
|------------------------------------------|------------------------------------------|
| CLOCKREGION_X0Y2: | CLOCKREGION_X1Y2: |
| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |
| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |
| 4 edge BUFIOs available, 3 in use | 4 edge BUFIOs available, 0 in use |
| 2 center BUFIOs available, 0 in use | |
| | |
|------------------------------------------|------------------------------------------|
| CLOCKREGION_X0Y1: | CLOCKREGION_X1Y1: |
| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |
| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use
|
| 4 edge BUFIOs available, 2 in use | 4 edge BUFIOs available, 0 in use |
| 0 center BUFIOs available, 0 in use | |
| | |
|------------------------------------------|------------------------------------------|
| CLOCKREGION_X0Y0: | CLOCKREGION_X1Y0: |
| 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use |
| 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use |
| 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use |
| 4 center BUFIOs available, 0 in use | |
| | |
|------------------------------------------|------------------------------------------|
Clock-Region: <CLOCKREGION_X0Y1>
key resource utilizations (used/available): edge-bufios - 2/4; bufrs - 0/2; regional-clock-spines - 0/4
|-----------------------------------------------------------------------------------------------------------------------------------------------------------
| | clock | BRAM | | | | | | | | | | | |
| | region | FIFO | DCM | GT | ILOGIC | OLOGIC | FF | LUTM | LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
| | Upper Region| 24 | 2 | 0 | 60 | 60 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the upper region
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
| |CurrentRegion| 24 | 4 | 0 | 40 | 40 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the current region
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
| | Lower Region| 24 | 0 | 0 | 80 | 80 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the lower region
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
| clock | region | -----------------------------------------------
| type | expansion | | <IO/Regional clock Net Name>
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>"
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>"
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
Clock-Region: <CLOCKREGION_X0Y2>
key resource utilizations (used/available): edge-bufios - 3/4; center-bufios - 0/2; bufrs - 0/2; regional-clock-spines - 0/4
|-----------------------------------------------------------------------------------------------------------------------------------------------------------
| | clock | BRAM | | | | | | | | | | | |
| | region | FIFO | DCM | GT | ILOGIC | OLOGIC | FF | LUTM | LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
| | Upper Region| 8 | 0 | 0 | 60 | 60 | 1280 | 640 | 1920 | 0 | 0 | 1 | 0 | <- Available resources in the upper region
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
| |CurrentRegion| 24 | 2 | 0 | 60 | 60 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the current region
|-------|-------------|------|-----|----|--------|-------
-|-------|-------|-------|------|------|-----|------|----------------------------------------------
| | Lower Region| 24 | 4 | 0 | 40 | 40 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the lower region
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
| clock | region | -----------------------------------------------
| type | expansion | | <IO/Regional clock Net Name>
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>"
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>"
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>"
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
Clock-Region: <CLOCKREGION_X0Y6>
key resource utilizations (used/available): edge-bufios - 3/4; bufrs - 0/2; regional-clock-spines - 0/4
|-----------------------------------------------------------------------------------------------------------------------------------------------------------
| | clock | BRAM | | | | | | | | | | | |
| | region | FIFO | DCM | GT | ILOGIC | OLOGIC | FF | LUTM | LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
| | Upper Region| 24 | 0 | 0 | 80 | 80 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the upper region
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
| |CurrentRegion| 24 | 4 | 0 | 40 | 40 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the current region
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
| | Lower Region| 24 | 2 | 0 | 60 | 60 | 3200 | 1600 | 4800 | 0 | 0 | 0 | 0 | <- Available resources in the lower region
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
| clock | region | -----------------------------------------------
| type | expansion | | <IO/Regional clock Net Name>
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 |
0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>"
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>"
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>"
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
######################################################################################
# REGIONAL CLOCKING RESOURCE DISTRIBUTION UCF REPORT:
#
# Number of Regional Clocking Regions in the device: 16 (4 clock spines in each)
# Number of Regional Clock Networks used in this design: 8 (each network can be
# composed of up to 3 clock spines and cover up to 3 regional clock regions)
#
######################################################################################
# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" driven by "BUFIO_X0Y27"
INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_bufio_dqs" LOC =
"BUFIO_X0Y27" ;
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" TNM_NET =
"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" ;
TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" AREA_GROUP =
"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" ;
AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" RANGE =
CLOCKREGION_X0Y6;
# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" driven by "BUFIO_X0Y9"
INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/u_bufio_dqs" LOC =
"BUFIO_X0Y9" ;
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" TNM_NET =
"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" ;
TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" AREA_GROUP =
"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" ;
AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" RANGE =
CLOCKREGION_X0Y2;
# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" driven by "BUFIO_X0Y11"
INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_bufio_dqs" LOC =
"BUFIO_X0Y11" ;
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" TNM_NET =
"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" ;
TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" AREA_GROUP =
"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" ;
AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" RANGE =
CLOCKREGION_X0Y2;
# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" driven by "BUFIO_X0Y4"
INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_bufio_dqs" LOC =
"BUFIO_X0Y4" ;
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" TNM_NET =
"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" ;
TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" AREA_GROUP =
"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" ;
AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" RANGE =
CLOCKREGION_X0Y1;
# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" driven by "BUFIO_X0Y25"
INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_bufio_dqs" LOC =
"BUFIO_X0Y25" ;
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" TNM_NET =
"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" ;
TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" AREA_GROUP =
"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" ;
AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" RANGE =
CLOCKREGION_X0Y6;
# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" driven by "BUFIO_X0Y7"
INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/u_bufio_dqs" LOC =
"BUFIO_X0Y7" ;
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" TNM_NET =
"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" ;
TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" AREA_GROUP =
"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" ;
AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" RANGE =
CLOCKREGION_X0Y1;
# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" driven by "BUFIO_X0Y26"
INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_bufio_dqs" LOC =
"BUFIO_X0Y26" ;
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" TNM_NET =
"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" ;
TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" AREA_GROUP =
"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" ;
AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" RANGE =
CLOCKREGION_X0Y6;
# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" driven by "BUFIO_X0Y10"
INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[3].u_iob_dqs/u_bufio_dqs" LOC =
"BUFIO_X0Y10" ;
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" TNM_NET =
"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" ;
TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" AREA_GROUP =
"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" ;
AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" RANGE =
CLOCKREGION_X0Y2;
Phase 7.2 Initial Clock and IO Placement (Checksum:7e049af9) REAL time: 9 mins 19 secs
Phase 8.36 Local Placement Optimization
Phase 8.36 Local Placement Optimization (Checksum:7e049af9) REAL time: 9 mins 19 secs
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Phase 9.30 Global Clock Region Assignment
######################################################################################
# GLOBAL CLOCK NET DISTRIBUTION UCF REPORT:
#
# Number of Global Clock Regions : 16
# Number of Global Clock Networks: 15
#
# Clock Region Assignment: SUCCESSFUL
# Location of Clock Components
INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT1.CLKOUT1_BUFG_INST" LOC = "BUFGCTRL_X0Y1" ;
INST "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y30" ;
INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.gtxclk_pll_bufg" LOC = "BUFGCTRL_X0Y29" ;
INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.coreclk_pll_bufg" LOC = "BUFGCTRL_X0Y27" ;
INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT2.CLKOUT2_BUFG_INST" LOC = "BUFGCTRL_X0Y2" ;
INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_BUFG_for_CLKFBOUT.CLKFB_BUFG_INST" LOC = "BUFGCTRL_X0Y3" ;
INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/notsame.usrclk_pll_bufg" LOC = "BUFGCTRL_X0Y28" ;
INST "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y8" ;
INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.clkfbin_pll_bufg" LOC = "BUFGCTRL_X0Y26" ;
INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT3.CLKOUT3_BUFG_INST" LOC = "BUFGCTRL_X0Y4" ;
INST "clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/Using_BUFG_for_CLK0.CLK0_BUFG_INST" LOC = "BUFGCTRL_X0Y7" ;
INST "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y31" ;
INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT0.CLKOUT0_BUFG_INST" LOC = "BUFGCTRL_X0Y5" ;
INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT4.CLKOUT4_BUFG_INST" LOC = "BUFGCTRL_X0Y6" ;
INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/bufg2" LOC = "BUFGCTRL_X0Y0" ;
INST "clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST" LOC = "DCM_ADV_X0Y0" ;
INST "fpga_0_SRAM_ZBT_CLK_FB_pin" LOC = "IOB_X1Y111" ;
INST "fpga_0_clk_1_sys_clk_pin" LOC = "IOB_X1Y109" ;
INST "fpga_0_Ethernet_MAC_PHY_rx_clk_pin" LOC = "IOB_X1Y219" ;
INST "fpga_0_Ethernet_MAC_PHY_tx_clk_pin" LOC = "IOB_X1Y217" ;
INST "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin" LOC = "IOB_X1Y105" ;
INST "fpga_0_PCIe_Bridge_RXN_pin" LOC = "IPAD_X1Y12" ;
INST "fpga_0_PCIe_Bridge_RXP_pin" LOC = "IPAD_X1Y13" ;
INST "fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin" LOC = "IPAD_X1Y16" ;
INST "fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin" LOC = "IPAD_X1Y17" ;
INST "fpga_0_PCIe_Bridge_TXN_pin" LOC = "OPAD_X0Y8" ;
INST "fpga_0_PCIe_Bridge_TXP_pin" LOC = "OPAD_X0Y9" ;
INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.pll_adv_i" LOC = "PLL_ADV_X0Y5" ;
INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst" LOC = "PLL_ADV_X0Y0" ;
INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC = "GTX_DUAL_X0Y2" ;
INST "ibufgds_76" LOC = "BUFDS_X0Y2" ;
# clk_125_0000MHzPLL0 driven by BUFGCTRL_X0Y1
NET "clk_125_0000MHzPLL0" TNM_NET = "TN_clk_125_0000MHzPLL0" ;
TIMEGRP "TN_clk_125_0000MHzPLL0" AREA_GROUP = "CLKAG_clk_125_0000MHzPLL0" ;
AREA_GROUP "CLKAG_clk_125_0000MHzPLL0" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
# fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP driven by BUFGCTRL_X0Y30
NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" TNM_NET = "TN_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" ;
TIMEGRP "TN_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" ;
AREA_GROUP "CLKAG_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" RANGE = CLOCKREGION_X0Y2, CLOCKREGION_X0Y3, CLOCKREGION_X0Y4, CLOCKREGION_X0Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk driven by BUFGCTRL_X0Y29
NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" ;
TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" ;
AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;
# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk driven by BUFGCTRL_X0Y27
NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" ;
TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" ;
AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
# clk_125_0000MHzPLL0_ADJUST driven by BUFGCTRL_X0Y2
NET "clk_125_0000MHzPLL0_ADJUST" TNM_NET = "TN_clk_125_0000MHzPLL0_ADJUST" ;
TIMEGRP "TN_clk_125_0000MHzPLL0_ADJUST" AREA_GROUP = "CLKAG_clk_125_0000MHzPLL0_ADJUST" ;
AREA_GROUP "CLKAG_clk_125_0000MHzPLL0_ADJUST" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
# clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6> driven by BUFGCTRL_X0Y3
NET "clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" TNM_NET = "TN_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" ;
TIMEGRP "TN_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" AREA_GROUP = "CLKAG_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" ;
AREA_GROUP "CLKAG_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X0Y1 ;
# PCIe_Bridge/Bridge_Clk driven by BUFGCTRL_X0Y28
NET "PCIe_Bridge/Bridge_Clk" TNM_NET = "TN_PCIe_Bridge/Bridge_Clk" ;
TIMEGRP "TN_PCIe_Bridge/Bridge_Clk" AREA_GROUP = "CLKAG_PCIe_Bridge/Bridge_Clk" ;
AREA_GROUP "CLKAG_PCIe_Bridge/Bridge_Clk" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
# fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP driven by BUFGCTRL_X0Y8
NET "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" TNM_NET = "TN_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" ;
TIMEGRP "TN_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" ;
AREA_GROUP "CLKAG_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" RANGE = CLOCKREGION_X1Y0, CLOCKREGION_X1Y1, CLOCKREGION_X1Y2, CLOCKREGION_X1Y3, CLOCKREGION_X1Y4, CLOCKREGION_X1Y5, CLOCKREGION_X1Y6, CLOCKREGION_X1Y7 ;
# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin driven by BUFGCTRL_X0Y26
NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" ;
TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" ;
AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" RANGE = CLOCKREGION_X0Y6, CLOCKREGION_X0Y7 ;
# clk_200_0000MHz driven by BUFGCTRL_X0Y4
NET "clk_200_0000MHz" TNM_NET = "TN_clk_200_0000MHz" ;
TIMEGRP "TN_clk_200_0000MHz" AREA_GROUP = "CLKAG_clk_200_0000MHz" ;
AREA_GROUP "CLKAG_clk_200_0000MHz" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
# fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF driven by BUFGCTRL_X0Y7
NET "fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" TNM_NET = "TN_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" ;
TIMEGRP "TN_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" AREA_GROUP = "CLKAG_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" ;
AREA_GROUP "CLKAG_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" RANGE = CLOCKREGION_X1Y6, CLOCKREGION_X1Y7 ;
# fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP driven by BUFGCTRL_X0Y31
NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" TNM_NET = "TN_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" ;
TIMEGRP "TN_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" ;
AREA_GROUP "CLKAG_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;
# clk_125_0000MHz90PLL0_ADJUST driven by BUFGCTRL_X0Y5
NET "clk_125_0000MHz90PLL0_ADJUST" TNM_NET = "TN_clk_125_0000MHz90PLL0_ADJUST" ;
TIMEGRP "TN_clk_125_0000MHz90PLL0_ADJUST" AREA_GROUP = "CLKAG_clk_125_0000MHz90PLL0_ADJUST" ;
AREA_GROUP "CLKAG_clk_125_0000MHz90PLL0_ADJUST" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
# clk_62_5000MHzPLL0_ADJUST driven by BUFGCTRL_X0Y6
NET "clk_62_5000MHzPLL0_ADJUST" TNM_NET = "TN_clk_62_5000MHzPLL0_ADJUST" ;
TIMEGRP "TN_clk_62_5000MHzPLL0_ADJUST" AREA_GROUP = "CLKAG_clk_62_5000MHzPLL0_ADJUST" ;
AREA_GROUP "CLKAG_clk_62_5000MHzPLL0_ADJUST" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg driven by BUFGCTRL_X0Y0
NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" ;
TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" ;
AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" RANGE = CLOCKREGION_X0Y6, CLOCKREGION_X0Y7 ;
# NOTE:
# This report is provided to help reproduce successful clock-region
# assignments. The report provides range constraints for all global
# clock networks, in a format that is directly usable in ucf files.
#
#END of Global Clock Net Distribution UCF Constraints
######################################################################################
######################################################################################
GLOBAL CLOCK NET LOADS DISTRIBUTION REPORT:
Number of Global Clock Regions : 16
Number of Global Clock Networks: 15
Clock Region Assignment: SUCCESSFUL
Clock-Region: <CLOCKREGION_X0Y0>
key resource utilizations (used/available): global-clocks - 2/10 ;
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)
FIFO | | | | | | | | | | | | | |
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
12 | 0 | 0 | 0 | 80 | 80 | 0 | 0 | 0 | 0 | 2 | 0 | 1600 | 3200 | <- (Available Resources in this Region)
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
| | | | | | | | | | | | | | <Global clock Net Name>
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 44 | 548 |PCIe_Bridge/Bridge_Clk
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 202 |clk_125_0000MHzPLL0_ADJUST
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 46 | 750 | Total
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
Clock-Region: <CLOCKREGION_X1Y0>
key resource utilizations (used/available): global-clocks - 2/10 ;
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)
FIFO | | | | | | | | | | | | | |
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
8 | 0 | 0 | 0 | 40 | 40 | 16 | 0 | 0 | 1 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
| | | | | | | | | | | | | | <Global clock Net Name>
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 38 | 934 |PCIe_Bridge/Bridge_Clk
4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 24 | 52 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 62 | 986 | Total
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
Clock-Region: <CLOCKREGION_X0Y1>
key resource utilizations (used/available): global-clocks - 6/10 ;
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)
FIFO | | | | | | | | | | | | | |
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
12 | 4 | 2 | 0 | 40 | 40 | 0 | 0 | 0 | 0 | 1 | 0 | 1600 | 3200 | <- (Available Resources in this Region)
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
| | | | | | | | | | | | | | <Global clock Net Name>
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13 | 195 |PCIe_Bridge/Bridge_Clk
0 | 0 | 0 | 0 | 0 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |clk_125_0000MHz90PLL0_ADJUST
0 | 1 | 0 | 0 | 0 | 17 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 719 |clk_125_0000MHzPLL0_ADJUST
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |clk_200_0000MHz
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 |clk_62_5000MHzPLL0_ADJUST
0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
0 | 1 | 1 | 0 | 0 | 35 | 0 | 0 | 0 | 0 | 1 | 0 | 17 | 918 | Total
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
Clock-Region: <CLOCKREGION_X1Y1>
key resource utilizations (used/available): global-clocks - 4/10 ;
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)
FIFO | | | | | | | | | | | | | |
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
8 | 0 | 0 | 0 | 40 | 40 | 16 | 0 | 0 | 0 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
| | | | | | | | | | | | | | <Global clock Net Name>
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 6 | 500 |PCIe_Bridge/Bridge_Clk
1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 20 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11 | 364 |clk_125_0000MHzPLL0_ADJUST
0 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
1 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 17 | 884 | Total
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
Clock-Region: <CLOCKREGION_X0Y2>
key resource utilizations (used/available): global-clocks - 5/10 ;
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)
FIFO | | | | | | | | | | | | | |
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
12 | 2 | 1 | 0 | 60 | 60 | 0 | 0 | 0 | 0 | 2 | 0 | 1600 | 3200 | <- (Available Resources in this Region)
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
| | | | | | | | | | | | | | <Global clock Net Name>
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |PCIe_Bridge/Bridge_Clk
0 | 0 | 0 | 0 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 17 |clk_125_0000MHz90PLL0_ADJUST
5 | 0 | 0 | 0 | 9 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 58 | 913 |clk_125_0000MHzPLL0_ADJUST
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |clk_200_0000MHz
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 142 |clk_62_5000MHzPLL0_ADJUST
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
7 | 0 | 0 | 0 | 9 | 42 | 0 | 0 | 0 | 0 | 1 | 0 | 58 | 1072 | Total
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
Clock-Region: <CLOCKREGION_X1Y2>
key resource utilizations (used/available): global-clocks - 4/10 ;
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)
FIFO | | | | | | | | | | | | | |
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
8 | 0 | 0 | 0 | 40 | 40 | 16 | 0 | 0 | 1 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
| | | | | | | | | | | | | | <Global clock Net Name>
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 94 | 387 |PCIe_Bridge/Bridge_Clk
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 81 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk
0 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 36 | 500 |clk_125_0000MHzPLL0_ADJUST
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
0 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 130 | 970 | Total
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
Clock-Region: <CLOCKREGION_X0Y3>
key resource utilizations (used/available): global-clocks - 4/10 ;
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)
FIFO | | | | | | | | | | | | | |
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
4 | 0 | 0 | 0 | 60 | 60 | 0 | 0 | 1 | 0 | 2 | 16 | 640 | 1280 | <- (Available Resources in this Region)
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
| | | | | | | | | | | | | | <Global clock Net Name>
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 83 |clk_125_0000MHz90PLL0_ADJUST
0 | 0 | 0 | 0 | 8 | 17 | 0 | 0 | 1 | 0 | 0 | 0 | 36 | 272 |clk_125_0000MHzPLL0_ADJUST
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 |clk_200_0000MHz
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 154 |clk_62_5000MHzPLL0_ADJUST
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
0 | 0 | 0 | 0 | 8 | 17 | 0 | 0 | 1 | 0 | 0 | 0 | 36 | 512 | Total
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
Clock-Region: <CLOCKREGION_X1Y3>
key resource utilizations (used/available): global-clocks - 3/10 ;
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)
FIFO | | | | | | | | | | | | | |
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
8 | 0 | 0 | 0 | 40 | 40 | 16 | 0 | 0 | 0 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
| | | | | | | | | | | | | | <Global clock Net Name>
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 44 | 290 |PCIe_Bridge/Bridge_Clk
6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 22 | 659 |clk_125_0000MHzPLL0_ADJUST
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 66 | 950 | Total
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
Clock-Region: <CLOCKREGION_X0Y4>
key resource utilizations (used/available): global-clocks - 5/10 ;
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)
FIFO | | | | | | | | | | | | | |
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
4 | 0 | 0 | 0 | 60 | 60 | 0 | 0 | 1 | 0 | 2 | 16 | 640 | 1280 | <- (Available Resources in this Region)
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
| | | | | | | | | | | | | | <Global clock Net Name>
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |PCIe_Bridge/Bridge_Clk
2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 34 |clk_125_0000MHz90PLL0_ADJUST
4 | 0 | 0 | 0 | 1 | 20 | 0 | 0 | 0 | 0 | 0 | 0 | 16 | 231 |clk_125_0000MHzPLL0_ADJUST
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 200 |clk_62_5000MHzPLL0_ADJUST
0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
6 | 0 | 0 | 0 | 7 | 20 | 0 | 0 | 0 | 0 | 0 | 0 | 18 | 466 | Total
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
Clock-Region: <CLOCKREGION_X1Y4>
key resource utilizations (used/available): global-clocks - 3/10 ;
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)
FIFO | | | | | | | | | | | | | |
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
10 | 0 | 0 | 0 | 40 | 40 | 16 | 1 | 0 | 0 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
| | | | | | | | | | | | | | <Global clock Net Name>
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 54 | 367 |PCIe_Bridge/Bridge_Clk
3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 20 | 602 |clk_125_0000MHzPLL0_ADJUST
0 | 0 | 0 | 0 | 16 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 16 |fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3 | 0 | 0 | 0 | 16 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 74 | 985 | Total
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
Clock-Region: <CLOCKREGION_X0Y5>
key resource utilizations (used/available): global-clocks - 4/10 ;
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)
FIFO | | | | | | | | | | | | | |
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
12 | 2 | 1 | 0 | 60 | 60 | 0 | 0 | 0 | 0 | 2 | 0 | 1600 | 3200 | <- (Available Resources in this Region)
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
| | | | | | | | | | | | | | <Global clock Net Name>
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 2 |PCIe_Bridge/Bridge_Clk
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 48 |clk_125_0000MHz90PLL0_ADJUST
0 | 0 | 0 | 0 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 16 | 517 |clk_125_0000MHzPLL0_ADJUST
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 206 |clk_62_5000MHzPLL0_ADJUST
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
0 | 0 | 0 | 0 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 28 | 773 | Total
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
Clock-Region: <CLOCKREGION_X1Y5>
key resource utilizations (used/available): global-clocks - 3/10 ;
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)
FIFO | | | | | | | | | | | | | |
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
10 | 0 | 0 | 0 | 40 | 40 | 16 | 1 | 0 | 0 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
| | | | | | | | | | | | | | <Global clock Net Name>
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 68 | 285 |PCIe_Bridge/Bridge_Clk
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 50 | 333 |clk_125_0000MHzPLL0_ADJUST
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 21 |fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 118 | 639 | Total
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
Clock-Region: <CLOCKREGION_X0Y6>
key resource utilizations (used/available): global-clocks - 7/10 ;
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)
FIFO | | | | | | | | | | | | | |
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
12 | 4 | 2 | 0 | 40 | 40 | 0 | 0 | 0 | 0 | 1 | 0 | 1600 | 3200 | <- (Available Resources in this Region)
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
| | | | | | | | | | | | | | <Global clock Net Name>
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg
0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin
0 | 0 | 0 | 0 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 |clk_125_0000MHz90PLL0_ADJUST
0 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 10 | 605 |clk_125_0000MHzPLL0_ADJUST
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |clk_200_0000MHz
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 158 |clk_62_5000MHzPLL0_ADJUST
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 12 |fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
0 | 0 | 2 | 0 | 0 | 35 | 0 | 0 | 0 | 0 | 1 | 0 | 27 | 777 | Total
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
Clock-Region: <CLOCKREGION_X1Y6>
key resource utilizations (used/available): global-clocks - 2/10 ;
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)
FIFO | | | | | | | | | | | | | |
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
8 | 0 | 0 | 0 | 40 | 40 | 16 | 0 | 0 | 1 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
| | | | | | | | | | | | | | <Global clock Net Name>
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 103 |PCIe_Bridge/Bridge_Clk
0 | 0 | 0 | 0 | 19 | 23 | 0 | 0 | 0 | 0 | 0 | 0 | 22 | 413 |clk_125_0000MHzPLL0_ADJUST
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
0 | 0 | 0 | 0 | 19 | 23 | 0 | 0 | 0 | 0 | 0 | 0 | 26 | 516 | Total
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
Clock-Region: <CLOCKREGION_X0Y7>
key resource utilizations (used/available): global-clocks - 2/10 ;
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)
FIFO | | | | | | | | | | | | | |
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
12 | 0 | 0 | 0 | 80 | 80 | 0 | 0 | 0 | 0 | 2 | 0 | 1600 | 3200 | <- (Available Resources in this Region)
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
| | | | | | | | | | | | | | <Global clock Net Name>
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 16 | 495 |clk_125_0000MHzPLL0_ADJUST
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 19 |clk_62_5000MHzPLL0_ADJUST
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 16 | 514 | Total
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
Clock-Region: <CLOCKREGION_X1Y7>
key resource utilizations (used/available): global-clocks - 1/10 ;
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
BRAM | DCM | PLL | GT | ILOGIC | OLOGIC | MULT | TEMAC | PPC | PCIE | IDLYCT | BUFGCT | LUT | FF | <- (Types of Resources in this Region)
FIFO | | | | | | | | | | | | | |
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
8 | 0 | 0 | 0 | 40 | 40 | 16 | 0 | 0 | 0 | 1 | 0 | 1920 | 2880 | <- (Available Resources in this Region)
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
| | | | | | | | | | | | | | <Global clock Net Name>
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 46 | 327 |clk_125_0000MHzPLL0_ADJUST
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 46 | 327 | Total
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
NOTE:
The above detailed report is the initial placement of the logic after the clock region assignment. The final placement
may be significantly different because of the various optimization steps which will follow. Specifically, logic blocks
maybe moved to adjacent clock-regions as long as the "number of clocks per region" constraint is not violated.
# END of Global Clock Net Loads Distribution Report:
######################################################################################
Phase 9.30 Global Clock Region Assignment (Checksum:7e049af9) REAL time: 10 mins 42 secs
Phase 10.3 Local Placement Optimization
Phase 10.3 Local Placement Optimization (Checksum:7e049af9) REAL time: 10 mins 43 secs
Phase 11.5 Local Placement Optimization
Phase 11.5 Local Placement Optimization (Checksum:7e049af9) REAL time: 10 mins 45 secs
Phase 12.8 Global Placement
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Phase 12.8 Global Placement (Checksum:4ba01660) REAL time: 15 mins 18 secs
Phase 13.29 Local Placement Optimization
Phase 13.29 Local Placement Optimization (Checksum:4ba01660) REAL time: 15 mins 18 secs
Phase 14.5 Local Placement Optimization
Phase 14.5 Local Placement Optimization (Checksum:4ba01660) REAL time: 15 mins 22 secs
Phase 15.18 Placement Optimization
Phase 15.18 Placement Optimization (Checksum:f81b02a1) REAL time: 18 mins 1 secs
Phase 16.5 Local Placement Optimization
Phase 16.5 Local Placement Optimization (Checksum:f81b02a1) REAL time: 18 mins 3 secs
Phase 17.34 Placement Validation
Phase 17.34 Placement Validation (Checksum:f81b02a1) REAL time: 18 mins 5 secs
Total REAL time to Placer completion: 18 mins 7 secs
Total CPU time to Placer completion: 17 mins 4 secs
Running post-placement packing...
Writing output files...
Design Summary:
Number of errors: 0
Number of warnings: 50
Slice Logic Utilization:
Number of Slice Registers: 12,128 out of 44,800 27%
Number used as Flip Flops: 12,127
Number used as Latches: 1
Number of Slice LUTs: 12,266 out of 44,800 27%
Number used as logic: 11,767 out of 44,800 26%
Number using O6 output only: 10,791
Number using O5 output only: 282
Number using O5 and O6: 694
Number used as Memory: 392 out of 13,120 2%
Number used as Dual Port RAM: 56
Number using O6 output only: 12
Number using O5 and O6: 44
Number used as Single Port RAM: 4
Number using O6 output only: 4
Number used as Shift Register: 332
Number using O6 output only: 332
Number used as exclusive route-thru: 107
Number of route-thrus: 438
Number using O6 output only: 382
Number using O5 output only: 51
Number using O5 and O6: 5
Slice Logic Distribution:
Number of occupied Slices: 6,488 out of 11,200 57%
Number of LUT Flip Flop pairs used: 17,046
Number with an unused Flip Flop: 4,918 out of 17,046 28%
Number with an unused LUT: 4,780 out of 17,046 28%
Number of fully used LUT-FF pairs: 7,348 out of 17,046 43%
Number of unique control sets: 1,288
Number of slice register sites lost
to control set restrictions: 3,000 out of 44,800 6%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
OVERMAPPING of BRAM resources should be ignored if the design is
over-mapped for a non-BRAM resource or if placement fails.
IO Utilization:
Number of bonded IOBs: 255 out of 640 39%
Number of LOCed IOBs: 255 out of 255 100%
IOB Flip Flops: 494
Number of bonded IPADs: 4 out of 50 8%
Number of bonded OPADs: 2 out of 32 6%
Specific Feature Utilization:
Number of BlockRAM/FIFO: 23 out of 148 15%
Number using BlockRAM only: 21
Number using FIFO only: 2
Total primitives used:
Number of 36k BlockRAM used: 16
Number of 18k BlockRAM used: 6
Number of 36k FIFO used: 2
Total Memory used (KB): 756 out of 5,328 14%
Number of BUFG/BUFGCTRLs: 15 out of 32 46%
Number used as BUFGs: 15
Number of IDELAYCTRLs: 3 out of 22 13%
Number of BUFDSs: 1 out of 8 12%
Number of BUFIOs: 8 out of 80 10%
Number of DCM_ADVs: 1 out of 12 8%
Number of GTX_DUALs: 1 out of 8 12%
Number of PCIEs: 1 out of 3 33%
Number of LOCed PCIEs: 1 out of 1 100%
Number of PLL_ADVs: 2 out of 6 33%
Number of PPC440s: 1 out of 1 100%
Number of RPM macros: 64
Average Fanout of Non-Clock Nets: 3.76
Peak Memory Usage: 701 MB
Total REAL time to MAP completion: 18 mins 45 secs
Total CPU time to MAP completion: 17 mins 40 secs
Mapping completed.
See MAP report file "system_map.mrp" for details.
#----------------------------------------------#
# Starting program par
# par -ise ../__xps/ise/system.ise -w -ol high system_map.ncd system.ncd
system.pcf
#----------------------------------------------#
Release 11.2 - par L.46 (nt)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file <C:/devtools/Xilinx/11.1/EDK/data/parBmgr.acd> with local file
<c:/devtools/Xilinx/11.1/ISE/data/parBmgr.acd>
Loading device for application Rf_Device from file '5vfx70t.nph' in environment
c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.
"system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1
Constraints file: system.pcf.
"system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1
WARNING:ConstraintSystem:65 - Constraint <NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(65973)]
overrides constraint <NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(65972)].
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)
WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP
"TNM_CLK0" TS_MC_CLK * 4; ignored during timing analysis.
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please
consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.
Device speed data version: "PRODUCTION 1.65 2009-06-01".
Device Utilization Summary:
Number of BUFDSs 1 out of 8 12%
Number of BUFGs 15 out of 32 46%
Number of BUFIOs 8 out of 80 10%
Number of DCM_ADVs 1 out of 12 8%
Number of FIFO36_72_EXPs 2 out of 148 1%
Number of LOCed FIFO36_72_EXPs 2 out of 2 100%
Number of GTX_DUALs 1 out of 8 12%
Number of IDELAYCTRLs 3 out of 22 13%
Number of LOCed IDELAYCTRLs 3 out of 3 100%
Number of ILOGICs 131 out of 800 16%
Number of LOCed ILOGICs 8 out of 131 6%
Number of External IOBs 255 out of 640 39%
Number of LOCed IOBs 255 out of 255 100%
Number of IODELAYs 80 out of 800 10%
Number of LOCed IODELAYs 8 out of 80 10%
Number of External IPADs 4 out of 690 1%
Number of LOCed IPADs 4 out of 4 100%
Number of JTAGPPCs 1 out of 1 100%
Number of OLOGICs 236 out of 800 29%
Number of External OPADs 2 out of 32 6%
Number of LOCed OPADs 2 out of 2 100%
Number of PCIEs 1 out of 3 33%
Number of LOCed PCIEs 1 out of 1 100%
Number of PLL_ADVs 2 out of 6 33%
Number of PPC440s 1 out of 1 100%
Number of RAMB18X2SDPs 5 out of 148 3%
Number of RAMB36SDP_EXPs 6 out of 148 4%
Number of LOCed RAMB36SDP_EXPs 1 out of 6 16%
Number of RAMB36_EXPs 10 out of 148 6%
Number of LOCed RAMB36_EXPs 6 out of 10 60%
Number of Slice Registers 12128 out of 44800 27%
Number used as Flip Flops 12127
Number used as Latches 1
Number used as LatchThrus 0
Number of Slice LUTS 12266 out of 44800 27%
Number of Slice LUT-Flip Flop pairs 17046 out of 44800 38%
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 51 secs
Finished initial Timing Analysis. REAL time: 52 secs
WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n<0> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn<0> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal xps_bram_if_cntlr_1_port_BRAM_Addr<30> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal xps_bram_if_cntlr_1_port_BRAM_Addr<31> has no load. PAR will not attempt to route this
signal.
WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull has no load. PAR will not attempt to route this
signal.
Starting Router
INFO:Route:501 - One or more directed routing (DIRT) constraints generated for a specific device have been found. Note
that DIRT strings are guaranteed to work only on the same device they were created for. If the DIRT constraints fail,
verify that the same connectivity is available in the target device for this implementation.
Phase 1 : 82160 unrouted; REAL time: 1 mins 9 secs
Phase 2 : 72970 unrouted; REAL time: 1 mins 22 secs
Phase 3 : 28783 unrouted; REAL time: 3 mins 31 secs
Phase 4 : 28815 unrouted; (Setup:0, Hold:103206, Component Switching Limit:0) REAL time: 3 mins 57 secs
Updating file: system.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:103693, Component Switching Limit:0) REAL time: 5 mins 9 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:103693, Component Switching Limit:0) REAL time: 5 mins 9 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:103693, Component Switching Limit:0) REAL time: 5 mins 9 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:103693, Component Switching Limit:0) REAL time: 5 mins 9 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 7 mins 25 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 7 mins 57 secs
Total REAL time to Router completion: 7 mins 57 secs
Total CPU time to Router completion: 7 mins 31 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|clk_125_0000MHzPLL0_ | | | | | |
| ADJUST | BUFGCTRL_X0Y2| No | 3176 | 0.533 | 2.076 |
+---------------------+--------------+------+------+------------+-------------+
|PCIe_Bridge/Bridge_C | | | | | |
| lk |BUFGCTRL_X0Y28| No | 1481 | 0.519 | 2.085 |
+---------------------+--------------+------+------+------------+-------------+
|clk_62_5000MHzPLL0_A | | | | | |
| DJUST | BUFGCTRL_X0Y6| No | 501 | 0.313 | 2.062 |
+---------------------+--------------+------+------+------------+-------------+
|clk_125_0000MHz90PLL | | | | | |
| 0_ADJUST | BUFGCTRL_X0Y5| No | 165 | 0.262 | 2.028 |
+---------------------+--------------+------+------+------------+-------------+
|PCIe_Bridge/PCIe_Bri | | | | | |
|dge/comp_block_plus/ | | | | | |
|comp_endpoint/core_c | | | | | |
| lk |BUFGCTRL_X0Y27| No | 92 | 0.338 | 2.085 |
+---------------------+--------------+------+------+------------+-------------+
|fpga_0_SysACE_Compac | | | | | |
|tFlash_SysACE_CLK_pi | | | | | |
| n_BUFGP | BUFGCTRL_X0Y8| No | 55 | 0.171 | 1.797 |
+---------------------+--------------+------+------+------------+-------------+
|PCIe_Bridge/PCIe_Bri | | | | | |
|dge/comp_block_plus/ | | | | | |
|comp_endpoint/pcie_b | | | | | |
| lk/gt_usrclk |BUFGCTRL_X0Y29| No | 6 | 0.065 | 1.886 |
+---------------------+--------------+------+------+------------+-------------+
|fpga_0_Ethernet_MAC_ | | | | | |
|PHY_rx_clk_pin_BUFGP | | | | | |
| |BUFGCTRL_X0Y30| No | 12 | 0.086 | 1.874 |
+---------------------+--------------+------+------+------------+-------------+
|fpga_0_Ethernet_MAC_ | | | | | |
|PHY_tx_clk_pin_BUFGP | | | | | |
| |BUFGCTRL_X0Y31| No | 6 | 0.004 | 1.941 |
+---------------------+--------------+------+------+------------+-------------+
|DDR2_SDRAM/DDR2_SDRA | | | | | |
|M/u_ddr2_top/u_mem_i | | | | | |
|f_top/u_phy_top/u_ph | | | | | |
| y_io/delayed_dqs<0> | IO Clk| No | 18 | 0.095 | 0.419 |
+---------------------+--------------+------+------+------------+-------------+
|DDR2_SDRAM/DDR2_SDRA | | | | | |
|M/u_ddr2_top/u_mem_i | | | | | |
|f_top/u_phy_top/u_ph | | | | | |
| y_io/delayed_dqs<1> | IO Clk| No | 18 | 0.083 | 0.380 |
+---------------------+--------------+------+------+------------+-------------+
|DDR2_SDRAM/DDR2_SDRA | | | | | |
|M/u_ddr2_top/u_mem_i | | | | | |
|f_top/u_phy_top/u_ph | | |
| | |
| y_io/delayed_dqs<2> | IO Clk| No | 18 | 0.101 | 0.425 |
+---------------------+--------------+------+------+------------+-------------+
|DDR2_SDRAM/DDR2_SDRA | | | | | |
|M/u_ddr2_top/u_mem_i | | | | | |
|f_top/u_phy_top/u_ph | | | | | |
| y_io/delayed_dqs<3> | IO Clk| No | 18 | 0.107 | 0.404 |
+---------------------+--------------+------+------+------------+-------------+
|DDR2_SDRAM/DDR2_SDRA | | | | | |
|M/u_ddr2_top/u_mem_i | | | | | |
|f_top/u_phy_top/u_ph | | | | | |
| y_io/delayed_dqs<5> | IO Clk| No | 18 | 0.101 | 0.425 |
+---------------------+--------------+------+------+------------+-------------+
|DDR2_SDRAM/DDR2_SDRA | | | | | |
|M/u_ddr2_top/u_mem_i | | | | | |
|f_top/u_phy_top/u_ph | | | | | |
| y_io/delayed_dqs<4> | IO Clk| No | 18 | 0.101 | 0.425 |
+---------------------+--------------+------+------+------------+-------------+
|DDR2_SDRAM/DDR2_SDRA | | | | | |
|M/u_ddr2_top/u_mem_i | | | | | |
|f_top/u_phy_top/u_ph | | | | | |
| y_io/delayed_dqs<6> | IO Clk| No | 18 | 0.096 | 0.393 |
+---------------------+--------------+------+------+------------+-------------+
|DDR2_SDRAM/DDR2_SDRA | | | | | |
|M/u_ddr2_top/u_mem_i | | | | | |
|f_top/u_phy_top/u_ph | | | | | |
| y_io/delayed_dqs<7> | IO Clk| No | 18 | 0.101 | 0.425 |
+---------------------+--------------+------+------+------------+-------------+
| clk_125_0000MHzPLL0 | BUFGCTRL_X0Y1| No | 2 | 0.000 | 1.739 |
+---------------------+--------------+------+------+------------+-------------+
| clk_200_0000MHz | BUFGCTRL_X0Y4| No | 4 | 0.100 | 1.879 |
+---------------------+--------------+------+------+------------+-------------+
|RS232_Uart_1_Interru | | | | | |
| pt | Local| | 1 | 0.000 | 0.625 |
+---------------------+--------------+------+------+------------+-------------+
|PCIe_Bridge/PCIe_Bri | | | | | |
|dge/comp_block_plus/ | | | | | |
|comp_endpoint/pcie_b | | | | | |
|lk/SIO/.pcie_gt_wrap | | | | | |
| per_i/icdrreset<0> | Local| | 1 | 0.000 | 0.590 |
+---------------------+--------------+------+------+------------+-------------+
|Ethernet_MAC/Etherne | | | | | |
| t_MAC/phy_tx_clk_i | Local| | 9 | 3.273 | 3.994 |
+---------------------+--------------+------+------+------------+-------------+
|ppc440_0_jtagppc_bus | | | | | |
| _JTGC405TCK | Local| | 1 | 0.000 | 1.699 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Number of Timing Constraints that were not applied: 5
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 n | SETUP | 0.026ns| 7.974ns| 0| 0
s HIGH 50% | HOLD | 0.030ns| | 0| 0
| MINPERIOD | 0.000ns| 8.000ns| 0| 0
------------------------------------------------------------------------------------------------------
NET "PCIe_Bridge/PCIe_Bridge/comp_block_p | SETUP | 0.026ns| 3.974ns| 0| 0
lus/comp_endpoint/core_clk" PERIOD = | HOLD | 0.315ns| | 0| 0
4 ns HIGH 50% | MINPERIOD | 0.000ns| 4.000ns| 0| 0
------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.012ns| 0.838ns| 0| 0
_top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | |
dqs[7].u_iob_dqs/en_dqs_sync" MAX | | | | |
DELAY = 0.85 ns | | | | |
------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.015ns| 0.835ns| 0| 0
_top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | |
dqs[0].u_iob_dqs/en_dqs_sync" MAX | | | | |
DELAY = 0.85 ns | | | | |
------------------------------------------------------------------------------------------------------
TS_DQ_CE = MAXDELAY FROM TIMEGRP "TNM_DQ_ | SETUP | 0.021ns| 1.879ns| 0| 0
CE_IDDR" TO TIMEGRP "TNM_DQS_FLOPS" | HOLD | 1.026ns| | 0| 0
1.9 ns | | | | |
------------------------------------------------------------------------------------------------------
TS_clock_generator_0_clock_generator_0_PL | SETUP | 0.027ns| 7.973ns| 0| 0
L0_CLK_OUT_2_ = PERIOD TIMEGRP "c | HOLD | 0.021ns| | 0| 0
lock_generator_0_clock_generator_0_PLL0_C | | | | |
LK_OUT_2_" TS_sys_clk_pin * 1.25 | | | | |
HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.045ns| 0.805ns| 0| 0
_top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | |
dqs[1].u_iob_dqs/en_dqs_sync" MAX | | | | |
DELAY = 0.85 ns | | | | |
------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.045ns| 0.805ns| 0| 0
_top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | |
dqs[5].u_iob_dqs/en_dqs_sync" MAX | | | | |
DELAY = 0.85 ns | | | | |
------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.047ns| 0.803ns| 0| 0
_top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | |
dqs[2].u_iob_dqs/en_dqs_sync" MAX | | | | |
DELAY = 0.85 ns | | | | |
------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.047ns| 0.803ns| 0| 0
_top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | |
dqs[3].u_iob_dqs/en_dqs_sync" MAX | | | | |
DELAY = 0.85 ns | | | | |
------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.047ns| 0.803ns| 0| 0
_top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | |
dqs[4].u_iob_dqs/en_dqs_sync" MAX | | | | |
DELAY = 0.85 ns | | | | |
------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.047ns| 0.803ns| 0| 0
_top/u_mem_if_top/u_phy_top/u_phy_io/gen_ | | | | |
dqs[6].u_iob_dqs/en_dqs_sync" MAX | | | | |
DELAY = 0.85 ns | | | | |
------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.068ns| 0.532ns| 0| 0
_top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | |
qs<1>" MAXDELAY = 0.6 ns | | | | |
------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0
_top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | |
qs<0>" MAXDELAY = 0.6 ns | | | | |
------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0
_top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | |
qs<2>" MAXDELAY = 0.6 ns | | | | |
------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0
_top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | |
qs<3>" MAXDELAY = 0.6 ns | | | | |
------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0
_top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | |
qs<4>" MAXDELAY = 0.6 ns | | | | |
------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0
_top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | |
qs<5>" MAXDELAY = 0.6 ns | | | | |
------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0
_top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | |
qs<6>" MAXDELAY = 0.6 ns | | | | |
------------------------------------------------------------------------------------------------------
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY | 0.071ns| 0.529ns| 0| 0
_top/u_mem_if_top/u_phy_top/u_phy_io/en_d | | | | |
qs<7>" MAXDELAY = 0.6 ns | | | | |
------------------------------------------------------------------------------------------------------
TS_PCIe_PLB = MAXDELAY FROM TIMEGRP "Brid | SETUP | 0.188ns| 7.812ns| 0| 0
ge_Clk" TO TIMEGRP "SPLB_Clk" 8 ns | HOLD | 0.516ns| | 0| 0
DATAPATHONLY | | | | |
------------------------------------------------------------------------------------------------------
TS_MC_CLK = PERIOD TIMEGRP "mc_clk" 5 ns | MINPERIOD | 1.010ns| 3.990ns| 0| 0
HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_PLB_PCIe = MAXDELAY FROM TIMEGRP "SPLB | SETUP | 1.252ns| 6.748ns| 0| 0
_Clk" TO TIMEGRP "Bridge_Clk" 8 ns | HOLD | 0.451ns| | 0| 0
DATAPATHONLY | | | | |
------------------------------------------------------------------------------------------------------
TSRXIN_Ethernet_MAC = MAXDELAY FROM TIMEG | MAXDELAY | 1.700ns| 4.300ns| 0| 0
RP "PADS" TO TIMEGRP "RXCLK_GRP_E | HOLD | 1.060ns| | 0| 0
thernet_MAC" 6 ns | | | | |
------------------------------------------------------------------------------------------------------
TS_clock_generator_0_clock_generator_0_PL | SETUP | 2.073ns| 5.466ns| 0| 0
L0_CLK_OUT_0_ = PERIOD TIMEGRP "c | HOLD | 0.307ns| | 0| 0
lock_generator_0_clock_generator_0_PLL0_C | | | | |
LK_OUT_0_" TS_sys_clk_pin * 1.25 | | | | |
PHASE 2 ns HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | MINLOWPULSE | 6.000ns| 4.000ns| 0| 0
pin" 100 MHz HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_clock_generator_0_clock_generator_0_PL | SETUP | 3.700ns| 8.600ns| 0| 0
L0_CLK_OUT_4_ = PERIOD TIMEGRP "c | HOLD | 0.153ns| | 0| 0
lock_generator_0_clock_generator_0_PLL0_C | | | | |
LK_OUT_4_" TS_sys_clk_pin * 0.625 | | | | |
HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TS_clock_generator_0_clock_generator_0_PL | SETUP | 3.950ns| 1.050ns| 0| 0
L0_CLK_OUT_3_ = PERIOD TIMEGRP "c | HOLD | 0.465ns| | 0| 0
lock_generator_0_clock_generator_0_PLL0_C | MINLOWPULSE | 3.946ns| 1.054ns| 0| 0
LK_OUT_3_" TS_sys_clk_pin * 2 HIG | | | | |
H 50% | | | | |
------------------------------------------------------------------------------------------------------
NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_B | NETSKEW | 4.392ns| 0.608ns| 0| 0
UFGP" MAXSKEW = 5 ns | | | | |
------------------------------------------------------------------------------------------------------
NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_B | NETSKEW | 4.789ns| 0.211ns| 0| 0
UFGP" MAXSKEW = 5 ns | | | | |
------------------------------------------------------------------------------------------------------
TS_clock_generator_0_clock_generator_0_PL | MINPERIOD | 4.900ns| 3.100ns| 0| 0
L0_CLK_OUT_1_ = PERIOD TIMEGRP "c | | | | |
lock_generator_0_clock_generator_0_PLL0_C | | | | |
LK_OUT_1_" TS_sys_clk_pin * 1.25 | | | | |
HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
TSTXOUT_Ethernet_MAC = MAXDELAY FROM TIME | MAXDELAY | 7.423ns| 2.577ns| 0| 0
GRP "TXCLK_GRP_Ethernet_MAC" TO T | | | | |
IMEGRP "PADS" 10 ns | | | | |
------------------------------------------------------------------------------------------------------
NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_B | SETUP | 10.092ns| 11.165ns| 0| 0
UFGP" PERIOD = 40 ns HIGH 14 ns | HOLD | 0.473ns| | 0| 0
------------------------------------------------------------------------------------------------------
TS_MC_PHY_INIT_DATA_SEL_90 = MAXDELAY FRO | SETUP | 13.832ns| 6.168ns| 0| 0
M TIMEGRP "TNM_PHY_INIT_DATA_SEL" TO | HOLD | 0.471ns| | 0| 0
TIMEGRP "TNM_CLK90" TS_MC_CLK * 4 | | | | |
------------------------------------------------------------------------------------------------------
TS_MC_PHY_INIT_DATA_SEL_0 = MAXDELAY FROM | SETUP | 16.202ns| 3.798ns| 0| 0
TIMEGRP "TNM_PHY_INIT_DATA_SEL" TO | HOLD | 0.049ns| | 0| 0
TIMEGRP "TNM_CLK0" TS_MC_CLK * 4 | | | | |
------------------------------------------------------------------------------------------------------
TS_MC_RDEN_DLY = MAXDELAY FROM TIMEGRP "T | SETUP | 17.943ns| 2.057ns| 0| 0
NM_RDEN_DLY" TO TIMEGRP "TNM_CLK0" | HOLD | 0.295ns| | 0| 0
TS_MC_CLK * 4 | | | | |
------------------------------------------------------------------------------------------------------
TS_MC_GATE_DLY = MAXDELAY FROM TIMEGRP "T | SETUP | 17.975ns| 2.025ns| 0| 0
NM_GATE_DLY" TO TIMEGRP "TNM_CLK0" | HOLD | 0.030ns| | 0| 0
TS_MC_CLK * 4 | | | | |
------------------------------------------------------------------------------------------------------
TS_MC_CAL_RDEN_DLY = MAXDELAY FROM TIMEGR | SETUP | 18.085ns| 1.915ns| 0| 0
P "TNM_CAL_RDEN_DLY" TO TIMEGRP " | HOLD | 0.096ns| | 0| 0
TNM_CLK0" TS_MC_CLK * 4 | | | | |
------------------------------------------------------------------------------------------------------
NET "fpga_0_SysACE_CompactFlash_SysACE_CL | SETUP | 26.710ns| 3.290ns| 0| 0
K_pin_BUFGP/IBUFG" PERIOD = 30 ns | HOLD | 0.465ns| | 0| 0
HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_B | SETUP | 32.431ns| 7.569ns| 0| 0
UFGP" PERIOD = 40 ns HIGH 14 ns | HOLD | 0.351ns| | 0| 0
------------------------------------------------------------------------------------------------------
Pin to Pin Skew Constraint | MAXDELAY | 2106523.523ns| 2106523.837ns| 0| 0
------------------------------------------------------------------------------------------------------
TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGR | N/A | N/A| N/A| N/A| N/A
P "TNM_RDEN_SEL_MUX" TO TIMEGRP " | | | | |
TNM_CLK0" TS_MC_CLK * 4 | | | | |
------------------------------------------------------------------------------------------------------
NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 n | N/A | N/A| N/A| N/A| N/A
s HIGH 50% | | | | |
------------------------------------------------------------------------------------------------------
Derived Constraint Report
Derived Constraints for TS_MC_CLK
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_MC_CLK | 5.000ns| 3.990ns| 1.542ns| 0| 0| 0| 345|
| TS_MC_PHY_INIT_DATA_SEL_0 | 20.000ns| 3.798ns| N/A| 0| 0| 21| 0|
| TS_MC_PHY_INIT_DATA_SEL_90 | 20.000ns| 6.168ns| N/A| 0| 0| 274| 0|
| TS_MC_GATE_DLY | 20.000ns| 2.025ns| N/A| 0| 0| 40| 0|
| TS_MC_RDEN_DLY | 20.000ns| 2.057ns| N/A| 0| 0| 5| 0|
| TS_MC_CAL_RDEN_DLY | 20.000ns| 1.915ns| N/A| 0| 0| 5| 0|
| TS_MC_RDEN_SEL_MUX | 20.000ns| N/A| N/A| 0| 0| 0| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_sys_clk_pin
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_sys_clk_pin | 10.000ns| 4.000ns| 9.966ns| 0| 0| 0| 636358|
| TS_clock_generator_0_clock_gen| 8.000ns| 5.466ns| N/A| 0| 0| 626| 0|
| erator_0_PLL0_CLK_OUT_0_ | | | | | | | |
| TS_clock_generator_0_clock_gen| 8.000ns| 3.100ns| N/A| 0| 0| 0| 0|
| erator_0_PLL0_CLK_OUT_1_ | | | | | | | |
| TS_clock_generator_0_clock_gen| 8.000ns| 7.973ns| N/A| 0| 0| 624688| 0|
| erator_0_PLL0_CLK_OUT_2_ | | | | | | | |
| TS_clock_generator_0_clock_gen| 5.000ns| 1.054ns| N/A| 0| 0| 2| 0|
| erator_0_PLL0_CLK_OUT_3_ | | | | | | | |
| TS_clock_generator_0_clock_gen| 16.000ns| 8.600ns| N/A| 0| 0| 11042| 0|
| erator_0_PLL0_CLK_OUT_4_ | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
constraint does not cover any paths or that it has no requested value.
Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 5 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Loading device for application Rf_Device from file '5vlx50t.nph' in environment
c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.
INFO:ParHelpers:197 - Number of "Exact" mode Directed Routing Constraints: 128
INFO:ParHelpers:199 - All "EXACT" mode Directed Routing constrained nets successfully routed. The number of constraints
found: 128, number successful: 128
Total REAL time to PAR completion: 9 mins 1 secs
Total CPU time to PAR completion: 8 mins 19 secs
Peak Memory Usage: 653 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 9
Number of info messages: 4
Writing design to file system.ncd
PAR done!
#----------------------------------------------#
# Starting program post_par_trce
# trce -ise ../__xps/ise/system.ise -e 3 -xml system.twx system.ncd system.pcf
#----------------------------------------------#
Release 11.2 - Trace (nt)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file
<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file
<c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>
Loading device for application Rf_Device from file '5vfx70t.nph' in environment
c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.
"system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1
WARNING:ConstraintSystem:65 - Constraint <NET "PCIe_Bridge/Bridge_Clk" PERIOD =
8 ns HIGH 50%;> [system.pcf(65973)] overrides constraint <NET
"PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(65972)].
WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM
TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP "TNM_CLK0" TS_MC_CLK * 4;
ignored during timing analysis.
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more
information, see the TSI report. Please consult the Xilinx Command Line
Tools User Guide for information on generating a TSI report.
--------------------------------------------------------------------------------
Release 11.2 Trace (nt)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
trce -ise ../__xps/ise/system.ise -e 3 -xml system.twx system.ncd system.pcf
Design file: system.ncd
Physical constraint file: system.pcf
Device,speed: xc5vfx70t,-1 (PRODUCTION 1.65 2009-06-01, STEPPING
level 0)
Report level: error report
--------------------------------------------------------------------------------
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a
50 Ohm transmission line loading model. For the details of this model, and
for more information on accounting for different loading conditions, please
see the device datasheet.
Timing summary:
---------------
Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
Constraints cover 826342 paths, 18 nets, and 74598 connections
Design statistics:
Minimum period: 11.165ns (Maximum frequency: 89.566MHz)
Maximum path delay from/to any node: 7.812ns
Maximum net delay: 0.838ns
Maximum net skew: 0.608ns
Analysis completed Tue Jun 30 21:57:31 2009
--------------------------------------------------------------------------------
Generating Report ...
Number of warnings: 2
Number of info messages: 3
Total time: 1 mins 36 secs
xflow done!
touch __xps/system_routed
xilperl C:/devtools/Xilinx/11.1/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par
Analyzing implementation/system.par
*********************************************
Running Bitgen..
*********************************************
cd implementation; bitgen -w -f bitgen.ut system; cd ..
Release 11.2 - Bitgen L.46 (nt)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file
<C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file
<c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>
Loading device for application Rf_Device from file '5vfx70t.nph' in environment
c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.
"system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1
Opened constraints file system.pcf.
Tue Jun 30 21:58:01 2009
Running DRC.
WARNING:PhysDesignRules:1842 - One or more GTXs are being used in this design.
Evaluate the SelectIO-To-GTX Crosstalk section of the Virtex-5 RocketIO GTX
Transceiver User Guide to ensure that the design SelectIO usage meets the
guidelines to minimize the impact on GTX performance.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_w
rapper_i/icdrreset<0> is sourced by a combinatorial pin. This is not good
design practice. Use the CE pin to control the loading of data into the
flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
Ethernet_MAC/Ethernet_MAC/phy_tx_clk_i is sourced by a combinatorial pin.
This is not good design practice. Use the CE pin to control the loading of
data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal
<PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n<0>> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn<0>> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<xps_bram_if_cntlr_1_port_BRAM_Addr<30>> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<xps_bram_if_cntlr_1_port_BRAM_Addr<31>> is incomplete. The signal does not
drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull>
is incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:1269 - Dangling pins on
block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
qs[1].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not
used.
WARNING:PhysDesignRules:1273 - Dangling pins on
block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
qs[1].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF
Flip-flop but the SRVAL_Q1 set/reset value is not configured.
WARNING:PhysDesignRules:1269 - Dangling pins on
block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
qs[4].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not
used.
WARNING:PhysDesignRules:1273 - Dangling pins on
block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
qs[4].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF
Flip-flop but the SRVAL_Q1 set/reset value is not configured.
WARNING:PhysDesignRules:1269 - Dangling pins on
block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
qs[7].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not
used.
WARNING:PhysDesignRules:1273 - Dangling pins on
block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
qs[7].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF
Flip-flop but the SRVAL_Q1 set/reset value is not configured.
WARNING:PhysDesignRules:1269 - Dangling pins on
block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
qs[2].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not
used.
WARNING:PhysDesignRules:1273 - Dangling pins on
block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
qs[2].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF
Flip-flop but the SRVAL_Q1 set/reset value is not configured.
WARNING:PhysDesignRules:1269 - Dangling pins on
block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
qs[5].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not
used.
WARNING:PhysDesignRules:1273 - Dangling pins on
block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
qs[5].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF
Flip-flop but the SRVAL_Q1 set/reset value is not configured.
WARNING:PhysDesignRules:1269 - Dangling pins on
block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
qs[0].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not
used.
WARNING:PhysDesignRules:1273 - Dangling pins on
block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
qs[0].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF
Flip-flop but the SRVAL_Q1 set/reset value is not configured.
WARNING:PhysDesignRules:1269 - Dangling pins on
block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
qs[3].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not
used.
WARNING:PhysDesignRules:1273 - Dangling pins on
block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
qs[3].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF
Flip-flop but the SRVAL_Q1 set/reset value is not configured.
WARNING:PhysDesignRules:1269 - Dangling pins on
block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
qs[6].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not
used.
WARNING:PhysDesignRules:1273 - Dangling pins on
block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d
qs[6].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF
Flip-flop but the SRVAL_Q1 set/reset value is not configured.
DRC detected 0 errors and 24 warnings. Please see the previously displayed
individual error or warning messages for more details.
Creating bit map...
Saving bit stream in "system.bit".
Bitstream generation is complete.
Done!
Writing filter settings....
Done writing filter settings to:
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters
Done writing Tab View settings to:
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 237 - deprecated core for architecture 'virtex5fx'!
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 282 - deprecated core for architecture 'virtex5fx'!
Generating Block Diagram to Buffer
Generated Block Diagram SVG
At Local date and time: Sat Jul 04 20:43:06 2009
make -f system.make download started...
cp -f /cygdrive/c/devtools/Xilinx/11.1/EDK/sw/lib/ppc440/ppc440_bootloop.elf bootloops/ppc440_0.elf
*********************************************
Initializing BRAM contents of the bitstream
*********************************************
bitinit -p xc5vfx70tff1136-1 system.mhs -pe ppc440_0 bootloops/ppc440_0.elf \
-bt implementation/system.bit -o implementation/download.bit
bitinit version Xilinx EDK 11.2 Build EDK_LS3.47
Copyright (c) Xilinx Inc. 2002.
Parsing MHS File system.mhs...
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
251 - deprecated core for architecture 'virtex5fx'!
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
296 - deprecated core for architecture 'virtex5fx'!
Overriding IP level properties ...
Performing IP level DRCs on properties...
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
Address Map for Processor ppc440_0
(0b0000000000-0b0011111111) ppc440_0
(0000000000-0x0fffffff) DDR2_SDRAM ppc440_0_PPC440MC
(0x81000000-0x8100ffff) Ethernet_MAC plb_v46_0
(0x81400000-0x8140ffff) Push_Buttons_5Bit plb_v46_0
(0x81420000-0x8142ffff) LEDs_Positions plb_v46_0
(0x81440000-0x8144ffff) LEDs_8Bit plb_v46_0
(0x81460000-0x8146ffff) DIP_Switches_8Bit plb_v46_0
(0x81600000-0x8160ffff) IIC_EEPROM plb_v46_0
(0x81800000-0x8180ffff) xps_intc_0 plb_v46_0
(0x83600000-0x8360ffff) SysACE_CompactFlash plb_v46_0
(0x84000000-0x8400ffff) RS232_Uart_1 plb_v46_0
(0x85c00000-0x85c0ffff) PCIe_Bridge plb_v46_0
(0xc0000000-0xdfffffff) PCIe_Bridge plb_v46_0
(0xe0000000-0xefffffff) PCIe_Bridge plb_v46_0
(0xf8000000-0xf80fffff) SRAM plb_v46_0
(0xffffe000-0xffffffff) xps_bram_if_cntlr_1 plb_v46_0
INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_
01_a\data\ppc440_virtex5_v2_1_0.mpd line 175 - tool is overriding PARAMETER
C_SPLB0_P2P value to 0
Computing clock values...
INFO:EDK:1432 - Frequency for Top-Level Input Clock
'fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin' is not specified. Clock DRCs will not be
performed for IPs connected to that clock port, unless they are connected
through the clock generator IP.
INFO:EDK:1432 - Frequency for Top-Level Input Clock
'fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin' is not specified. Clock DRCs will not be
performed for IPs connected to that clock port, unless they are connected
through the clock generator IP.
INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER
C_PLBV46_NUM_MASTERS value to 1
INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER
C_PLBV46_NUM_SLAVES value to 12
INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER
C_PLBV46_MID_WIDTH value to 1
INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH
value to 128
INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 75 - tool is overriding
PARAMETER C_SPLB_DWIDTH value to 128
INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 76 - tool is overriding
PARAMETER C_SPLB_NUM_MASTERS value to 1
INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 80 - tool is overriding
PARAMETER C_SPLB_SMALLEST_MASTER value to 128
INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
\data\bram_block_v2_1_0.mpd line 69 - tool is overriding PARAMETER C_MEMSIZE
value to 0x2000
INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
\data\bram_block_v2_1_0.mpd line 70 - tool is overriding PARAMETER
C_PORT_DWIDTH value to 64
INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
\data\bram_block_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_NUM_WE
value to 8
INFO:EDK:1560 - IPNAME:xps_uartlite INSTANCE:RS232_Uart_1 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_01
_a\data\xps_uartlite_v2_1_0.mpd line 73 - tool is overriding PARAMETER
C_SPLB_DWIDTH value to 128
INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_8Bit -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH
value to 128
INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_Positions -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH
value to 128
INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:Push_Buttons_5Bit -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH
value to 128
INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:DIP_Switches_8Bit -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH
value to 128
INFO:EDK:1560 - IPNAME:xps_iic INSTANCE:IIC_EEPROM -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_iic_v2_01_a\da
ta\xps_iic_v2_1_0.mpd line 79 - tool is overriding PARAMETER C_SPLB_DWIDTH
value to 128
INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_
a\data\xps_mch_emc_v2_1_0.mpd line 82 - tool is overriding PARAMETER
C_SPLB_DWIDTH value to 128
INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_
a\data\xps_mch_emc_v2_1_0.mpd line 84 - tool is overriding PARAMETER
C_SPLB_SMALLEST_MASTER value to 128
INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
b\data\plbv46_pcie_v2_1_0.mpd line 86 - tool is overriding PARAMETER
C_MPLB_DWIDTH value to 128
INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
b\data\plbv46_pcie_v2_1_0.mpd line 87 - tool is overriding PARAMETER
C_MPLB_SMALLEST_SLAVE value to 128
INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
b\data\plbv46_pcie_v2_1_0.mpd line 89 - tool is overriding PARAMETER
C_SPLB_MID_WIDTH value to 1
INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
b\data\plbv46_pcie_v2_1_0.mpd line 90 - tool is overriding PARAMETER
C_SPLB_NUM_MASTERS value to 1
INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
b\data\plbv46_pcie_v2_1_0.mpd line 91 - tool is overriding PARAMETER
C_SPLB_SMALLEST_MASTER value to 128
INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
b\data\plbv46_pcie_v2_1_0.mpd line 95 - tool is overriding PARAMETER
C_SPLB_DWIDTH value to 128
INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER
C_PLBV46_NUM_MASTERS value to 1
INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER
C_PLBV46_NUM_SLAVES value to 1
INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER
C_PLBV46_MID_WIDTH value to 1
INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH
value to 128
INFO:EDK:1560 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ethernetlite_v
2_01_a\data\xps_ethernetlite_v2_1_0.mpd line 75 - tool is overriding
PARAMETER C_SPLB_DWIDTH value to 128
INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
\data\xps_sysace_v2_1_0.mpd line 72 - tool is overriding PARAMETER
C_SPLB_DWIDTH value to 128
INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
\data\xps_sysace_v2_1_0.mpd line 74 - tool is overriding PARAMETER
C_SPLB_MID_WIDTH value to 1
INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
\data\xps_sysace_v2_1_0.mpd line 75 - tool is overriding PARAMETER
C_SPLB_NUM_MASTERS value to 1
INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -
C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d
ata\xps_intc_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_SPLB_DWIDTH
value to 128
Checking platform address map ...
Initializing Memory...
Running Data2Mem with the following command:
data2mem -bm "implementation/system_bd" -bt "implementation/system.bit" -bd
"bootloops/ppc440_0.elf" tag ppc440_0 -o b implementation/download.bit
Memory Initialization completed successfully.
*********************************************
Downloading Bitstream onto the target board
*********************************************
impact -batch etc/download.cmd
Release 11.2 - iMPACT L.46 (nt)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
Preference Table
Name Setting
StartupClock Auto_Correction
AutoSignature False
KeepSVF False
ConcurrentMode False
UseHighz False
ConfigOnFailure Stop
UserLevel Novice
MessageLevel Detailed
svfUseTime false
SpiByteSwap Auto_Correction
AutoDetecting cable. Please wait.
Connecting to cable (Usb Port - USB21).
Checking cable driver.
Driver file xusb_xp2.sys found.
Driver version: src=2301, dest=2301.
Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS
13:58:07, version = 900.
Cable PID = 0008.
Max current requested during enumeration is 300 mA.
Type = 0x0005.
Cable Type = 3, Revision = 0.
Setting cable speed to 6 MHz.
Cable connection established.
Firmware version = 2401.
File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.
Firmware hex file version = 2401.
PLD file version = 200Dh.
PLD version = 200Dh.
Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6
INFO:iMPACT:1777 -
Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...
----------------------------------------------------------------------
----------------------------------------------------------------------
'1': : Manufacturer's ID = Xilinx xccace, Version : 0
----------------------------------------------------------------------
----------------------------------------------------------------------
'2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5
INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.
INFO:iMPACT:1777 -
Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...
INFO:iMPACT:501 - '1': Added Device xccace successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
'3': : Manufacturer's ID = Xilinx xcf32p, Version : 15
INFO:iMPACT:1777 -
Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...
INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15
----------------------------------------------------------------------
----------------------------------------------------------------------
done.
Elapsed time = 0 sec.
Elapsed time = 0 sec.
'5': Loading file 'implementation/download.bit' ...
INFO:iMPACT:1777 -
Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
done.
UserID read from the bitstream file = 0xFFFFFFFF.
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
Maximum TCK operating frequency for this device chain: 10000000.
Validating chain...
Boundary-scan chain validated successfully.
5: Device Temperature: Current Reading: 72.52 C, Min. Reading: 30.69 C, Max.
Reading: 74.49 C
5: VCCINT Supply: Current Reading: 0.993 V, Min. Reading: 0.993 V, Max.
Reading: 1.002 V
5: VCCAUX Supply: Current Reading: 2.496 V, Min. Reading: 2.493 V, Max.
Reading: 2.508 V
INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.
'5': Programming device...
Match_cycle = 2.
done.
'5': Reading status register contents...
CRC error : 0
Decryptor security set : 0
DCM locked : 1
DCI matched : 1
End of startup signal from Startup block : 1
status of GTS_CFG_B : 1
status of GWE : 1
status of GHIGH : 1
value of MODE pin M0 : 1
value of MODE pin M1 : 0
Value of MODE pin M2 : 1
Internal signal indicates when housecleaning is completed: 1
Value driver in from INIT pad : 1
Internal signal indicates that chip is configured : 1
Value of DONE pin : 1
Indicates when ID value written does not match chip ID: 0
Decryptor error Signal : 0
System Monitor Over-Temperature Alarm : 0
startup_state[18] CFG startup state machine : 0
startup_state[19] CFG startup state machine : 0
startup_state[20] CFG startup state machine : 1
E-fuse program voltage available : 0
SPI Flash Type[22] Select : 1
SPI Flash Type[23] Select : 1
SPI Flash Type[24] Select : 1
CFG bus width auto detection result : 0
CFG bus width auto detection result : 0
Reserved : 0
BPI address wrap around error : 0
IPROG pulsed : 0
read back crc error : 0
Indicates that efuse logic is busy : 0
Match_cycle = 2.
'5': Programmed successfully.
Elapsed time = 11 sec.
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
INFO:iMPACT:2219 - Status register values:
INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000
INFO:iMPACT:579 - '5': Completed downloading bit file to device.
INFO:iMPACT - '5': Programing completed successfully.
INFO:iMPACT - '5': Checking done pin....done.
Done!
At Local date and time: Sat Jul 04 20:43:42 2009
make -f system.make program started...
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygd
rive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/D
ev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/main.c -o RTOSDemo/executable.elf \
-mcpu=440 -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld -g -I./ppc440_0/include/ -I../../Source/include -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop -L./ppc440_0/lib/ \
-D GCC_PPC440 -mregnames
powerpc-eabi-size RTOSDemo/executable.elf
text data bss dec hex filename
53174 372 86528 140074 2232a RTOSDemo/executable.elf
Done!
start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/; exit;"
Writing filter settings....
Done writing filter settings to:
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters
Done writing Tab View settings to:
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 11.2 Build EDK_LS3.47
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 237 - deprecated core for architecture 'virtex5fx'!
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 282 - deprecated core for architecture 'virtex5fx'!
Generating Block Diagram to Buffer
Generated Block Diagram SVG
At Local date and time: Sun Jul 05 09:35:22 2009
make -f system.make hwclean started...
rm -f implementation/system.ngc
rm -f platgen.log
rm -f __xps/ise/_xmsgs/platgen.xmsgs
rm -f implementation/system.bmm
rm -f implementation/system.bit
rm -f implementation/system.ncd
rm -f implementation/system_bd.bmm
rm -f implementation/system_map.ncd
rm -f __xps/system_routed
rm -rf implementation synthesis xst hdl
rm -rf xst.srp system.srp
rm -f __xps/ise/_xmsgs/bitinit.xmsgs
Done!
At Local date and time: Sun Jul 05 09:35:36 2009
make -f system.make swclean started...
rm -rf ppc440_0/
rm -f libgen.log
rm -f __xps/ise/_xmsgs/libgen.xmsgs
rm -f RTOSDemo/executable.elf
Done!
Writing filter settings....
Done writing filter settings to:
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters
Done writing Tab View settings to:
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui
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