Subversion Repositories or1200_hp

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Release 11.1 Trace  (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.

C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise
C:/EDAptability/coremultiplier/reference/or1200_new/ise/ise_or1200_cm2/ise_or1200_cm2/ise_or1200_cm2.ise
-intstyle ise -v 3 -s 1 -fastpaths -xml or1200_top_cm2.twx or1200_top_cm2.ncd
-o or1200_top_cm2.twr or1200_top_cm2.pcf -ucf or1200_top_cm2.ucf

Design file:              or1200_top_cm2.ncd
Physical constraint file: or1200_top_cm2.pcf
Device,package,speed:     xc5vlx50,ff676,-1 (PRODUCTION 1.64 2009-03-03, STEPPING level 0)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: TS_clk_i = PERIOD TIMEGRP "clk_i" 0.5 ns HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 5987 timing errors detected. (5987 component switching limit errors)
 Minimum period is   2.400ns.
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Component Switching Limit Checks: TS_clk_i = PERIOD TIMEGRP "clk_i" 0.5 ns HIGH 50%;
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Slack: -1.900ns (period - (min high pulse limit / (high pulse / period)))
  Period: 0.500ns
  High pulse: 0.250ns
  High pulse limit: 1.200ns (Tospwh)
  Physical resource: or1200_du/dbg_ack_o/SR
  Logical resource: or1200_du/dbg_ack_o/SR
  Location pin: OLOGIC_X1Y162.SR
  Clock network: rst_i_IBUF
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Slack: -1.900ns (period - (min high pulse limit / (high pulse / period)))
  Period: 0.500ns
  High pulse: 0.250ns
  High pulse limit: 1.200ns (Tospwh)
  Physical resource: dwb_biu/wb_adr_o_10_1/SR
  Logical resource: dwb_biu/wb_adr_o_10_1/SR
  Location pin: OLOGIC_X0Y188.SR
  Clock network: rst_i_IBUF
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Slack: -1.900ns (period - (min high pulse limit / (high pulse / period)))
  Period: 0.500ns
  High pulse: 0.250ns
  High pulse limit: 1.200ns (Tospwh)
  Physical resource: dwb_biu/wb_adr_o_11_1/SR
  Logical resource: dwb_biu/wb_adr_o_11_1/SR
  Location pin: OLOGIC_X0Y187.SR
  Clock network: rst_i_IBUF
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================================================================================
Timing constraint: TS_clk_i_cml_1 = PERIOD TIMEGRP "clk_i_cml_1" 0.5 ns HIGH 
50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 3922 timing errors detected. (3922 component switching limit errors)
 Minimum period is   2.400ns.
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Component Switching Limit Checks: TS_clk_i_cml_1 = PERIOD TIMEGRP "clk_i_cml_1" 0.5 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: -1.900ns (period - (min high pulse limit / (high pulse / period)))
  Period: 0.500ns
  High pulse: 0.250ns
  High pulse limit: 1.200ns (Tospwh)
  Physical resource: or1200_pic/intr_cml_1_1/SR
  Logical resource: or1200_pic/intr_cml_1_1/SR
  Location pin: OLOGIC_X0Y74.SR
  Clock network: or1200_pic/intr10
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Slack: -0.500ns (period - (min low pulse limit / (low pulse / period)))
  Period: 0.500ns
  Low pulse: 0.250ns
  Low pulse limit: 0.500ns (Tockpwl)
  Physical resource: or1200_pic/intr_cml_1_1/CLK
  Logical resource: or1200_pic/intr_cml_1_1/CK
  Location pin: OLOGIC_X0Y74.CLK
  Clock network: clk_i_cml_1_BUFGP
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Slack: -0.500ns (period - (min high pulse limit / (high pulse / period)))
  Period: 0.500ns
  High pulse: 0.250ns
  High pulse limit: 0.500ns (Tockpwh)
  Physical resource: or1200_pic/intr_cml_1_1/CLK
  Logical resource: or1200_pic/intr_cml_1_1/CK
  Location pin: OLOGIC_X0Y74.CLK
  Clock network: clk_i_cml_1_BUFGP
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2 constraints not met.


Data Sheet report:
-----------------
No constraints were found to generate data for the Data Sheet Report section.
Use the Advanced Analysis (-a) option or generate global constraints for each
clock, its pad to setup and clock to pad paths, and a pad to pad constraint.

Timing summary:
---------------

Timing errors: 9909  Score: 4391040  (Setup/Max: 0, Hold: 0, Component Switching Limit: 4391040)

Constraints cover 0 paths, 0 nets, and 0 connections

Design statistics:
   Minimum period:   2.400ns{1}   (Maximum frequency: 416.667MHz)


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Thu Oct 21 14:53:27 2010 
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Trace Settings:
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Trace Settings 

Peak Memory Usage: 302 MB