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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200 Top Level                                            ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  OR1200 Top Level                                            ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9  2001/10/14 13:12:10  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.4  2001/08/13 03:36:20  lampret
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
//
// Revision 1.3  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/22 03:31:54  lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1  2001/07/20 00:46:21  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
module or1200(
	// System
	clk, rst, pic_ints, clkdiv_by_2,
 
	// Instruction WISHBONE INTERFACE
	iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,
	iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o,
 
	// Data WISHBONE INTERFACE
	dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,
	dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o,
 
	// External Debug Interface
	dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
	dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o,
 
	// Power Management
	pm_clksd, pm_cpustall, pm_dc_gate, pm_ic_gate, pm_dmmu_gate, 
	pm_immu_gate, pm_tt_gate, pm_cpu_gate, pm_wakeup, pm_lvolt
 
);
 
parameter dw = `OPERAND_WIDTH;
parameter aw = `OPERAND_WIDTH;
parameter ppic_ints = `PIC_INTS;
 
//
// I/O
//
 
//
// System
//
input			clk;
input			rst;
input			clkdiv_by_2;
input	[ppic_ints-1:0]	pic_ints;
 
//
// Instruction WISHBONE interface
//
input			iwb_clk_i;	// clock input
input			iwb_rst_i;	// reset input
input			iwb_ack_i;	// normal termination
input			iwb_err_i;	// termination w/ error
input			iwb_rty_i;	// termination w/ retry
input	[dw-1:0]	iwb_dat_i;	// input data bus
output			iwb_cyc_o;	// cycle valid output
output	[aw-1:0]	iwb_adr_o;	// address bus outputs
output			iwb_stb_o;	// strobe output
output			iwb_we_o;	// indicates write transfer
output	[3:0]		iwb_sel_o;	// byte select outputs
output	[dw-1:0]	iwb_dat_o;	// output data bus
 
//
// Data WISHBONE interface
//
input			dwb_clk_i;	// clock input
input			dwb_rst_i;	// reset input
input			dwb_ack_i;	// normal termination
input			dwb_err_i;	// termination w/ error
input			dwb_rty_i;	// termination w/ retry
input	[dw-1:0]	dwb_dat_i;	// input data bus
output			dwb_cyc_o;	// cycle valid output
output	[aw-1:0]	dwb_adr_o;	// address bus outputs
output			dwb_stb_o;	// strobe output
output			dwb_we_o;	// indicates write transfer
output	[3:0]		dwb_sel_o;	// byte select outputs
output	[dw-1:0]	dwb_dat_o;	// output data bus
 
//
// External Debug Interface
//
input			dbg_stall_i;	// External Stall Input
input	[dw-1:0]	dbg_dat_i;	// External Data Input
input	[aw-1:0]	dbg_adr_i;	// External Address Input
input	[2:0]		dbg_op_i;	// External Operation Select Input
input			dbg_ewt_i;	// External Watchpoint Trigger Input
output	[3:0]		dbg_lss_o;	// External Load/Store Unit Status
output	[1:0]		dbg_is_o;	// External Insn Fetch Status
output	[10:0]		dbg_wp_o;	// Watchpoints Outputs
output			dbg_bp_o;	// Breakpoint Output
output	[dw-1:0]	dbg_dat_o;	// External Data Output
 
//
// Power Management
//
input			pm_cpustall;
output	[3:0]		pm_clksd;
output			pm_dc_gate;
output			pm_ic_gate;
output			pm_dmmu_gate;
output			pm_immu_gate;
output			pm_tt_gate;
output			pm_cpu_gate;
output			pm_wakeup;
output			pm_lvolt;
 
 
//
// Internal wires and regs
//
 
//
// DC to BIU
//
wire			dcbiu_rdy;
wire	[dw-1:0] 	dcbiu_from_biu;
wire	[dw-1:0] 	dcbiu_to_biu;
wire	[aw-1:0] 	dcbiu_addr;
wire			dcbiu_read;
wire			dcbiu_write;
wire	[3:0]		dcbiu_sel;
 
//
// IC to BIU
//
wire			icbiu_rdy;
wire	[dw-1:0]	icbiu_from_biu;
wire	[aw-1:0]	icbiu_addr;
wire			icbiu_read;
wire	[3:0]		icbiu_sel;
 
//
// CPU's SPR access to various RISC units (shared wires)
//
wire			supv;
wire	[aw-1:0]	spr_addr;
wire	[dw-1:0]	spr_dat_cpu;
wire	[31:0]		spr_cs;
wire			spr_we;
 
//
// DMMU and CPU
//
wire			dmmu_en;
wire			dmmuexcept_miss;
wire			dmmuexcept_fault;
wire	[31:0]		spr_dat_dmmu;
 
//
// DMMU and DC
//
wire	[aw-1:0]	dcdmmu_paddr;
 
//
// DC and CPU's LSU
//
wire			dclsu_stall;
wire			dclsu_unstall;
wire	[aw-1:0]	dclsu_addr;
wire	[aw-1:0]	dclsu_from_dc;
wire	[aw-1:0]	dclsu_to_dc;
wire	[`LSUOP_WIDTH-1:0] dclsu_lsuop;
wire			dc_en;
 
//
// IMMU and CPU
//
wire			immu_en;
wire			immuexcept_miss;
wire			immuexcept_fault;
wire	[31:0]		spr_dat_immu;
 
//
// IC and CPU's ifetch
//
wire			icfetch_stall;
wire	[aw-1:0]	icfetch_addr;
wire	[dw-1:0]	icfetch_dataout;
wire	[`FETCHOP_WIDTH-1:0] icfetch_op;
wire			ic_en;
 
//
// IMMU and IC
//
wire	[aw-1:0]	icimmu_paddr;
 
//
// Connection between CPU and PIC
//
wire	[dw-1:0]	spr_dat_pic;
wire			pic_wakeup;
wire			int_low;
wire			int_high;
wire			int_high_tt;
 
//
// Connection between CPU and PM
//
wire	[dw-1:0]	spr_dat_pm;
 
//
// CPU and TT
//
wire	[dw-1:0]	spr_dat_tt;
wire			tt_int;
 
//
// Trace port and caches/MMUs
//
wire	[dw-1:0]	spr_dat_du;
wire			du_stall;
wire	[dw-1:0]	du_addr;
wire	[dw-1:0]	du_dat_du;
wire			du_read;
wire			du_write;
wire	[`EXCEPT_WIDTH-1:0] du_except;
 
wire			ex_freeze;
wire	[`BRANCHOP_WIDTH-1:0]	branch_op;
 
//
// Assignments
//
assign int_high_tt = int_high | tt_int;
 
//
// Instantiation of Instruction WISHBONE BIU
//
wb_biu iwb_biu(
	// WISHBONE interface
	.wb_clk_i(iwb_clk_i),
	.wb_rst_i(iwb_rst_i),
	.wb_ack_i(iwb_ack_i),
	.wb_err_i(iwb_err_i),
	.wb_rty_i(iwb_rty_i),
	.wb_dat_i(iwb_dat_i),
	.wb_cyc_o(iwb_cyc_o),
	.wb_adr_o(iwb_adr_o),
	.wb_stb_o(iwb_stb_o),
	.wb_we_o(iwb_we_o),
	.wb_sel_o(iwb_sel_o),
	.wb_dat_o(iwb_dat_o),
 
	// Internal RISC bus
	.biu_to_biu(32'b0),
	.biu_addr(icbiu_addr),
	.biu_read(icbiu_read),
	.biu_write(1'b0),
	.biu_rdy(icbiu_rdy),
	.biu_from_biu(icbiu_from_biu),
	.biu_sel(icbiu_sel)
);
 
//
// Instantiation of Data WISHBONE BIU
//
wb_biu dwb_biu(
	// WISHBONE interface
	.wb_clk_i(dwb_clk_i),
	.wb_rst_i(dwb_rst_i),
	.wb_ack_i(dwb_ack_i),
	.wb_err_i(dwb_err_i),
	.wb_rty_i(dwb_rty_i),
	.wb_dat_i(dwb_dat_i),
	.wb_cyc_o(dwb_cyc_o),
	.wb_adr_o(dwb_adr_o),
	.wb_stb_o(dwb_stb_o),
	.wb_we_o(dwb_we_o),
	.wb_sel_o(dwb_sel_o),
	.wb_dat_o(dwb_dat_o),
 
	// Internal RISC bus
	.biu_to_biu(dcbiu_to_biu),
	.biu_addr(dcbiu_addr),
	.biu_read(dcbiu_read),
	.biu_write(dcbiu_write),
	.biu_rdy(dcbiu_rdy),
	.biu_from_biu(dcbiu_from_biu),
	.biu_sel(dcbiu_sel)
);
 
//
// Instantiation of IMMU
//
immu immu(
	// Rst and clk
	.clk(clk),
	.rst(rst),
 
	// Fetch i/f
	.immu_en(immu_en),
	.supv(supv),
	.immufetch_vaddr(icfetch_addr),
	.immufetch_op(icfetch_op),
	.immufetch_stall(),
 
	// Except I/F
	.immuexcept_miss(immuexcept_miss),
	.immuexcept_fault(immuexcept_fault),
 
	// SPR access
	.spr_cs(spr_cs[`SPR_GROUP_IMMU]),
	.spr_write(spr_we),
	.spr_addr(spr_addr),
	.spr_dat_i(spr_dat_cpu),
	.spr_dat_o(spr_dat_immu),
 
	// IC i/f
	.icimmu_paddr(icimmu_paddr)
);
 
//
// Instantiation of Instruction Cache
//
ic ic(
	.clk(clk),
	.rst(rst),
	.clkdiv_by_2(clkdiv_by_2),
 
	// These connect IC to CPU's ifetch
	.icfetch_addr(icimmu_paddr),
	.icfetch_op(icfetch_op),
	.icfetch_dataout(icfetch_dataout),
	.icfetch_stall(icfetch_stall),
	.ic_en(ic_en),
 
	// SPR access
	.spr_cs(spr_cs[`SPR_GROUP_IC]),
	.spr_write(spr_we),
	.spr_dat_i(spr_dat_cpu),
 
	// These connect IC to BIU
	.icbiu_rdy(icbiu_rdy),
	.icbiu_datain(icbiu_from_biu),
	.icbiu_addr(icbiu_addr),
	.icbiu_read(icbiu_read),
	.icbiu_sel(icbiu_sel)
);
 
//
// Instantiation of Instruction Cache
//
cpu cpu(
	.clk(clk),
	.rst(rst),
 
	// Connection IC and IFETCHER inside CPU
	.ic_insn(icfetch_dataout),
	.ic_addr(icfetch_addr),
	.ic_stall(icfetch_stall),
	.ic_fetchop(icfetch_op),
	.ic_en(ic_en),
 
	// Connection CPU to external Trace port
	.ex_freeze(ex_freeze),
	.branch_op(branch_op),
	.du_stall(du_stall),
	.du_addr(du_addr),
	.du_dat_du(du_dat_du),
	.du_read(du_read),
	.du_write(du_write),
	.du_except(du_except),
 
	// Connection IMMU and CPU internally
	.immu_en(immu_en),
	.immuexcept_miss(immuexcept_miss),
	.immuexcept_fault(immuexcept_fault),
 
	// Connection DMMU and CPU internally
	.dmmu_en(dmmu_en),
	.dmmuexcept_miss(dmmuexcept_miss),
	.dmmuexcept_fault(dmmuexcept_fault),
 
	// Connection DC and CPU's LSU
	.dclsu_stall(dclsu_stall),
	.dclsu_unstall(dclsu_unstall),
	.dclsu_addr(dclsu_addr),
	.dclsu_datain(dclsu_from_dc),
	.dclsu_dataout(dclsu_to_dc),
	.dclsu_lsuop(dclsu_lsuop),
	.dc_en(dc_en),
 
	// Connection PIC and CPU's EXCEPT
	.int_high(int_high_tt),
	.int_low(int_low),
 
	// SPRs
	.supv(supv),
	.spr_addr(spr_addr),
	.spr_dataout(spr_dat_cpu),
	.spr_dat_pic(spr_dat_pic),
	.spr_dat_tt(spr_dat_tt),
	.spr_dat_pm(spr_dat_pm),
	.spr_dat_dmmu(spr_dat_dmmu),
	.spr_dat_immu(spr_dat_immu),
	.spr_dat_du(spr_dat_du),
	.spr_cs(spr_cs),
	.spr_we(spr_we)
);
 
//
// Instantiation of DMMU
//
dmmu dmmu(
	// Rst and clk
	.clk(clk),
	.rst(rst),
 
	// LSU i/f
	.dmmu_en(dmmu_en),
	.supv(supv),
	.dmmulsu_vaddr(dclsu_addr),
	.dmmulsu_lsuop(dclsu_lsuop),
	.dmmulsu_stall(),
 
	// Except I/F
	.dmmuexcept_miss(dmmuexcept_miss),
	.dmmuexcept_fault(dmmuexcept_fault),
 
	// SPR access
	.spr_cs(spr_cs[`SPR_GROUP_DMMU]),
	.spr_write(spr_we),
	.spr_addr(spr_addr),
	.spr_dat_i(spr_dat_cpu),
	.spr_dat_o(spr_dat_dmmu),
 
	// DC i/f
	.dcdmmu_paddr(dcdmmu_paddr)
);
 
//
// Instantiation of Data Cache
//
dc dc(
	.clk(clk),
	.rst(rst),
	.clkdiv_by_2(clkdiv_by_2),
 
	// These connect DC to CPU's LSU
	.dclsu_addr(dcdmmu_paddr),
	.dclsu_lsuop(dclsu_lsuop),
	.dclsu_datain(dclsu_to_dc),
	.dclsu_dataout(dclsu_from_dc),
	.dclsu_stall(dclsu_stall),
	.dclsu_unstall(dclsu_unstall),
	.dc_en(dc_en),
 
	// SPR access
	.spr_cs(spr_cs[`SPR_GROUP_DC]),
	.spr_write(spr_we),
	.spr_dat_i(spr_dat_cpu),
 
	// These connect DC to BIU
	.dcbiu_rdy(dcbiu_rdy),
	.dcbiu_datain(dcbiu_from_biu),
	.dcbiu_dataout(dcbiu_to_biu),
	.dcbiu_addr(dcbiu_addr),
	.dcbiu_read(dcbiu_read),
	.dcbiu_write(dcbiu_write),
	.dcbiu_sel(dcbiu_sel)
);
 
//
// Instantiation of Debug Unit
//
du du(
	// RISC Internal Interface
	.clk(clk),
	.rst(rst),
	.dclsu_lsuop(dclsu_lsuop),
	.icfetch_op(icfetch_op),
	.ex_freeze(ex_freeze),
	.branch_op(branch_op),
 
	// DU's access to SPR unit
	.du_stall(du_stall),
	.du_addr(du_addr),
	.du_dat_i(spr_dat_cpu),
	.du_dat_o(du_dat_du),
	.du_read(du_read),
	.du_write(du_write),
	.du_except(du_except),
 
	// Access to DU's SPRs
	.spr_cs(spr_cs[`SPR_GROUP_DU]),
	.spr_write(spr_we),
	.spr_addr(spr_addr),
	.spr_dat_i(spr_dat_cpu),
	.spr_dat_o(spr_dat_du),
 
	// External Debug Interface
	.dbg_stall_i(dbg_stall_i),
	.dbg_dat_i(dbg_dat_i),
	.dbg_adr_i(dbg_adr_i),
	.dbg_op_i(dbg_op_i),
	.dbg_ewt_i(dbg_ewt_i),
	.dbg_lss_o(dbg_lss_o),
	.dbg_is_o(dbg_is_o),
	.dbg_wp_o(dbg_wp_o),
	.dbg_bp_o(dbg_bp_o),
	.dbg_dat_o(dbg_dat_o)
);
 
//
// Programmable interrupt controller
//
pic pic(
	// RISC Internal Interface
	.clk(clk),
	.rst(rst),
	.spr_cs(spr_cs[`SPR_GROUP_PIC]),
	.spr_write(spr_we),
	.spr_addr(spr_addr),
	.spr_dat_i(spr_dat_cpu),
	.spr_dat_o(spr_dat_pic),
	.pic_wakeup(pic_wakeup),
	.int_low(int_low), 
	.int_high(int_high),
 
	// PIC Interface
	.pic_int(pic_ints)
);
 
//
// Instantiation of Tick timer
//
tt tt(
	// RISC Internal Interface
	.clk(clk),
	.rst(rst),
	.spr_cs(spr_cs[`SPR_GROUP_TT]),
	.spr_write(spr_we),
	.spr_addr(spr_addr),
	.spr_dat_i(spr_dat_cpu),
	.spr_dat_o(spr_dat_tt),
	.int(tt_int)
);
 
//
// Instantiation of Power Management
//
pm pm(
	// RISC Internal Interface
	.clk(clk),
	.rst(rst),
	.pic_wakeup(pic_wakeup),
	.spr_write(spr_we),
	.spr_addr(spr_addr),
	.spr_dat_i(spr_dat_cpu),
	.spr_dat_o(spr_dat_pm),
 
	// Power Management Interface
	.pm_clksd(pm_clksd),
	.pm_cpustall(pm_cpustall),
	.pm_dc_gate(pm_dc_gate),
	.pm_ic_gate(pm_ic_gate),
	.pm_dmmu_gate(pm_dmmu_gate),
	.pm_immu_gate(pm_immu_gate),
	.pm_tt_gate(pm_tt_gate),
	.pm_cpu_gate(pm_cpu_gate),
	.pm_wakeup(pm_wakeup),
	.pm_lvolt(pm_lvolt)
);
 
 
endmodule