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[/] [or1k/] [tags/] [stable/] [mp3/] [rtl/] [verilog/] [xfpga_defines.v] - Rev 1765
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////////////////////////////////////////////////////////////////////// //// //// //// MP3 demo Definitions //// //// //// //// This file is part of the MP3 demo application //// //// http://www.opencores.org/cores/or1k/mp3/ //// //// //// //// Description //// //// DEfine target technology etc. Right now FIFOs are available //// //// only for Xilinx Virtex FPGAs. (TARGET_VIRTEX) //// //// //// //// To Do: //// //// - nothing really //// //// //// //// Author(s): //// //// - Damjan Lampret, damjan.lampret@opencores.org //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2001 Authors //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: not supported by cvs2svn $ // // Define to target to Xilinx Virtex // `define TARGET_VIRTEX