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https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk
Subversion Repositories pcie_sg_dma
[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [ipcore_dir_ISE12.3/] [v6_mBuf_128x72.veo] - Rev 11
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// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
v6_mBuf_128x72 YourInstanceName (
.clk(clk),
.rst(rst),
.din(din), // Bus [71 : 0]
.wr_en(wr_en),
.rd_en(rd_en),
.dout(dout), // Bus [71 : 0]
.full(full),
.empty(empty),
.prog_full(prog_full));
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file v6_mBuf_128x72.v when simulating
// the core, v6_mBuf_128x72. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".