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https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk
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[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MyUserLogic/] [UserLogic_00/] [top_level_1_PCIe_UserLogic_00_USER_LOGIC/] [sysgen/] [icon_1_06_a_87e2f476e984e565.vhd] - Rev 13
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------------------------------------------------------------------------------- -- Copyright (c) 2012 Xilinx, Inc. -- All Rights Reserved ------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 13.3 -- \ \ Application: XILINX CORE Generator -- / / Filename : icon_1_06_a_87e2f476e984e565.vhd -- /___/ /\ Timestamp : Tue Feb 07 11:26:21 ora solare Europa occidentale 2012 -- \ \ / \ -- \___\/\___\ -- -- Design Name: VHDL Synthesis Wrapper ------------------------------------------------------------------------------- -- This wrapper is used to integrate with Project Navigator and PlanAhead LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY icon_1_06_a_87e2f476e984e565 IS port ( CONTROL0: inout std_logic_vector(35 downto 0)); END icon_1_06_a_87e2f476e984e565; ARCHITECTURE icon_1_06_a_87e2f476e984e565_a OF icon_1_06_a_87e2f476e984e565 IS BEGIN END icon_1_06_a_87e2f476e984e565_a;