URL
https://opencores.org/ocsvn/plb2wbbridge/plb2wbbridge/trunk
Subversion Repositories plb2wbbridge
[/] [plb2wbbridge/] [trunk/] [systems/] [test_system_sim/] [wb_irqs/] [simulation/] [test_cases/] [irq_tests/] [transfers.bfl] - Rev 2
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set_alias(PART = 1)set_alias(SUBPART = 2)set_alias(SUBSUBPART = 3)----------------------------------- 32-Bit Master --set_device(path=/system_tb/dut/plb_bfm_master_32/plb_bfm_master_32/master,device_type=plb_master)configure(msize=00)mem_update(addr=00010000,data=80000000)mem_update(addr=0001000c,data=80000000)wait( level=PART )-- the first irq was risedread ( addr=0001000c, size=0000, be=1111 )-- clear the bridge-irqwrite ( addr=00010000, size=0000, be=1111 )-- there should be a second irq (rised directly after the first)mem_update(addr=0001000c,data=20000000)read ( addr=0001000c, size=0000, be=1111 )-- clear the bridge-irqwrite ( addr=00010000, size=0000, be=1111 )mem_update(addr=00010000,data=80000000)mem_update(addr=0001000c,data=40000000)wait( level=PART )read ( addr=00010000, size=0000, be=1111 )read ( addr=0001000c, size=0000, be=1111 )mem_update(addr=00010000,data=00000000)write ( addr=00010000, size=0000, be=1111 )mem_update(addr=00010000,data=80000000)mem_update(addr=0001000c,data=20000000)wait( level=PART )read ( addr=00010000, size=0000, be=1111 )read ( addr=0001000c, size=0000, be=1111 )mem_update(addr=00010000,data=00000000)write ( addr=00010000, size=0000, be=1111 )mem_update(addr=00010000,data=80000000)mem_update(addr=0001000c,data=10000000)wait( level=PART )read ( addr=0001000c, size=0000, be=1111 )mem_update(addr=00010000,data=00000000)write ( addr=00010000, size=0000, be=1111 )