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[/] [pss/] [trunk/] [pss/] [hdl/] [pss/] [zpu_uc/] [motherblock/] [pss_edge_detector.v] - Rev 5
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/* PSS Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru> All rights reserved. Version 0.99 The FreeBSD license Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ module pss_edge_detector ( input clk_i, rst_i, input in, output reg out ); reg edge_inv; reg inbuf0, inbuf1, inbuf2; always @(posedge in, posedge rst_i) begin if (rst_i) edge_inv <= 1'b0; else edge_inv <= ~edge_inv; end always @(posedge clk_i) begin if (rst_i) begin inbuf0 <= 1'b0; inbuf1 <= 1'b0; inbuf2 <= 1'b0; out <= 1'b0; end else begin inbuf0 <= edge_inv; inbuf1 <= inbuf0; inbuf2 <= inbuf1; if (inbuf1 != inbuf2) out <= 1'b1; else out <= 1'b0; end end endmodule