Subversion Repositories qaz_libs

//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////

module
  riffa_chn_tx
  #(
    N // data bus width in bytes
  )
  (
    riffa_chnl_if chnl_bus,
    input tx_ready,
    input tx_done,
    output acked,
    output reg [30:0] tx_index,
    input tx_last,
    input [31:0] tx_len,
    input [30:0] tx_off,

    input clk,
    input reset
  );

  // --------------------------------------------------------------------
  //
  riffa_chnl_tx_fsm
    riffa_chnl_tx_fsm_i
    (
      .tx(chnl_bus.tx),
      .tx_ack(chnl_bus.tx_ack),
      .*
    );


  // --------------------------------------------------------------------
  //
  always_ff @(posedge clk)
    if(reset | ~chnl_bus.tx | tx_done)
      tx_index <= 0;
    else if(chnl_bus.tx_data_valid & chnl_bus.tx_data_ren)
      tx_index <= tx_index + (N/4); // increment by 32 bit words


// --------------------------------------------------------------------
//
endmodule